Parallel Input/Output

Textbook Chapter 14 – General-Purpose Input/Output

STM32F407 Reference Manual, Chapter 8 (general-purpose IOs)
 Computer Architecture (Chapter 1)
Von-Neumann Harvard
Instructions and data are stored in Data and instructions are stored
the same memory. into separate memories.

I/O
Peripherals
I/O Address
Peripherals Data
Address
Data

Memory-mapped I/O : I/O peripherals assigned addresses in memory address map

Isolated I/O : I/O peripherals have a separate (isolated) address map
Embedded system components

STM32F407VG
Arm Cortex-M4 based system
Microcontroller System bus
ARM® CortexTM-M
processor
Input
PPB ports
Internal
Advanced
peripherals High-perf Output
Bus ports
Instructions
Flash ROM Data
ICode bus DCode bus RAM

 ARM Cortex-M4 processor

 Harvard architecture
Different busses for instructions and data
 RISC machine
Pipelining effectively provides single cycle operation for many
instructions
Thumb-2 configuration employs both 16 and 32 bit instructions

Bard, Gerstlauer, Valvano,Yerraballi

Arm Cortex-M4 processor
Interrupt
Signals
Interrupt
Control
ST-Link
Debugger
(on the board)

Program memory Data memory I/O devices

Arm Cortex-M4
memory map 4

STM32F407VG Microcontroller
1. Flash memory @0x08000000
2. SRAM @0x20000000
3. ST peripheral modules*
4. Cortex-M4 peripherals*
*Memory-Mapped I/O

1
 ROM
CPU
ST Microelectronics
STM32F40x RAM
microcontroller
General-Purpose
Inputs/Outputs
(GPIO)

Other
Peripheral
Other Modules
Peripheral
Modules
 STM32F407 flash memory
Main memory = 1Mbyte = 7x128K + 1x64K + 4x16K “sectors”
(Commands erase one “sector” or entire memory)

Program code,
Constant data

Separate,
one-time
programmable
STM32F407 SRAM blocks
 Byte, half-word, and word addressable
 192Kbytes of system SRAM
 112Kbyte and 16Kbyte blocks at 0x2000_0000
 Accessible by all AHB masters
 64Kbyte block at 0x1000_0000
 Accessible by CPU only via D-bus
 Supports concurrent SRAM accesses to separate blocks
 4Kbytes of battery-backed-up SRAM
 Configure with control registers
 Input/Output (I/O) Overview
 Issues
 Device selection: I/O addressing/address decoding
 Data transfer: amount, rate, to/from device
 Synchronization: CPU and external device
 Bus structures
 Links: Internal bus, system bus, data link
 Memory-mapped I/O
 Synchronization
 Programmed I/O
 Interrupt-driven I/O
 DMA (Direct Memory Access) I/O
Interface between CPU and external device
 “Device” may include digital and/or non-digital components.
 Two paths: CPU-to-interface; interface-to-device
 Can be different data widths and speeds (data rates)
 Might not be ready “at the same time”
 Typical digital interface to CPU is via addressable registers
 Registers assigned memory-mapped (or isolated I/O) addresses

Interface
control
reg

mechanism
CPU data
System bus reg Data “Device”
link

status
reg
 Simple input: on/off switch
+3.3V +3.3V
TM4C TM4C
10kΩ
s Input port t Input port
10kΩ
Negative logic Positive logic

Negative Logic s Positive Logic t

– pressed, 0V, false – pressed, 3.3V, true
– not pressed, 3.3V, true – not pressed, 0V, false
+3.3V +3.3V +3.3V +3.3V
TM4C TM4C TM4C TM4C
10kΩ 10kΩ
3.3V 0V
s Input port s Input port t Input port t Input port
0.0V 3.3V
10kΩ 10kΩ
Pressed Not pressed Pressed Not pressed

Bard, Gerstlauer,
Valvano, Yerraballi
Example – 10-key matrix keypad
1
Drive (output pins) 0
1
1
Uses both input
and output pins.
1

Read (input pins) 0

Pull-up Pressed
10K
Resistors Key
+3v
 Simple output: LED
anode (+)

anode cathode
cathode (-)
“big voltage connects to big pin”

Current
high LM3S +3.3V
2 + a Out R
I I or 1mA
R 1mA TM4C
(mA) 1 - k LM3S LED
or
TM4C LED
voltage low
0 Out
1.5 1.6 1.7
V (volts)
(a) LED curve (b) Positive logic interface (c) Negative logic interface

Bard, Gerstlauer,
Valvano, Yerraballi
LED interfaces
Positive logic, low current Positive logic, high current
high +5V
Out TM4C 7405 10mA
R 2mA or 7406 R
TM4C +5V LED
LED high
Out 0.5V
PF2

Negative logic, low current Negative logic, high current

+5V
TM4C 3.3 V TM4C 10mA
R 7407 R
2mA +5V LED
LED low
Out 0.5V
Out
low
7-segment LED/LCD display
 May use parallel or multiplexed port outputs.
a a

b b
f f
g g

Common anode or c c
Common cathode e e

d d

Select digit

Data[6:0]
To LEDs a-g
 Discovery board button and LEDs
PAx = port GPIOA pin PDx = port GPIOD pin

LED3
 The user button is positive logic LED4 LED5
 Uses external pull-down resistor (outside the uC)
LED6
 Reset (black button) – NRST pin
 LED3-LED6 are positive logic
 LED7 (USB OTG, Vbus) – PA9
 LED8 (USB OTG, overcurrent) – PD5
 LED1 – USB communication From Discovery Board
 LED2 – 3.3v power User Manual
 Parallel input/output ports
 Parallel port => multiple bits read/written in parallel by the
CPU
 Parallel input port = portal through which a CPU can access
information FROM an external device
 Parallel output port = portal through which a CPU can send
information TO an external device
 Multiple I/O ports are contained in the most microcontrollers
 Some microcontrollers allow for additional I/O ports to be added
via “expansion buses”
 Each port is configured and accessed via one or more registers
 Each register is assigned a unique memory address
 CPU reads/writes data via port data registers
 Mode Register (or data direction register) for each port
determines whether each pin is input or output
 I/O Ports and Control Registers
Read from port address
GPIOA_IDR
n n
Input data
Processor
n n
DQ Input/Output Port

GPIOA_ODR Write to port address

Output data
Direction bits
n 1 means output
DQ 0 means input
GPIOA_MODER
Bus Write to port direction register

 The input/output direction of a bidirectional port is specified by its “mode”

register (sometimes called “data direction” register)
 GPIOx_MODER : designate each pin as input, output, analog, or
“alternate function”

Question:What if the program reads from GPIOA_ODR?

Bard, Gerstlauer,
Valvano, Yerraballi
STM32F4xx microcontroller
General-Purpose I/O (GPIO) ports
 Up to 144 GPIO pins, individually configurable
 # GPIO ports varies among microcontroller parts
 Each port (GPIOA through GPIOI) comprises 16 GPIO pins
 Pin options (each pin configurable via GPIO registers):
 Output: push-pull or open-drain+pull-up/down + selectable speed
 Input: floating, pull-up/down
 Analog: input or output
 Alternate functions: up to 16 per pin
 Data to/from peripheral functions (Timers, I2C/SPI, USART, USB, etc.)
 Digital data input/output via GPIO registers
 Input data reg. (IDR) – parallel (16-bit) data from pins
 Output data reg. (ODR) – parallel (16-bit) data to pins
 Bit set/reset registers (BSRR) for bitwise control of output pins
STM32F4xx GPIO pin structure
Analog IO

Alt. Function

PIN
IDR

BSRR
ODR

Alt. Function
GPIO “mode” register
 GPIOx_MODER selects operating mode for each pin
x = A…I (GPIOA, GPIOB, …, GPIOI)
 2 bits per pin: 31 7 6 5 4 3 2 1 0
00 – Input mode (reset state): … Pin 3 Pin 2 Pin 1 Pin 0
Pin value captured in IDR every bus clock (through Schmitt trigger)
01 – General purpose output mode:
 Write pin value to ODR
 Read IDR to determine pin state
 Read ODR for last written value
10 – Alternate function mode:
Select alternate function via AF mux/register (see later slide)
11 – Analog mode:
Disable output buffer, input Schmitt trigger, pull resistors
(so as not to alter the analog voltage on the pin)
GPIO data registers
 16-bit memory-mapped data registers for each port GPIOx
x = A…I (GPIOA, GPIOB, …, GPIOI)
 GPIOx_IDR
 Data input through the 16 pins
 Read-only
 GPIOx_ODR
 Write data to be output to the 16 pins
 Read last value written to ODR
 Read/write (for read-modify-write operations)
 C examples:
GPIOA->ODR = 0x45; //send data to output pins
N = GPIOA->IDR; //copy data from in pins to N
GPIO port bit set/reset registers
 GPIO output bits can be individually set and cleared
(without affecting other bits in that port)
 GPIOx_BSRR (Bit Set/Reset Register)
 Bits [15..0] = Port x set bit y (y = 15..0) (BSRRL)
 Bits [31..16] = Port x reset bit y (y = 15..0) (BSRRH)
 Bits are write-only
 1 = Set/reset the corresponding GPIOx bit
 0 = No action on the corresponding GPIOx bit
(“set” has precedence if bit=1 in both BSSRL and BSSRH)
 C examples:
GPIOA->BSRRL = (1 << 4); //set bit 4 of GPIOA
GPIOA->BSRRH = (1 << 5); //reset bit 5 of GPIOA
Alternate function selection
Each pin defaults to GPIO pin at reset (mux input 0)

GPIOx_AFRL GPIOx_AFRH
(low pins 0..7) (high pins 8..15)
 GPIO pin option registers
Modify these registers for other than default configuration
 GPIOx_OTYPER – output type
 0 = push/pull (reset state)
 1 = open drain
 GPIOx_PUPDR – pull-up/down
 00 – no pull-up/pull-down (reset state)
 01 – pull-up
 10 – pull-down
 GPIOx_OSPEEDR – output speed
 00 – 2 MHz low speed (reset state)
 01 – 25 MHz medium speed
 10 – 50 MHz fast speed
 11 – 100 MHz high speed (on 30 pf)
 GPIO register addresses
 Base addresses of GPIOx register “blocks”
 GPIOA = 0x4002 0000 • GPIOF = 0x4002 1400
 GPIOB = 0x4002 0400 • GPIOG = 0x4002 1800
 GPIOC = 0x4002 0800 • GPIOH = 0x4002 1C00
 GPIOD = 0x4002 0C00 • GPIOI = 0x4002 2000
 GPIOE = 0x4002 1000
 Register address offsets within each GPIOx register block
 GPIOx_MODER = 0x00 pin direction/mode register
 GPIOx_OTYPER = 0x04 pin output type register
 GPIOx_OSPEEDR = 0x08 pin output speed register
 GPIOx_PUPDR = 0x0C pull=up/pull-down register
 GPIOx_IDR = 0x10 input data register
 GPIOx_ODR = 0x14 output data register
 GPIOx_BSRR = 0x18 bit set/reset register
 GPIOx_BSRRL = 0x18 BSRR low half – set bits
 GPIOx_BSRRH = 0x1A BSRR high half – reset bits
 GPIOx_LCKR = 0x1C lock register
 GPIOx_AFRL = 0x20 alt. function register – low
 GPIOx_AFRH = 0x24 alt. function register - high
 Assembly language example
;Symbols for GPIO register block and register offsets
GPIOA EQU 0x40020000 ;GPIOA base address
GPIO_ODR EQU 0x14 ;ODR reg offset
GPIO_IDR EQU 0x10 ;IDR reg offset
;Alternative – create symbol for each register address
GPIOA_ODR EQU GPIOA + GPIO_ODR ;addr of GPIOA_ODR
GPIOA_IDR EQU GPIOA + GPIO_IDR ;addr of GPIOA_IDR

;Using addresses = GPIO base + register offset

LDR r0,=GPIOA ;GPIOA base address
STRH r1,[r0,#GPIOx_ODR] ;GPIOA base + ODR offset
LDRH r1,[r0,#GPIOx_IDR] ;GPIOA base + IDR offset
;Using separate address for each GPIO register
LDR r0,=GPIOA_ODR ;GPIOA_ODR address
STRH r1,[r0]
LDR r0,=GPIOA_IDR ;GPIOA_IDR address
LDRH r1,[r0]
How would we address GPIOD ODR/IDR?
 GPIO port initialization ritual
• Initialization (executed once at beginning)
1. Turn on GPIOx clock in register RCC_AHB1ENR
(Reset and Clock Control , AHB1 peripheral clock register)
• RCC register block base address = 0x4002 3800
• AHB1ENR register offset = 0x30
• AHB1ENR bits 0-8 enable clocks for GPIOA-GPIOI, respectively
2. Configure “mode” of each pin in GPIOx_MODER
• Input/Output/Analog/Alternate Function
3. Configure1 speed of each output pin in GPIOx_OSPEEDR
4. Configure1 type of each pin in GPIOx_OTYPER
5. Configure1 pull-up/pulldown of each pin in GPIOx_PUPDR
1 if other than reset state required
• Input from switches, output to LEDs
Read/write 16-bit data via GPIOx_IDR/ODR
Set/clear output pins via GPIOx_BSRRL/BSRRH
To set bits
The or operation to set bits 3-0 of GPIOD_MODER, to select analog mode for
pins PD1 and PD0.
( The other 28 bits of GPIOD_MODER are to remain constant.)
Friendly software modifies just the bits that need to be.
GPIOD_MODER |= 0x0F; // PD1,PD0 analog
Assembly:
LDR R0,=GPIOD_MODER
LDR R1,[R0] ; read previous value
ORR R1,R1,#0x0F ; set bits 0-3
STR R1,[R0] ; update

c7 c6 c5 c4 c3 c2 c1 c0 value of R1
0 0 0 0 1 1 1 1 0x0F constant
c7 c6 c5 c4 1 1 1 1 result of the ORR

Bard, Gerstlauer, Valvano, Yerraballi

To clear bits
The AND or BIC operations to clear bits 3-0 of GPIOD_MODER to select “input
mode” for pins PD1 and PD0. (Without altering other bits of GPIOD_MODER.)
Friendly software modifies just the bits that need to be.
GPIOD_MODER &= ~0x0F; // PD1,PD0 output
Assembly:
LDR R0,=GPIOD_MODER
LDR R1,[R0] ; read previous value
BIC R1,R1,#0x0F ; clear bits 3-0
STR R1,[R0] ; update

c7 c6 c5 c4 c3 c2 c1 c0 value of R1
1 1 1 1 0 0 0 0 BIC #x0F = AND #0xFFFFFFF0
c7 c6 c5 c4 0 0 0 0 result of the BIC

Bard, Gerstlauer, Valvano, Yerraballi

To toggle bits
The exclusive or operation can also be used to toggle bits.
GPIOD_ODR ^= 0x80; /* toggle PD7 */

Assembly:
LDR R0,=GPIOD_ODR
LDRH R1,[R0] ; read port D
EOR R1,R1,#0x80 ; toggle state of pin PD7
STRH R1,[R0] ; update port D

b7 b6 b5 b4 b3 b2 b1 b0 value of R1
1 0 0 0 0 0 0 0 0x80 constant
~b7 b6 b5 b4 b3 b2 b1 b0 result of the EOR

Bard, Gerstlauer, Valvano, Yerraballi

To set or reset bits using BSSR
Use BSSR register to set or reset selected GPIO bits, without affecting the others
GPIOD_ODR |= 0x0080; // PD7 = 1
GPIOD_ODR &= ~0x0400; // PD10 = 0

Assembly:
LDR R0,=GPIOD ; GPIOD base address
MOV R1,#0x0080 ; select PD7
STRH R1,[R0,#BSSRH] ; set PD7 = 1
MOV R1,#0x0400 ; select PD10
STRH R1,[R0,#BSSRL] ; reset PD10 = 0

Alternative: write concurrently to BSSRH and BSSRL (as one 32-bit register)
LDR R0,=GPIOD ; GPIOD base address
MOV R1,#0x0400 ; select PD10 in BSSRL
MOVT R1,#0x0080 ; select PD7 in BSSRH
STR R1,[R0,#BSSR] ; PD10=0 and PD7=1
Switch Interfacing
Not +3.3V +3.3V
pressed Pressed LM3S or LM3S or
10kΩ TM4C TM4C
s Input port t Input port
10kΩ
Open Closed Negative logic Positive logic

The and operation to extract, or mask, individual bits:

Pressed = GPIOA_ODR & 0x10;
//true if PA6 switch pressed (pos. logic)
Assembly:
LDR R0,=GPIOA_IDR
LDRH R1,[R0] ; read port A IDR
AND R1,#0x10 ; clear all bits except bit 6
LDR R0,=Pressed ; update variable
STRH R1,[R0] ; true iff switch pressed

a7 a6 a5 a4 a3 a2 a1 a0 value of R1
0 1 0 0 0 0 0 0 0x40 constant
0 a6 0 0 0 0 0 0 result of the AND

Bard, Gerstlauer, Valvano, Yerraballi