CS-235: Computer Organization & Assembly Language

Topic # 03
Fall 2019

Engr. Taufique-ur-Rehman <[email protected]>[1]

Muhammad Imran Abeel <[email protected]>
CS-235 Computer organization & assembly language, Fall(2019)
 Outlines

 General Concepts of CPU Architectures

 Internal Registers

 Floating Point Unit

 IA-32 Modes of Operation

 IA-32 Memory Management

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CS-235 Computer organization & assembly language, Fall(2019)
IA-32 Modes of Operations

Real Addressing Mode

Protected Mode

System Management Mode

Virtual 8086 Mode

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CS-235 Computer organization & assembly language, Fall(2019)
 IA-32 Modes of Operations
Real Address Mode
• Can access only 1MB Memory (beyond 80236)
• For MS-DOS
• One task at a time (Single-Tasking)
• Programs can access Shared Memory Locations
(Problem???)

[4]
CS-235 Computer organization & assembly language, Fall(2019)
 IA-32 Modes of Operations
Real Address Mode
• Can access only 1MB Memory (beyond 80236)
• For MS-DOS
• One task at a time (Single-Tasking)
• Programs can access Shared Memory Locations

Protected Mode
• Can access only 4GB RAM
• For Windows, Linux
• Allows multi-tasking
• Memory Reservation for each Program [5]
CS-235 Computer organization & assembly language, Fall(2019)
 IA-32 Modes of Operations
System Management Mode
• Implementing Functions : Power Management &
System Security
• Usually implemented by Computer Manufacturers

Virtual 8086 Mode

• Being in Protected Mode:
the processor can directly execute a
program in Real Mode
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CS-235 Computer organization & assembly language, Fall(2019)
 IA-32 Memory Management
Segmented Memory Model

• Real Mode
• Segmented Memory

Flat Memory Model

• Protected Mode
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CS-235 Computer organization & assembly language, Fall(2019)
 Segmented Memory Model
• Intel 8088/8086 is a so-called 16-bit
Machine

• Each Register has 16 Bits

• 2^16 = 65536 = 64K

• But we want to use more memory

(640K, 1M)… [8]
CS-235 Computer organization & assembly language, Fall(2019)
 Segmented Memory Model
• 1MB Total Memory (Real Mode)
• Base Address
• Divided into 64KB called Segments
• Offset Address

• Linear Address: resultant of 16-bits Base

Address and 16 bits Offset Address
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CS-235 Computer organization & assembly language, Fall(2019)
 Segmented memory model
FFFFFh
For Code Segment: CS:IP or CS:EIP
For Stack Segment: SS:SP or SS:ESP

…
1FFFFh

1-
segment
(64KB)
10000h

00000h
1MB memory

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CS-235 Computer organization & assembly language, Fall(2019)
 Segmented Memory Model
• For Code Segment: CS:IP or CS:EIP
• For Stack Segment: SS:SP or SS: ESP

1000h:5000h calculate linear address?

1 0 0 0
Linear Address Calculations:
1 0 0 0 0

Left shift Segment Address New Seg. Address 10000h

by 4 locations

Add offset into new Address Offset Address 5000h

Linear Address = Linear Address 15000h

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CS-235 Computer organization & assembly language, Fall(2019)
 [12]
CS-235 Computer organization & assembly language, Fall(2019)
 Segmented Memory Model
Segment : Offset

• Segment: one of CS, DS, SS, ES

• Real address = Segment * 16 + Offset

• Overlapping Segments. For example:

0000:01F0 = 0001:01E0 = 0010:00F0

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CS-235 Computer organization & assembly language, Fall(2019)
 Linear Address Calculation
• Activity
CS: 1200h IP: F000h

Calculate Linear Address?

Linear Address : 21000h

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CS-235 Computer organization & assembly language, Fall(2019)
Real Mode Operation

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CS-235 Computer organization & assembly language, Fall(2019)
Segment & Offset Combination

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CS-235 Computer organization & assembly language, Fall(2019)
 Protected Mode Memory Model
In place of the segment address, the segment register
contains a selector that selects a descriptor from a
descriptor table.

The descriptor describes the memory segment’s

location, length, and access rights.

Global descriptor table Local descriptor table

• segment definitions • segment definitions

that apply to all unique to a
programs program.
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CS-235 Computer organization & assembly language, Fall(2019)
 Protected Mode Memory Model
• Segment descriptor tables
• Program structure
 code, data, and stack areas
 CS, DS, SS segment descriptors
 global descriptor table (GDT)

• MASM Programs use the Microsoft flat

memory model
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CS-235 Computer organization & assembly language, Fall(2019)
 Protected Mode Memory Model
RAM

Local Descriptor Table

9000

Base Limit Access

00021000 0010
8000
00006000 0001
00002000 0000
3000

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CS-235 Computer organization & assembly language, Fall(2019)
 Descriptor Table
• Each descriptor table contains 8192 Descriptors

• A total of 16,384 Descriptors are available to an

application at any time
• Max Memory 4G X 16383 = 4TB

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CS-235 Computer organization & assembly language, Fall(2019)
 Descriptor Table: 80286

• Base Address: 24 bits

• Limit Address (Offset): 16 bits
• Each Descriptor is of 8-bytes
• An 80286 can access Memory Segments that are
between 1 and 64K bytes in length
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CS-235 Computer organization & assembly language, Fall(2019)
 Descriptor Format: 80386

• Base Address: 32 bits

• Limit Address (offset): 20 bits
• The 80386 and above access memory segments that
are between 1 and 1M byte, or 4K and 4G bytes in
length.
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CS-235 Computer organization & assembly language, Fall(2019)
 Descriptor Table
Granularity Bit:
• If G=0, segment limit of 00000H to FFFFFH.
• If G=1. multiplied by 4K bytes (appended with FFFH). The limit
is then 00000FFFFH to FFFFFFFFH.

Available Bit:
• If AV=1, mean memory segment available.

• If D=0, the instructions are 16-bit (backward

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compatible).
CS-235 Computer organization & assembly language, Fall(2019)
 Protected Mode Memory Management

The segment selector

Selector Offset
points to a segment
descriptor, which
contains the base
address of a memory
segment.
The 32-bit offset from
Segment descriptor
+
the logical address is
added to the
segment’s base
address, generating a Base address of Linear Address
descriptor table
32-bit linear address [24]
CS-235 Computer organization & assembly language, Fall(2019)
 Example
Each segment descriptor indexes into the Linear address space
program's local descriptor table (LDT). Each
table entry is mapped to a linear address: (unused)

Logical addresses
Local Descriptor Table DRAM
SS ESP
0018 0000003A

DS offset (index)
0010 000001B6 18 001A0000
10 0002A000
08 0001A000
IP 00003000
00
0008 00002CD3

LDTR register [25]

CS-235 Computer organization & assembly language, Fall(2019)
 Paging
• Virtual Memory uses disk as part of the memory,
thus allowing sum of all Programs can be larger
than Physical Memory

• Only part of a Program must be kept in Memory,

while the remaining parts are kept on disk

• The Memory used by the Program is divided into

small units called Pages (4096-byte)

• As the Program runs, the Processor selectively

unloads inactive pages from memory and loads
other pages that are immediately required [26]
CS-235 Computer organization & assembly language, Fall(2019)
 Paging
• OS maintains Page Directory and Page Tables

• Page Translation: CPU converts the Linear Address

into a Physical Address

• Page Fault: occurs when a needed page is not in

memory, and the CPU interrupts the program

• Virtual Memory Manager (VMM) – OS utility that

manages the loading and unloading of pages

• OS copies the page into memory, program resumes

execution [27]
CS-235 Computer organization & assembly language, Fall(2019)
Paging

Chunk of Program:
Page

Chunk of Memory:
Frame

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CS-235 Computer organization & assembly language, Fall(2019)
 Page Translation
A linear address is divided into a page directory field, page
table field, and page frame offset. The CPU uses all three to
calculate the physical address.
Linear Address
10 10 12
Directory Table Offset

Page Frame

Page Directory Page Table

Physical Address

Page-Table Entry

Directory Entry

CR3
32
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CS-235 Computer organization & assembly language, Fall(2019)
Page Translation

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CS-235 Computer organization & assembly language, Fall(2019)
 CISC vs RISC
• CISC – Complex Instruction Set
large instruction set
high-level operations
requires microcode interpreter
examples: Intel 80x86 family
• Mult 2,3

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CS-235 Computer organization & assembly language, Fall(2019)
 CISC vs RISC
• RISC – Reduced Instruction Set
• Simple instruction formats
• Small instruction set
• Directly executed by hardware

Examples:
ARM (Advanced RISC Machines)

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CS-235 Computer organization & assembly language, Fall(2019)
Questions?

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CS-235 Computer organization & assembly language, Fall(2019)
THANK YOU!

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CS-235 Computer organization & assembly language, Fall(2019)