EL525 – Digital Design using HDL and FPGA

LAB Assignment 6

Q1 Design NOT, NOR, NAND, XOR and XNOR gates using switch level
modeling.

Answer :

1.Not gate ( Inverter ) : Not gate is made of cmos(Complementary Metal Oxide

Semiconductor) , in which pmos and nmos are connected in complementary form to work as
full up and pull down device, for zero input pmos will work and gives high output,for high
input nmos will work and gives low output.

Figure 1.1: not gate using Pmos and nmos

module Q1not(out,in); //module for not gate
input in;
output out;
supply1 vdd; //vdd supply for source of pmos
supply0 gnd; //gnd supply for source of nmos

pmos p1(out,vdd,in); //pullup logic

nmos n1(out,gnd,in); //pullup logic

endmodule

Figure 1.2: simulation result of not gate or inverter

2.Nor gate
module Q1nor(out,a1,a2); //module for nor gate
input a1,a2;
output out;
supply1 vdd; //vdd supply for source of pmos
supply0 gnd; //gnd supply for source of nmos
wire w1;
pmos g1(w1,vdd,a1); //pullup logic
pmos g2(out,w1,a2); //pullup logic

nmos g3(out,gnd,a1); //pulldown logic

nmos g4(out,gnd,a2); //pulldown logic
endmodule

Figure 1.3: simulation result of nor gate

3.Nand gate
module Q1nand(out,a1,a2); //module for nand gate
input a1,a2;
output out;
supply1 vdd; //vdd supply for source of pmos
supply0 gnd; //gnd supply for source of nmos
wire w1;
pmos g1(out,vdd,a1); //pullup logic
pmos g2(out,vdd,a2); //pullup logic

nmos g3(out,w1,a1); //pulldown logic

nmos g4(w1,gnd,a2); //pulldown logic
endmodule

Figure 1.4 simulation result of nand gate

4.Xor gate
module Q1xor(out,a,b); //module for xor gate using cmos
input a,b;
output out;
supply1 vdd; //vdd supply for source of pmos
supply0 gnd; //gnd supply for source of nmos
wire w1,w2;
pmos g1(w1,vdd,a); //pullup logic
pmos g2(w1,vdd,b); //pullup logic
pmos g3(out,w1,~a); //pullup logic
pmos g4(out,w1,~b); //pullup logic

nmos g5(out,w4,a); //pulldown logic

nmos g6(w4,gnd,b); //pulldown logic
nmos g7(out,w5,~a); //pulldown logic
nmos g8(w5,gnd,~b); //pulldown logic
endmodule

Figure 1.5 simulation result of xor gate

5.Xnor gate
module Q1xnor(out,a,b); //module for xnor gate using cmos
input a,b;
output out;
supply1 vdd; //vdd supply for source of pmos
supply0 gnd; //gnd supply for source of nmos
wire w1,w2,w3;
pmos g1(w1,vdd,a); //pullup logic
pmos g2(w1,vdd,~b); //pullup logic
pmos g3(out,w1,~a); //pullup logic
pmos g4(out,w1,b); //pullup logic

nmos g5(out,w2,a); //pulldown logic

nmos g6(w2,gnd,~b); //pulldown logic
nmos g7(out,w3,~a); //pulldown logic
nmos g8(w3,gnd,b); //pulldown logic
endmodule

Figure 1.6 simulation result of xnor gate

Instance 1 : In this experiment all the logic design done on switch level modelling. Here
we couldn’t get any RTL block diagram but we simulated the results for different inputs,each
logic is devided in two block pull-up and pull-down respectively which manipulate the result
of logic gate.

2. Design NOT, NOR, NAND, XOR and XNOR gates using switch level
modeling with less number of transistor count than in conventional CMOS.

Answer : In this question we replaced all pmos transistor by Pull-up data-type and tried to
simulate all the logic gate

1.Not gate
module Q2not(out,in); //not gate using pull-up logic to reduce no of transistor
input in;
output out;
pullup (out); //pull-up logic
supply0 gnd; //ground supply for source of pmos

nmos n1(out,gnd,in); //pulldown logic

endmodule

Figure 2.1 simulation result of not gate

2.Nor gate
module Q2NOR(out,a,b);
input a,b;
output out;
pullup(out); //pullup logic
supply0 gnd; //ground supply for source of nmos

nmos g1(out,gnd,a); //pulldown logic

nmos g2(out,gnd,b); //pulldown logic

endmodule

Figure 2.2 simulation result of nor gate

3.Nand gate
module Q2Nand(out,a,b); //module of nand gate using pull-up logic
input a,b;
output out;
pullup (out); //pullup logic
supply0 gnd; //ground supply for source of pmos

nmos g1(out,w1,a); //pulldown logic

nmos g2(w1,gnd,b); //pulldown logic
endmodule

Figure 2.3 simulation result of nand gate

4.Xor gate
module Q2xor(out,a,b); //module of Xor gate using pull-up logic
input a,b;
output out;
pullup (out); //pullup logic
supply0 gnd; //gnd supply for source of nmos
wire w1,w2;

nmos g1(out,w1,a); //pulldown logic

nmos g2(w1,gnd,b); //pulldown logic
nmos g3(out,w2,~a); //pulldown logic
nmos g4(w2,gnd,~b); //pulldown logic

endmodule

Figure 2.4 simulation result of xor gate

5.Xnor gate
module Q2xnor(out,a,b); //module of Xnor gate using pull-up
input a,b;
output out;
pullup (out); //pullup logic
supply0 gnd; //gnd supply for source of nmos
wire w1,w2;
nmos g1(out,w1,a); //pulldown logic
nmos g2(w1,gnd,~b); //pulldown logic
nmos g3(out,w2,~a); //pulldown logic
nmos g4(w2,gnd,b); //pulldown logic
endmodule

Figure 2.5 simulation result of xnor gate

Instance 2 : In this experiment we implemented all the basic logic gates using switch level
modelling. Previously we use pmos as pull-up and nmos as pull-down but in this experiment
we replaced the pmos by pull-up type output, by doing this number of transistor is also
reduced.

Q3 Implement 2:1 and 4:1 multiplexers with switch level modeling.

module Q3_2to1(out,a,sel); //module of multiplexer 2:1 using switch level modeling

input [1:0]a;
input sel; //select line for 2 input multiplexer
output out;
pullup (out); //pullup logic
wire w1,out1,w2;
pullup (out1); //pullup logic
supply0 gnd; //gnd supply for source of nmos

nmos g1(out1,w1,~sel);
nmos g2(w1,gnd,a[0]);
nmos g3(out1,w2,sel);
nmos g4(w2,gnd,a[0]);

nmos g5(out,gnd,out1);

endmodule

Figure 3.1 simulation result of multiplexer 2:1

module Q3_4to1(out,a,sel); //module of multiplexer 4:1 using switch level modeling
input [3:0]a;
input [1:0]sel; //select line for 2 input multiplexer
output out;
pullup (out); //pullup logic
wire w1,out1,w2,w3,w4,w5,w,w7,w8;
pullup (out1); //pullup logic
supply0 gnd; //gnd supply for source of nmos

nmos g1(out1,w2,~sel[1]);
nmos g2(w2,w1,~sel[0]);
nmos g3(w1,gnd,a[0]);

nmos g4(out1,w4,~sel[1]);
nmos g5(w4,w3,sel[0]);
nmos g6(w3,gnd,a[1]);

nmos g7(out1,w6,sel[1]);
nmos g8(w6,w5,~sel[0]);
nmos g9(w5,gnd,a[2]);

nmos g10(out1,w8,sel[1]);
nmos g11(w8,w7,sel[0]);
nmos g12(w7,gnd,a[3]);

nmos g13(out,gnd,out1);
endmodule

Figure 3.2 simulation result of multiplexer 4:1

Instance 3: In this experiment we implemented two basic multiplexer using switch level
modelling. In above experiment we made output as pullup circuit. In this experiment we
learned that how we can realize the the basic multiplexer using transistors,also saw that
complexity and length of module is increased.
4. Design SRAM
(i) Without using strength in Verilog
(ii) Using strength in Verilog

Answer:
(i) Without using strength in Verilog

Figure 4.1 : block diagram of basic SRAM without using signal strength

module Q4sram_without(dataout,data_in,w_st,read); //module for SRAM w/o using signal strength

input data_in,w_st,read; //w_st =write/storage
output dataout;
wire w1,w2,w3;

bufif1 g1(w1,data_in,w_st);
bufif0 g2(w1,w2,w_st);
not g3(w3,w1);
not g4(w2,w3);
bufif1 g5(dataout,w2,read);

endmodule

Figure 4.2 : simulation result of SRAM Without using signal strength

 (ii) Using strength in Verilog

Figure 4.3 : block diagram of basic SRAM based on signal strength

module Q4sram_with(dataout,datain,w_st,rd); //module for SRAM using signal strength

input datain,w_st,rd; //w_st =write/storage
output dataout;
wire w1, w2;
bufif1 (strong1,strong0)a1(w1,datain,w_st);
not g2 (w2,w1);
not (weak0,weak0)g3 (w1,w2);
bufif1 g4(dataout,w1,rd);

endmodule

Figure 4.4 simulation result of SRAM using signal strength

Instance 4: In this experiment we analysed the SRAM (static random access memory) with
or without using signal strength. We can simply observed that complexity of circuit is
reduced in SRAM using signal strength, less wire is used for bigger circuit. The reduction of
complexity can directly be observed in block diagram of figure 4.1 and 4.3 .
Exercise:

1.Implement capacitor using nmos switch primitive in Verilog HDL. Write

test bench to check its functionality.

module Ex_cap(out,in); //module for capacitance using nmos

input in;
output out;
trireg #(0,0,3)out1;
supply1 vdd;
nmos n1(out1,vdd,in);
assign out=out1;
endmodule

module ex_cap_tb; //test bench for nmos capacitor

// Inputs
reg in;

// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Ex_cap uut (.out(out), .in(in));

initial begin
// Initialize Inputs
#0 in = 0;
#1 in= 1'b1;
#1 in= 1'b1;
#1 in= 1'b1;
#1 in= 1'b0;
#1 in= 1'b0;
#1 in= 1'b0;
#1 in= 1'b0;
#1 in= 1'b0;
#1 in= 1'b1;
// Wait 100 ns for global reset to finish
#100;

end
endmodule

Figure Ex 1.1 : simulation of switch level nmos capatitor

2. Design 4-bit Full Adder using switch level modeling.

module Exq2(sum,a,b,c); //module of 4bit adder

input [3:0]a,b;
input c;
output [4:0]sum;
wire [2:0]w;
adder a1(sum[0],w[0],a[0],b[0],c); //instantiation of 3bit adder made of switch level modeling
adder a2(sum[1],w[1],a[1],b[1],w[0]); //instantiation of 3bit adder made of switch level modeling
adder a3(sum[2],w[2],a[2],b[2],w[1]); //instantiation of 3bit adder made of switch level modeling
adder a4(sum[3],sum[4],a[0],b[0],w[2]); //instantiation of 3bit adder made of switch level modeling
endmodule

module adder(sum,carry,a,b,c); // 3bit adder made of switch level modelling for instantiation
input a,b,c;
output sum,carry;
wire w1,w2,w3,w4;
Q1xor b1(w1,a,b); //instantiating the switch level xor gate
Q1xor b2(sum,w1,c); //instantiating the switch level xor gate
andgate b3(w2,a,b); //instantiating the switch level and gate
andgate b4(w3,b,c); //instantiating the switch level and gate
andgate b5(w4,c,a); //instantiating the switch level and gate
orgate b6(carry,w2,w3,w4); //instantiating the switch level or gate

endmodule

module andgate(out,a,b); //module of and gate using switch level modelling for instantiation
input a,b;
output out;
wire w1;
wire out1;
supply0 gnd;
pullup (out1);
nmos g1(out1,w1,a);
nmos g2(w1,gnd,b);

nmos g3(out,gnd,out1);
endmodule

module orgate(out,a,b,c); //module of or gate using switch level modelling for instantiation

input a,b,c;
output out;
supply0 gnd;
pullup (out);
wire out1;
pullup (out1);
wire w1,w2;

nmos n1(out1,w1,a);
nmos n2(w1,w2,b);
nmos n3(w2,gnd,c);
nmos n4(out,gnd,out1);
endmodule

module Q1xor(out,a,b); //module of xor gate using switch level modelling for instantiation

input a,b;
output out;
supply1 vdd;
supply0 gnd;
wire w1,w4,w5;
pmos g1(w1,vdd,a);
pmos g2(w1,vdd,b);
pmos g3(out,w1,~a);
pmos g4(out,w1,~b);
nmos g5(out,w4,a);
nmos g6(w4,gnd,b);
nmos g7(out,w5,~a);
nmos g8(w5,gnd,~b);

endmodule

Figure Ex2.1 simulation result of 4 bit full adder

Instace of Exercise: In this Exercise we analysed a 4 bit full adder and a capacitor using
switch level modelling. All the module instantiated in full adder module is made of switch
level modelling. We simple can say that switch level modelling provide better realization of
logic cicuit at smaller level but as size of logic circuit increase it become tedious task to find
error of logic circuit. So that is the reason we basic logic gate to make design more flexible.

Conclusion: In this assignment we implemented and analyzed combinational

circuits with switch level modeling techniques and observed that switch level
modelling(transistor level modelling) makes logic design little complex
compare to logic gates(made of switch level modeling). All the module
performed on Xilinx ISE 14.7(verilog).