Genus Quick Start Guide: Timing

Analysis
Product Version 19.12
December 11, 2019
Copyright Statement

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 Genus Quick Start Guide: Timing Analysis

Contents
Purpose................................................................................................................................................ 4
Overview .............................................................................................................................................. 4
1. Stages for Timing Analysis ............................................................................................................... 4
2. Checklist for Timing Analysis......................................................................................................... 5
2.1. Constraints ......................................................................................................................... 5
2.2. Pre-synthesis Diagnosis ..................................................................................................... 5
2.3. Check path groups and cost groups specification ............................................................... 5
2.4. Ungrouping requirements ................................................................................................... 6
2.5. Check for Ideal (I) nets on critical path ................................................................................ 6
2.6. Logic levels ......................................................................................................................... 6
2.7. Abnormally Large Cell/Transition Delay .............................................................................. 7
2.8. Clock Crossing Domain ...................................................................................................... 9
2.9. Input to Output Path............................................................................................................ 9
2.10. Half Path Cycle ............................................................................................................... 9
3. Timing Report Analysis ............................................................................................................... 10
3.1 GUI Analysis ..................................................................................................................... 10
3.2 Command report_timing ................................................................................................... 12
3.3 Examples of sample scripts using the commands discussed earlier ................................. 14
3.4. Command report_timing_summary ...................................................................................... 21
4. Optimizations for Timing Analysis................................................................................................ 22
4.1. Cost Groups and Path Groups .......................................................................................... 22
4.2. Path Adjust ....................................................................................................................... 22
4.3. Logic Levels...................................................................................................................... 23
4.4. Ungrouping a design with preserved instances ................................................................. 23
4.5. Optimizing endpoints ........................................................................................................ 24
4.6. Re-timing .......................................................................................................................... 24
4.7. Hard Regions ................................................................................................................... 24
4.8. Ideal Nets ......................................................................................................................... 25
4.9. Combinational Feedback Loops ....................................................................................... 25
4.10. Effort levels for synthesis .............................................................................................. 26
4.11. Modifying Constraints.................................................................................................... 26
5. Timing Analysis for MMMC Design .............................................................................................. 27
6. LAB ............................................................................................................................................. 27
6.1 Non-MMMC Design .............................................................................................................. 27
6.2 MMMC Design...................................................................................................................... 32
Summary............................................................................................................................................ 33
References......................................................................................................................................... 33
Further Reading ................................................................................................................................. 33
Support .............................................................................................................................................. 33
Videos ................................................................................................................................................ 33
Feedback ........................................................................................................................................... 33

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 Genus Quick Start Guide: Timing Analysis

Purpose
This Application Note guides the user through a step by step process for timing analysis,
debugging and optimization in the synthesis stage.

Audience
This document is intended for users who use Genus Synthesis Solution™ to close the
timing in the synthesis stage.

Overview
Timing Closure is the most critical component of a digital design. Timing analysis has
become critical within synthesis stage itself, so it’s critical to meet the timing in this stage.

This appnote discusses a step by step approach on how to perform timing analysis, the
debugging and optimization techniques. The timing closure is demonstrated for the DTMF
design used in various Genus RAKs.

1. Stages for Timing Analysis

1. Read the SDC file and understand the constraints

2. Understand the warnings generated

3. Check for failed SDC commands and check timing intent

4. Fix the timing intent warnings, as applicable

5. Analyze the timing report and modify the constraints if necessary

6. Analyze the attribute settings that impact timing in synthesis

7. Perform Generic, Mapped and Optimization synthesis and repeat steps 4, 5 & 6 as
necessary after each synthesis stage

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2. Checklist for Timing Analysis

2.1. Constraints

During the first stage of global mapping, the timing constraints are used to estimate
the initial target slack. This target slack is a timing goal for Genus to work toward
during the optimization process. Inaccurate or unrealistic constraints can lead to a bad
starting point during global mapping, and consequently, a bad result at the end. The
practice of over constraining the design with a small guard band is not recommended
in Genus.

2.2. Pre-synthesis Diagnosis

Paths that are not constrained correctly may not appear in timing violation reports
when the user perform timing analysis. For this reason, generate pre-synthesis timing
reports first for analysis, and anytime there are constraint updates.

Timing intent problems can be listed using commands –

check_timing_intent or
report_timing -lint

User must fix them first, as applicable. Some constraints may need to be modified or
new constraints might be added at this stage.

2.3. Check path groups and cost groups specification

Path groups, groups paths into the specified groups and assigns them to different cost
groups. Cost groups are containers for single/multiple path groups with weights
assigned for each group as specified by the user. Cost groups multiplies the WNS of
each path group, during optimization, with the weight assigned for it.

This mechanism can be used productively in conjunction with ‘path_adjust’

optimization approach, and with TNS optimization techniques.

However, there are situations in which it does not make sense to group all register to
register paths, so this method should not be applied blindly, as with all aspects of
timing optimization during synthesis. It is crucial to understand the clocking and timing
scheme of the design prior to setting up path and cost groups to control the
optimization process.
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 Genus Quick Start Guide: Timing Analysis

2.4. Ungrouping requirements

Too many hierarchies in the critical path hinder the optimization. The boundaries must
be maintained, which prevents sharing and moving logic together to reduce it.

Ungrouping helps in the optimization, however ungrouping all the hierarchies can
cause problem for the downstream users.

By default, Genus performs automatic ungrouping for medium and high effort level of
synthesis.

2.5. Check for Ideal (I) nets on critical path

Genus recognizes clock nets and asynchronous set and reset nets in a design and
treats them as “ideal”. This means it does not perform any optimization and buffering
on those nets. This allows them to have a high fanout and a high capacitance, but
show a zero transition, and consequently, not be considered a critical path.

However, when the user uses the clock or reset nets mixed in with the data signals,
the ideal nets suddenly become critical paths. Any logic on an ideal net will not be
properly optimized and that can cause all sorts of problems. The best design practice
is to isolate clocks and asynchronous pins from the data pins.

2.6. Logic levels

‘report_logic_levels_histogram’ can be used to get an idea about the logic

levels of different paths in the design. User can specify the range of the logic levels
using the -bar option.

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 Genus Quick Start Guide: Timing Analysis
User can use the below applet for the path specific logic level.

2.7. Abnormally Large Cell/Transition Delay

If all the cells have large delays, then there could be a problem with the wire-load
model, the operating conditions, or the technology library, all of which affect every cell
delay. Check the log file to see if there were any warnings when reading in the library
or when applying the constraints to the library.

If only one or two cells have unexpectedly large delays, then the user need to figure
out why. Look at the fanout, load, and slew columns in the timing report to see if any
of those factors correlate with the large delays.

Is there a high fanout that is under driven? If the cell is unable to drive the given fanout
and load requirements, the slew and delay value will be very high.

If the load is high, then check to see if it correlates with the fanout. If the load is
independent of the fanout, then it could be a bad ‘set_load’ constraint or a mis-
characterized value in the .lib file.

The slew column reflects how fast a signal is transitioning and is influenced by the
capacitive load and the drive strength of the cell. It is used by the delay models to look
up the delay for a given cell. Large transition times can be caused by a bad
‘set_input_transition’ constraint if the large slew is at the beginning of the path
or a bad cell description, which would be found in the .lib file.

The user can use the ‘report_cell_delay_calculation’ to get a detailed

analysis of the delay calculation for a cell. Similarly, the commands
‘report_net_delay_calculation’, ‘report_net_res_calculation’ and
‘report_net_cap_calculation’ can be used for analyzing appropriately.

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 Genus Quick Start Guide: Timing Analysis

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 Genus Quick Start Guide: Timing Analysis
2.8. Clock Crossing Domain

Make sure that all the clocks defined using ‘define_clock’ has the -domain
argument specified with it. Else the user will have to specify false path between each
clock domain. There can be paths in the design that are constrained by two different
clocks, and the relationship between the periods is not an integer multiple. Verify that
the periods of the clocks were defined correctly.

For example,

define_clock -name 100MHz -period 10000

define_clock -name 300MHz -period 10000 -divide_period 3 [clock_ports]

Genus recognizes that there are exactly three periods of clock 300MHz to every period
of clock 100MHz. If the user specified a period of 3333 picoseconds for the 300MHz
clock, then Genus computes a different relationship between the clocks (3333 periods
of one clock to 10000 periods of the other) and the timing analysis of the design would
be different.

2.9. Input to Output Path

If the timing is not met for Input to Output path, check for the input and output delays
and the ‘set_max_delay’ or ‘path_delay’ constraints and verify whether they are
reasonable.

2.10. Half Path Cycle

Look for the edge of the launch and the capture pins in the timing report. If they are
different it corresponds to a half path cycle. In such cases the user must ensure that
the datapath has enough time to propagate.

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3. Timing Report Analysis

3.1 GUI Analysis

The best way to understand and analyze the design would be through the Global Timing
Debug (GTD). Genus provides the GTD feature for debugging the timing results. The
various Timing Debug forms provide easy visual access to the timing reports and
debugging tools. Timing Debug Window will pop up automatically if you generate the
timing debug report through GUI by typing ‘gui_show’ and then clicking on Timing 
Debug Timing.

The Timing Debug form is used for debugging timing results. Use the path histogram to
identify all categories. The idea is to start looking at the big picture (overall histogram).
The Debug form shows information such as summary of timing results, path list, path
categories and can be used to start debugging the results.

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The Timing Path Analyzer form is used to identify issues related to a path using slack
calculation bars, timing bar, and hierarchy view. The Slack Calculation column displays
path arrival time and required time calculations in color bars. The Data Delay column
displays the details of the selected path in the violation reports. Timing Bar displays the
instance and net delay, size of the bar indicates the delay associated. Hierarchy view
displays a path’s traversal of logical hierarchy on a time axis.

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 Genus Quick Start Guide: Timing Analysis
3.2 Command report_timing

Most users like to keep it within the shell. To be good at timing analysis through shell, one
must be very fluent with all the flags and its combination of ‘report_timing’ command.
A lot of the intuition comes from experience. Study the description given about
report_timing and the examples following it.

Parameters

• -fields: Specify the fields to be displayed in the timing report.

• -output_format {text|gtd}: gtd is the machine-readable format

• -path_type {full|summary|full_clock|endpoint}:
- full is the default option.
- full_clock displays launch and capture clock path also.
- summary displays just the slack calculation without the paths.
- endpoint returns the slack for all endpoints in the design.
- Note that nworst doesn’t apply for endpoint flag

• -split_delay: Displays both drivers and load in the datapath of the report

• -stage_delay: Displays only drivers in the datapath of the report

• -hpins: Displays hpins in the datapath of the report

• -nets: Displays nets in the datapath of the report

• -physical: Reports physical information like x, y location

• -user_derate: Controls the display of an additional column for the user derating
values in the timing report.

• -from | -from_fall | -from_rise

{<inst>|<hsinst>|<external_delay>|<clock>|<port>|<pin>}

• -through | through_fall | through_rise {<insts>

|<hinsts>|<port>|<pin>}

• -to | -to_fall| -to_rise

{<inst>|<hsinst>|<external_delay>|<clock>|<port>|<pin>}

• -capture_clock_pins | -capture_clock_pins_fall_clock |
-capture_clock_pins_rise_clock | -capture_clock_pins_fall_pin
| -capture_clock_pins_rise_pin} {<pin>|<hpin>}

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 Genus Quick Start Guide: Timing Analysis
• -max_paths <integer>: Specifies the max number of paths to report

• -nworst <integer>: Specifies the max number of paths to report for each
endpoint

• -max_slack <integer>: Reports only paths with a slack smaller than the
specified number

• -min_slack <integer>: Reports only paths with a slack greater than the
specified number

• -unconstrained: Reports only the unconstrained paths (paths with no slack)

• -logic_levels <integer>: Returns the start and end points, and the number
of levels of logic for the number of top paths

• -logic_levels_tcl_list: Returns the above in TCL list format

• -skip_buf: Excludes buffer from logic level count

• -skip_inv: Excludes inverter from logic level count

• -exception_data: Display the exception cross-linking information

• -exceptions <exceptions>: Reports paths only where the exception applies

• -group <group_list>: Reports path for the specified cost group.

• -domain <clock_domain>: Restricts the paths to the specified clock domain

• -views <analysis_view>: Specify the analysis view for MMMC

• -paths <string>: The string argument must be created using

set_path_specification

• -timing_bin <bin>: Reports timing for all paths in the bin

• -timing_path <path>: The timing path must be part of a timing bin

• -collection: Returns a collection of timing paths which can be saved to a variable

for further use. It is not supported for unmapped design.

• -gui: Creates a detailed timing report in the GUI without having to use the menu
commands.

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3.3 Examples of sample scripts using the commands discussed earlier

Example #1: Script to report of the endpoints and startpoints slack of top 1000 failing paths

set rpt [report_timing -max_paths 10 -max_slack 0 -collection]

foreach_in_collection r $rpt {
puts “Endpoint :[get_db [get_db $r .capturing_point] .hierarchical_name] \t \
Startpoint: [get_db [get_db $r .launching_point] .hierarchical_name] \t \
Slack: [get_db $r .slack] “
}

Output

Example #2: Script to report slack and difference between clock arrival time at launch and capture clocks

set a [report_timing -max_paths 4 -collection]

puts " Reporting Slack and Skew between paths \n
\t StartPoint \t\t\t EndPoint \t\t\t Slack \t\t\t Skew"
foreach_in_collection i $a {
set StartPoint [get_object_name [get_db $i .launching_point]]
set EndPoint [get_object_name [get_db $i .capturing_point]]
set l1 [get_db $i .launching_clock_latency]
set c1 [get_db $i .capturing_clock_latency]
set Slack [get_db $i .slack]
set Skew [expr $c1 - $l1]
puts "$StartPoint \t $EndPoint \t $Slack \t $Skew"
}

Output

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 Genus Quick Start Guide: Timing Analysis

Example #3: To get a list of the register sinks for a clock

puts “Clock Name \t No: of register sinks \t Sink Lists”

foreach_in_collection a [all_clocks] {
set name [get_object_name $a]
puts “$name \t \t [sizeof_collection [all_registers -clock $a]]”
foreach b [get_object_name [all_registers -clock $a] ] {
puts “ \t \t \t \t \t $b “
}
}

Output

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 Genus Quick Start Guide: Timing Analysis

Example #4: To return all the instance pins that are used in the path

set paths [report_timing -collection]

foreach_in_collection path $paths {
puts ""
set timingPoints [get_db $path .timing_points]
foreach_in_collection point $timingPoints {
set pinPtr [get_db $point .pin]
set pin [get_object_name $pinPtr]
puts $pin
}
}

Output

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Example #5: Script to report logics between reg-to-reg. This script can be modified for different path
groups:

group_path -from [all_registers] -to [all_registers] -name GRP

set a [report_timing -group GRP -max_paths 10 -collection]
foreach_in_collection i $a {
set StartPoint [get_object_name [get_db $i .launching_point]]
set EndPoint [get_object_name [get_db $i .capturing_point]]
set points [get_db $i .timing_points]
puts ""
puts "Timing points between $StartPoint and $EndPoint"
puts ""
foreach_in_collection j $points {
set p [get_object_name [get_db $j .pin]]
puts $p
}
}

Output

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 Genus Quick Start Guide: Timing Analysis
Example #6: Script to get the intermediate logic between fanout cone of one instance to fanin cone of
another instance:

proc intersect_fanin_fanout {x y} {
if {[get_ports -quiet $x] != ""} {
set X [all_fanout -from [get_ports $x]]
} else {
set X [all_fanout -from [get_pins $x]]
}
if {[get_ports -quiet $y] != ""} {
set Y [all_fanin -to [get_ports $y]]
} else {
set Y [all_fanin -to [get_pins $y]]
}
set result [remove_from_collection -intersect $X $Y]
return $result
}

Output

Example #7: Script to find the number of logic levels (combinational) in a timing path or group of timing
paths

proc num_of_logicLevel {max_paths} {

set a [report_timing -max_paths $max_paths -collection]
puts "Start Point \t\t\t \t \t End Point \t\t\t\t \tInstance Count"
foreach_in_collection i $a {
set StartPoint [get_object_name [get_db $i .launching_point]]
set EndPoint [get_object_name [get_db $i .capturing_point]]
set Size [sizeof_collection [get_db $i .timing_points]]
set InstCount [expr $Size/2]
puts "$StartPoint \t $EndPoint \t $InstCount"
}
}

Output

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 Genus Quick Start Guide: Timing Analysis
Example #8: Script to report worst slack for all clock group

foreach_in_collection clk [all_clocks] {

set timing_path_collection [report_timing -from $clk -to $clk -collection]
foreach_in_collection path $timing_path_collection {
set path_group [get_object_name $clk]
set wns [get_db $path .slack]
set view [get_db $path .view_name]
puts "Clock group: $path_group View: $view WNS: $wns"
}
}

Output

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 Genus Quick Start Guide: Timing Analysis
Example #9: Script to report cell delays above/below a specified value

foreach_in_collection timing_path [report_timing -collection -max_paths 10000

-max_slack 10] {
foreach_in_collection tp [get_db $timing_path .timing_points] {
set delay [get_db $tp .delay]
if {$delay > 0.1} {
puts "[get_db $tp .hierarchical_name] \t [get_db $tp .delay]"
}
}
}

Output:

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 Genus Quick Start Guide: Timing Analysis

3.4. Command report_timing_summary

This is another useful command in timing analysis. It reports the Worst Negative
Slack(WNS), Total Negative Slack (TNS) and Failing Endpoints (FEP) for all cost groups
defined for both Setup and DRV checks.

Note: If the user hasn’t defined any cost groups, Genus will internally create cost groups
for reporting and remove them, when the user invokes this command.

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 Genus Quick Start Guide: Timing Analysis

4. Optimizations for Timing Analysis

4.1. Cost Groups and Path Groups

Understand the structure of the design properly and define cost groups and path
groups appropriately. If the user wants the tool to focus on a group, increase the
weight of the cost group. By default, we have path groups for each clock domain,
clock gated path group and a default path group consisting of all non-clocked
paths.

define_cost_group -weight <weight> -name <name>

path_group -from <from point> -to <to point> -through <through point> -name <name>
-group <cost group name>

4.2. Path Adjust

As described earlier, path_adjust is used in conjunction with cost groups. If the

user wants the tool to focus on a path group or paths, the user can tighten the
timing constraints for it alone and loosen for the remaining. However, beware of
over constraining! The tool will react differently for different levels of values as is
indicated in the upcoming section.

Suppose the user want the tool to focus mainly on the reg2reg paths:

path_adjust -from [all_inputs] -to [all_outputs] -delay 500 -name PA_I2O

path_adjust -from [all_inputs] -to [all_registers] -delay 500 -name PA_I2C
path_adjust -from [all_registers] -to [all_outputs] -delay 500 -name PA_C2O
path_adjust -from [all_registers] -to [all_registers] -delay -500 -name PA_C2C

Here the reg2reg is tightened by 500 whereas other groups are relaxed by 500
causing the tool to treat it with more seriousness.

The difference between using ‘cost_group’ weight and ‘path_adjust’ for

directing the optimizer is as follows: cost_group refers to a group of timing paths
with a single timing optimization objective. During optimization, Genus tries to
minimize the worst negative slack (WNS) among all paths in each cost group.
Thus, the mapper sets a different target, the worst or most critical path (WNS) for
each cost group and works on it separately. Genus performs incremental
optimization on each path separately. The costing function considers the weight of
the cost group and multiplies it to the worst slack for scoring.

So, while cost group weight would mean multiplying the WNS of the slack group
by a factor, ‘path_adjust’ is adding/subtracting the delay to all paths of that
path adjust group. Now the user could make the path adjust groups independent

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 Genus Quick Start Guide: Timing Analysis
of the user cost groups. So, the user could have a mix-and-match approach to tune
the optimizer. Remember to normalize the timing by removing the path adjust
constraints in the end.

4.3. Logic Levels

For a Datapath intensive design the logic level of the timing path can be reduced
using the following methods.

Ungroup the hierarchical instances giving the major hit in slack. While ungrouping
the user must keep the following things in mind:

• Ungroup the user defined hierarchies before generic stage to give the tool
more chance of restructuring at generic stage.

ungroup -flatten -force [get_db insts <instance_name>]

• Ungroup the adders, shifters or other complex logic before map stage

ungroup -flatten -force [get_db insts <adder_name>]

4.4. Ungrouping a design with preserved instances

syn_map
set_db ui_respects_preserve false
ungroup
set_db ui_respects_preserve true

Using the attributes and commands mentioned below, the user can ungroup the
design that contains retimed state points.

set_db ui_respects_preserve false

set num_sp [llength [get_db hinsts *_state_point*] ]
if { $num_sp != 0 } {
foreach sp [get_db hinsts *_state_point*] {
set_db $sp .preserve false
}
}
ungroup -all -flatten -force
set_db ui_respects_preserve true

Note:Ungrouping preserved instances might lead to violation of designer's intent.

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 Genus Quick Start Guide: Timing Analysis

4.5. Optimizing endpoints

Genus works on the critical path (WNS) of each cost group until there is no more
improvement. The non-critical paths can be downsized for area saving. In the TNS
optimization mode, all endpoints of the cost group are optimized.

Optimizing for TNS reduces the number of violating paths and might reduce WNS
in some cases. However, there is a drawback on runtime and possible area
increase. To enable TNS optimization, use:

set_db tns_opto true

The user can also make mapper treat paths with a slack within the specified range
from the WNS as critical paths to help optimizing TNS using the command

set_db tns_critical_range <delay>

4.6. Re-timing

Retiming is an advanced optimization technique where registers are re-positioned

to reduce cycle time or area without changing the input-output latency of the
design. This technique is best fitted for a design that can be pipelined. The
drawback of this technique is possible problem in formal verification. Retiming can
be enabled at the top level or selective modules manually using the ‘retime’
attribute.

set_db <design/module/submodule>.retime true

This must be specified before generic stage.

4.7. Hard Regions

Use the hard_region attribute to specify hierarchical instances that are recognized
as hard regions in the user floorplan during logic synthesis and to preserve pins
and subports.

Place and route tools operate better if the user design has no buffers between
regions at the top level. To accommodate this, specify hard regions before
mapping. The regular boundary optimization related controls are also applicable
to hard regions.

set_db module:dtmf_recvr_core/power_manager .hard_region true

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 Genus Quick Start Guide: Timing Analysis
4.8. Ideal Nets

Genus automatically puts ideal attributes on the HFNs. The tool will automatically
idealize clock nets and asynchronous reset nets (only net connected directly to the
asynchronous reset pin of a flop). For all the other HFNs, except clocks and resets,
it will try to buffer these to satisfy the DRC rules. If the critical path has a buffer
chain due to HFN, idealize the net in Genus and buffer HFN later, during Place
and Route for a more efficient buffer tree.

To stop Genus from doing HFN synthesis with a fanout is greater than threshold,
issue the following commands:

set_db [get_db ports * -if { .direction == in && pin_fanouts >

<threshold>}] .ideal_driver true //top level input ports

4.9. Combinational Feedback Loops

Unnecessary buffering of must be avoided during synthesis stage wherever

possible. A combinational feedback loop is a path that can be traced - through
combinational logic - back to the starting point. To analyze such a path, the Genus
requires to break the loop at some point within the loop. By default, Genus
identifies each feedback loop, inserts a buffer from the technology library on the
feedback loop and disables the timing arc from its input to the output, thus breaking
the timing loop. These cells follow the cdn_loop_breaker<number> nomenclature,
and therefore, they are easily identified in the synthesized netlist.

Note: cdn_loop_breaker cells are inserted when the first report_timing command
is issued (before syn_generic).If there is no ‘report_timing’ before
syn_generic, then cdn_loop_breakers are inserted during the generic synthesis.

Ideally once Genus reports that a timing loop is broken, the user must determine
if it was broken in a safe location, without disabling any valid timing path. If it is a
safe location to break the loop, the user should hard code this loop-breaking point
in the user SDC file using the ‘set_disable_timing’ command. Once the loop
breaker instances inserted by Genus are removed, the user can break the loops
manually using the ‘set_disable_timing’ SDC constraint.

If the user executes the ‘remove_cdn_loop_breaker’ command before writing

out the design database for Innovus, the output netlist will still have the
cdn_loop_breaker instances. This is because when writing out the design
database, the timer is triggered to calculate SDC, causing the loop breakers to be
re-inserted. To get around this, run the ‘remove_cdn_loop_breaker’
command again, then execute the ‘write_hdl’ command to write out the netlist
to replace with the one written by ‘write_design’ command.

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 Genus Quick Start Guide: Timing Analysis

4.10. Effort levels for synthesis

Speculation reverses the effects of resource sharing between multiplexors and

datapath resources, such as adders if the critical path comes in through the select
lines (the control lines) of the mux. Use the ‘syn_generic’command with high
effort to enable speculation. Use this command if the critical path has both a mux
followed by an arithmetic resource.

set_db ultra_global_mapping true

This enhanced optimization algorithms are only available when the user uses the
syn_map command with high effort. This attribute is automatically enabled when
the user uses physical-aware mapping and physical-aware structuring.

Multiple incremental synthesis runs can help to improve timing result. It is a

common practice to try a couple of incremental runs until there is no more
improvement. If runtime is not a concern, one can try the Ultra Incremental mode
by setting the ‘iopt_ultra_optimization’ attribute. In this mode, Genus will
work rigorously to achieve the best result.

set_db iopt_sequential_duplication true

If the user sees buffering to break huge fanouts in a register to register path try
sequential duplication for the transitive fanout to avoid buffering.

4.11. Modifying Constraints

If none of the above techniques work, probably the user may have to modify the
constraints. Even if that is unable to resolve the issue, the change must be made
in the RTL level.

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 Genus Quick Start Guide: Timing Analysis

5. Timing Analysis for MMMC Design

MMMC analysis includes multiple modes of operation of the device and multiple corners
to model the behavior of delay for the different combination of the libraries, PVT and
constraints. Combination of these as specified are the different views.

The goal of timing analysis for an MMMC design is to meet the timing in one analysis
view without affecting the remaining. Luckily Genus is intelligent enough to take care the
timing of all the views while focusing on one.

User must take care of the worst-case analysis view, and work towards it using the steps
discussed for a non MMMC design. Genus will take care of the other views.
The user can report_qor to see the performance in each view. If the timing is not met or
up to the mark in the other views, the user can focus on them separately. There won’t be
much changes in first view the user had worked on.

6. LAB
The design files are provided as an attachment along with this document. The scripts are
in the SCRIPTS folder. The script run.tcl is for non-mmmc design and run_mmmc.tcl for
the mmmc design.

6.1 Non-MMMC Design

1. Open the SDC file in the constraints directory and read the contents. Read and
understand the SDC file properly.

1.1 The logic assignment for test mode and scan enable port are set to 0 disabling
them.

1.2 The clock waveforms are associated with the ports.

1.3 The false path is defined from reset port and test mode ports.

1.4 The hold analysis through clock enable pin is also marked as false path.(Genus
doesn't do hold analysis but passes the constraints as such to the PnR tools)

1.5 All the input and output pin delays are 300ps with respect to their appropriate
clocks except for some anomalies for the output pins in the end. They are to be
corrected. The -add_delay option is used with multiple clock sources to analyze

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 Genus Quick Start Guide: Timing Analysis
different modes in one run, such as scan or test modes, or different operating
modes corresponding to different speeds.

1.6 The design constraints max transition and fanout are also specified.

1.7 There is also a max path delay constraint on all paths from m_clk to itself.
This means it overrides the clock period for m_clk with the max_delay specified.

2. At checkpoint A, check for failed SDC commands and timing intent warnings. Fix
the intent warnings if necessary

There are no failed SDC commands, however there are 93 timing intent warning.

For example,

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 Genus Quick Start Guide: Timing Analysis

Here we have nine inputs, outputs and inout ports without clocked external delays
5 of them are power pins which can be ignored.
From the GUI, scan_in[2:0] and scan_out[2:0] ports are not at all connected in the
circuit at present.
The last one tdsp_pso is connected to power manager instance to power_down
pin. Similarly switch_en_out can be ignored.
Hence all 9 can be ignored.
Similarly check whether the warnings need fix and eliminate the implications of all
the warnings.

3. At check point B, you can uncomment the code to create cost groups, path adjusts
and TNS optimization technique and complete the synthesis. You must specify
your own delay value and weights for different groups and understand

4. At check point C, analyze and debug the timing violations (if any) and go back to
the necessary stages and update the constraints or attributes as required. (The
aim of the synthesis is to get slack within 10% of the fastest clock’s period which
is 300ps. )

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 Genus Quick Start Guide: Timing Analysis
The results of various runs and their corresponding observations are quantified below.

Note: All the timing numbers are reported in ps.

A: No optimization techniques were applied
B: Only cost groups were defined and reg2reg group had a weight of 2
C: Only cost groups were defined and reg2reg group had a weight of 5
D: Only path adjust was defined with -500ps for reg2reg and -200ps for reg2out and 200 for the rest
E: Only path adjust was defined with -1000ps for reg2reg and -400ps for reg2out and 200 for the rest
F: Cost groups were defined and reg2reg group had a weight of 2 and path adjust was defined with
-1000ps for reg2reg and -400ps for reg2out and 200 for the rest
G: Cost groups were defined and reg2reg group had a weight of 2 and path adjust was defined with
-250ps for reg2reg and -200ps for reg2out and 200 for the rest

Stages syn_gen syn_map syn_opt

R2R R2R R2O R2R R2O
A -1120 - 918 - 60 - 560 - 252
B -1120 - 914 - 60 - 417 - 118
C -1120 - 914 - 60 - 520 - 250
In this specific design, pertaining to this slack, we see that a weight of 5 was more of an over constrain for
the tool, hence optimum results were obtained with a lower weight. The user is encouraged to try with
different weights to understand how the tool reacts.

Stages syn_gen syn_map syn_opt

R2R R2R R2O R2R R2O
A -1120 - 918 - 60 - 560 - 252
D -1120 -1052 - 60 - 413 - 129
E -1196 -1023 - 60 - 343 - 177
Tightening the constraint by 1000ps on reg2reg and 400ps on reg2out proved more effective in making the
tool focus on them compared to, 500ps and 200ps respectively.

Stages syn_gen syn_map syn_opt

R2R R2R R2O R2R R2O
A -1120 - 918 - 60 - 560 - 252
F -1192 - 915 - 60 - 293 - 150
G -1192 - 950 - 60 - 446 - 125
In this the weight for reg2reg path in both cases is 2. As observed above, tightening the constraint by
1000ps on reg2reg and 400ps on reg2 out proved more efficient in focusing on those paths and furthermore
using it in conjunction with the cost group of weight 2 for reg2reg path produced the best results among all
these iterations.

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 Genus Quick Start Guide: Timing Analysis

The major effect of the cost group and path groups were seen after the optimization stage.
The cost group multiples the WNS with the path adjusts included, with the specified
weight, during optimization.
The values for the constraints and attributes must be set only after properly analyzing the
results.

Our analysis in R2R proved satisfactory. To analyze the timing of the R20 path group,use
the command ‘report_timing -group R20’.It shows that there is already a negative
slack. So, we must look at the constraints and change the output delay of 2.3 to 0.3ns as
it was the anomaly we missed in the beginning. Note that here we don’t have the Clock
Edge field, rather we have the Path Delay field, since we have set maximum delay for all
paths from m_clk to itself in the sdc file.

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 Genus Quick Start Guide: Timing Analysis

6.2 MMMC Design

First task is to analyze the mmmc.tcl file in the work directory to understand the various
lib files used, constraints and their combinations to make the views. There are 6 SDC files
which can be accessed from Constraints_MMMC directory.
Read through all of them to get an idea about the constraints.
The user can see that all 4 views are using the various functional mode constraints and
a single test mode.

Run the run_mmmc.tcl file. Upon checking the timing intent, the user can see that each
view has different warnings. Solve them if they are necessary.

After having successfully eliminated the implications of all the warnings, next step is to
create cost groups and path adjusts for each group and analyze. Only the reg2reg path
of the fast view had a negative slack. Hence it was given a weight of 5 and a path adjust
of -200 and the rest 200. The user is encouraged to change these values and understand
the behavior of the tool for various values.

After syn_opt stage, the slack has turned to a positive value and hence the design in
closed for timing.

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 Genus Quick Start Guide: Timing Analysis

Summary
This application note had guided through the basic checks, analysis and optimization
techniques for Timing Analysis. It has also demonstrated them on a design.

References
• Genus Timing Analysis Guide for Common UI

Further Reading
• Genus Synthesis Solution™ Constraints : Appnote defining all the relevant
constraints to be used.

Support
Cadence Online Support provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.

Videos
Refer to video library for Genus Synthesis Solution on COS:
http://support.cadence.com/TrainingBytes/Genus

Feedback
Email comments, questions, and suggestions to [email protected].

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