HISTORY:-

The first hardware description languages appeared in the late 1960s, looking like
more traditional languages.[2] The first that had a lasting effect was described in
1971 in C. Gordon Bell and Allen Newell's text Computer Structures.[3] This text
introduced the concept of register transfer level, first used in the ISP language
to describe the behavior of the Digital Equipment Corporation (DEC) PDP-8.[4]

The language became more widespread with the introduction of DEC's PDP-16 RT-Level
Modules (RTMs) and a book describing their use.[5] At least two implementations of
the basic ISP language (ISPL and ISPS) followed.[6][7] ISPS was well suited to
describe relations between the inputs and the outputs of the design and was quickly
adopted by commercial teams at DEC, as well as by a number of research teams both
in the US and among its NATO allies.

The RTM products never took off commercially and DEC stopped marketing them in the
mid-1980s, as new techniques and in particular very-large-scale integration (VLSI)
became more popular.

Separate work done about 1979 at the University of Kaiserslautern produced a

language called KARL ("KAiserslautern Register Transfer Language"), which included
design calculus language features supporting VLSI chip floorplanning[jargon] and
structured hardware design. This work was also the basis of KARL's interactive
graphic sister language ABL, whose name was an initialism for "A Block diagram
Language".[8] ABL was implemented in the early 1980s by the Centro Studi e
Laboratori Telecomunicazioni (CSELT) in Torino, Italy, producing the ABLED graphic
VLSI design editor. In the mid-1980s, a VLSI design framework was implemented
around KARL and ABL by an international consortium funded by the Commission of the
European Union.[9]

By the late 1970s, design using programmable logic devices (PLDs) became popular,
although these designs were primarily limited to designing finite state machines.
The work at Data General in 1980 used these same devices to design the Data General
Eclipse MV/8000, and commercial need began to grow for a language that could map
well to them. By 1983 Data I/O introduced ABEL to fill that need.

As design shifted to VLSI, the first modern HDL, Verilog, was introduced by Gateway
Design Automation in 1985. Cadence Design Systems later acquired the rights to
Verilog-XL, the HDL simulator that would become the de facto standard of Verilog
simulators for the next decade. In 1987, a request from the U.S. Department of
Defense led to the development of VHDL (VHSIC Hardware Description Language). VHDL
was based on the Ada programming language, as well as on the experience gained with
the earlier development of ISPS.[10] Initially, Verilog and VHDL were used to
document and simulate circuit designs already captured and described in another
form (such as schematic files). HDL simulation enabled engineers to work at a
higher level of abstraction than simulation at the schematic level, and thus
increased design capacity from hundreds of transistors to thousands.[citation
needed]

The introduction of logic synthesis for HDLs pushed HDLs from the background into
the foreground of digital design. Synthesis tools compiled HDL source files
(written in a constrained format called RTL) into a manufacturable netlist
description in terms of gates and transistors. Writing synthesizable RTL files
required practice and discipline on the part of the designer; compared to a
traditional schematic layout, synthesized RTL netlists were almost always larger in
area and slower in performance[citation needed]. A circuit design from a skilled
engineer, using labor-intensive schematic-capture/hand-layout, would almost always
outperform its logically-synthesized equivalent, but the productivity advantage
held by synthesis soon displaced digital schematic capture to exactly those areas
that were problematic for RTL synthesis: extremely high-speed, low-power, or
asynchronous circuitry.

Within a few years, VHDL and Verilog emerged as the dominant HDLs in the
electronics industry, while older and less capable HDLs gradually disappeared from
use. However, VHDL and Verilog share many of the same limitations: neither is
suitable for analog or mixed-signal circuit simulation; neither possesses language
constructs to describe recursively-generated logic structures. Specialized HDLs
(such as Confluence) were introduced with the explicit goal of fixing specific
limitations of Verilog and VHDL, though none were ever intended to replace them.

Over the years, much effort has been invested in improving HDLs. The latest
iteration of Verilog, formally known as IEEE 1800-2005 SystemVerilog, introduces
many new features (classes, random variables, and properties/assertions) to address
the growing need for better test bench randomization, design hierarchy, and reuse.
A future revision of VHDL is also in development[when?], and is expected to match
SystemVerilog's improvements.

Structure of HDL:-
HDLs are standard text-based expressions of the structure of electronic systems and
their behaviour over time. Like concurrent programming languages, HDL syntax and
semantics include explicit notations for expressing concurrency. However, in
contrast to most software programming languages, HDLs also include an explicit
notion of time, which is a primary attribute of hardware. Languages whose only
characteristic is to express circuit connectivity between a hierarchy of blocks are
properly classified as netlist languages used in electric computer-aided design
(CAD). HDL can be used to express designs in structural, behavioral or register-
transfer-level architectures for the same circuit functionality; in the latter two
cases the synthesizer decides the architecture and logic gate layout.

HDLs are used to write executable specifications for hardware. A program designed
to implement the underlying semantics of the language statements and simulate the
progress of time provides the hardware designer with the ability to model a piece
of hardware before it is created physically. It is this executability that gives
HDLs the illusion of being programming languages, when they are more precisely
classified as specification languages or modeling languages. Simulators capable of
supporting discrete-event (digital) and continuous-time (analog) modeling exist,
and HDLs targeted for each are available.

Comparison with control-flow languages:-

It is certainly possible to represent hardware semantics using traditional
programming languages such as C++, which operate on control flow semantics as
opposed to data flow, although to function as such, programs must be augmented with
extensive and unwieldy class libraries. Generally, however, software programming
languages do not include any capability for explicitly expressing time, and thus
cannot function as hardware description languages. Before the introduction of
System Verilog in 2002, C++ integration with a logic simulator was one of the few
ways to use object-oriented programming in hardware verification. System Verilog is
the first major HDL to offer object orientation and garbage collection.

Using the proper subset of hardware description language, a program called a

synthesizer, or logic synthesis tool, can infer hardware logic operations from the
language statements and produce an equivalent netlist of generic hardware
primitives[jargon] to implement the specified behaviour.[citation needed]
Synthesizers generally ignore the expression of any timing constructs in the text.
Digital logic synthesizers, for example, generally use clock edges as the way to
time the circuit, ignoring any timing constructs. The ability to have a
synthesizable subset of the language does not itself make a hardware description
language.
VHDL Data Types and Operators:-
We have mainly been using the STD_LOGIC and STD_LOGIC_VECTOR data types so far in
this course. The BIT_VECTOR data type was introduced in the previous tutorial.

This part of the course will look at some of the other data types that are
available in VHDL as well as VHDL operators. We will then look at which VHDL
operators can operate on which data types.

This is not a full list of all the data types and operators in VHDL. It also does
not contain an explanation of all the operators shown, rather the purpose of this
part of the course is to show you where the data types and operators that you have
been using so far fit into the bigger picture of VHDL.

VHDL Data Types

VHDL has a set of standard data types (predefined / built-in). It is also possible
to have user defined data types and subtypes.

Some of the predefined data types in VHDL are: BIT, BOOLEAN and INTEGER.

The STD_LOGIC and STD_LOGIC_VECTOR data types are not built-in VHDL data types, but
are defined in the standard logic 1164 package of the IEEE library. We therefore
need to include this library in our VHDL code and specify that the STD_LOGIC_1164
package must be used in order to use the STD_LOGIC data type:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
We will look at only the data types used so far in the course, namely STD_LOGIC and
BIT, as well as their vector forms: STD_LOGIC_VECTOR and BIT_VECTOR.

BIT
The BIT data type can only have the value 0 or 1. When assigning a value of 0 or 1
to a BIT in VHDL code, the 0 or 1 must be enclosed in single quotes: '0' or '1'.

BIT_VECTOR
The BIT_VECTOR data type is the vector version of the BIT type consisting of two or
more bits. Each bit in a BIT_VECTOR can only have the value 0 or 1.

When assigning a value to a BIT_VECTOR, the value must be enclosed in double

quotes, e.g. "1011" and the number of bits in the value must match the size of the
BIT_VECTOR.

STD_LOGIC
The STD_LOGIC data type can have the value X, 0, 1 or Z. There are other values
that this data type can have, but the other values are not synthesizable – i.e.
they can not be used in VHDL code that will be implemented on a CPLD or FPGA.

These values have the following meanings:

X – unknown
0 – logic 0
1 – logic 1
Z – high impedance (open circuit) / tristate buffer
When assigning a value to a STD_LOGIC data type, the value must be enclosed in
single quotes: 'X', '0', '1' or 'Z'.

STD_LOGIC_VECTOR
The vector version of the STD_LOGIC data type. Each bit in the set of bits that
make up the vector can have the value X, 0, 1 or Z.
When assigning a value to a STD_LOGIC_VECTOR type, the value must be enclosed in
double quotes, e.g. "1010", "ZZZZ" or "ZZ001". The number of bits in the value must
match the size of the STD_LOGIC_VECTOR.

VHDL Operators
Some of the VHDL operators are listed below. Not all operators can operate on all
data types. Operators will be explained as they are used in this course.

Logical Operators
NOT, AND, NAND, OR, NOR, XOR and XNOR.

Arithmetic Operators
+ addition
- subtraction
* multiplication
/ division
ABS absolute value
MOD modulus
REM remainder
** exponent
Comparison Operators
= equal to
/= not equal to
< less than
> greater than
<= less than or equal to
>= greater than or equal to
Shift Operators
sll – shift left logical
srl – shift right logical
sla – shift left arithmetic
sra – shift right arithmetic
rol – rotate left
ror – rotate right

VHDL Operators usable on Data Types

The following operators can be used on the data types listed.

Logical Operators
Logical operators can operate on:

BIT and BIT_VECTOR

STD_LOGIC and STD_LOGIC_VECTOR

(also on other data types: STD_ULOGIC and STD_ULOGIC_VECTOR)

Arithmetic Operators
The STD_LOGIC_VECTOR data type can be used in addition and subtraction operations
(+ and -) if the STD_LOGIC_SIGNED or the STD_LOGIC_UNSIGNED package of the IEEE
library is used.

(Otherwise the arithmetic operators can only be used with INTEGER, SIGNED and
UNSIGNED data types)

Comparison Operators
BIT and BIT_VECTOR
STD_LOGIC and STD_LOGIC_VECTOR

(also on STD_ULOGIC, STD_ULOGIC_VECTOR, INTEGER, SIGNED and UNSIGNED)

Shift Operators
Shift operators can only be used on BIT_VECTOR data types.