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Verilog Assignment1

The document describes several Verilog modules for common digital logic components: 1) Binary to gray code and gray code to binary converters 2) A carry lookahead adder 3) A 2-bit comparator 4) A 3-input decoder and corresponding 3-to-8 line encoder 5) A ripple carry 4-bit adder using full adders 6) 2-to-1 and 4-to-1 multiplexers 7) Testbenches for the multiplexer modules

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88 views

Verilog Assignment1

The document describes several Verilog modules for common digital logic components: 1) Binary to gray code and gray code to binary converters 2) A carry lookahead adder 3) A 2-bit comparator 4) A 3-input decoder and corresponding 3-to-8 line encoder 5) A ripple carry 4-bit adder using full adders 6) 2-to-1 and 4-to-1 multiplexers 7) Testbenches for the multiplexer modules

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Alfiya
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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1.

binary to gray

module binary_to_gray(input [3:0] bin,


output [3:0] G );

assign G[3] = bin[3];


assign G[2] = bin[3] ^ bin[2];
assign G[1] = bin[2] ^ bin[1];
assign G[0] = bin[1] ^ bin[0];

endmodule
2.Carry look ahead
module CLA_Adder(a,b,cin,sum,cout);
input[3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4;
assign p0=(a[0]^b[0]),
p1=(a[1]^b[1]),
p2=(a[2]^b[2]),
p3=(a[3]^b[3]);
assign g0=(a[0]&b[0]),
g1=(a[1]&b[1]),
g2=(a[2]&b[2]),
g3=(a[3]&b[3]);
assign c0=cin,
c1=g0|(p0&cin),
l c2=g1|(p1&g0)|(p1&p0&cin),

c3=g2|(p2&g1)|(p2&p1&g0)|(p1&p1&p0&cin),

c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p
1&p0&cin);
assign sum[0]=p0^c0,
sum[1]=p1^c1,
sum[2]=p2^c2,
sum[3]=p3^c3;
assign cout=c4;

endmodule
3.Comparator

module comparator(input [1:0] A,B, output A_less_B,


A_equal_B, A_greater_B);
wire tmp1,tmp2,tmp3,tmp4,tmp5, tmp6, tmp7, tmp8;

xnor u1(tmp1,A[1],B[1]);
xnor u2(tmp2,A[0],B[0]);
and u3(A_equal_B,tmp1,tmp2);

assign tmp3 = (~A[0])& (~A[1])& B[0];


assign tmp4 = (~A[1])& B[1];
assign tmp5 = (~A[0])& B[1]& B[0];
assign A_less_B = tmp3 | tmp4 | tmp5;
assign tmp6 = (~B[0])& (~B[1])& A[0];
assign tmp7 = (~B[1])& A[1];
assign tmp8 = (~B[0])& A[1]& A[0];
assign A_greater_B = tmp6 | tmp7 | tmp8;
endmodule
4. decoder

module Decoder(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(~a&~b&~c),
d1=(~a&~b&c),
d2=(~a&b&~c),
d3=(~a&b&c),
d4=(a&~b&~c),
d5=(a&~b&c),
d6=(a&b&~c),
d7=(a&b&c);
endmodule
5. encoder

module Encoder(d0,d1,d2,d3,d4,d5,d6,d7,a,b,c);
input d0,d1,d2,d3,d4,d5,d6,d7;
output a,b,c;
or(a,d4,d5,d6,d7);
or(b,d2,d3,d6,d7);
or(c,d1,d3,d5,d7);
endmodule
6. ripplecarry adder

module rippeladder4(a, b, S, Co);


input [3:0] a, b;
output [3:0] S;
output Co;
wire w1, w2, w3;

fulladder u1(a[0], b[0], 1'b0, S[0], w1);


fulladder u2(a[1], b[1], w1, S[1], w2);
fulladder u3(a[2], b[2], w2, S[2], w3);
fulladder u4(a[3], b[3], w3, S[3], Co);
endmodule

module fulladder(a, b, Ci, S, Co);


input a, b, Ci;
output S, Co;
wire w1,w2,w3;

xor e(w1, a, b);


xor f(S, w1, Ci);
and g(w2, w1, Ci);
and h(w3, a, b);
or i(Co, w2, w3);
endmodule
7. gray to binary

module gray_to_binary (input [3:0] G,


output [3:0] bin
);

assign bin[3] = G[3];


assign bin[2] = G[3] ^ G[2];
assign bin[1] = G[3] ^ G[2] ^ G[1];
assign bin[0] = G[3] ^ G[2] ^ G[1] ^ G[0];

endmodule

gray tobinary_tb
8. mux2
module mux2(a,b,s,y);
input a,b,s;
output y;
assign y=((~s)&a)|(s&b);
endmodule

mux2_tb
module mux2_tb();

reg a,b,s;
wire y;
mux2 dut_any_name
(
.a(a),
.b(b),
.s(s),
.y(y));

initial
begin
a=1'b0;
b=1'b0;
s=1'b0;
#10
a=1'b0;
b=1'b1;
s=1'b1;
#10
$finish;
end
endmodule
9. mux4
module mux4(a,b,c,d,s,y);
input [2:0]a,b,c,d;
input [1:0]s;
output [3:0]y;
assign y= s[1]? (s[0]?d:c): (s[0]?b:a);
endmodule

mux4_tb
module mux4_tb();
reg [2:0] a,b,c,d;
reg [1:0]s;
wire [3:0]y;
mux4 aaa (.a(a),.b(b),.c(c),.d(d),.s(s),.y(y))
initial
begin
a=2’b01;
b=2’b00;
c=2’b01;
d=2’b10;
s=1’b0;
#10
a=2’b10
c=2’b11;
d=2’b00;
s=1’b1;
#10
$finish;
end
endmodule

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