DFT Lab Manual

VLSI Test Seminar-Bangalore

(21-22 September 2019)

LAB-1: Scan Insertion and DRC Analysis:

Upon completion of this lab, we will be able to:
a. Understand Scan insertion inputs and libraries
b. Define Clock and reset constraints
c. Define Scan constraint and configuration
d. Understand and analyse different Scan configurations
e. Convert normal flops into scan flops
f. Analyse and understand Scan DRC issues
g. Scan DRC fixing
h. Scan insertion and stitching
Linux > mkdir labs
Linux > cd labs
Linux> cp –r /home/dft/LAB-1 ./
Linux> cd LAB-1

DIRECTORY STRUCTURE
inputs/ => verilog netlist
scripts/ => scripts to invoke tool and dofiles for execution of task.
reports/ => Directory to save all reports
outputs/ => To write out Scan inserted Netlist and SPF files
logs/ => To save log files

TO INVOKE THE SCAN INSERTION TOOL

Linux > source scripts/run

WITH DRC VIOLATIONS

dc_shell > source scripts/scan_script.tcl

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 DFT Lab Manual
VLSI Test Seminar-Bangalore
(21-22 September 2019)

WITH DRC VIOLATIONS FIXED

dc_shell > source scripts/scan_script_fixed.tcl

dc_shell > exit

QUIZ:

1. Total DRC violations? __________________________________________

2. List the name, number and cause of Violations
_____________________________________________________________
_____________________________________________________________
3. How many total sequential cells in the design? _______________________
4. How many Sequential cells with violations? _________________________
5. How many Sequential cells without violations? _______________________
6. List out DRC fix commands ______________________________________
________________________________________________________________________
________________________________________________________________________
7. What are the output files of the scan insertion? _______________________
_____________________________________________________________
8. What is the full form of SPF? _____________________________________
9. What information contains in SPF? ________________________________
_______________________________________________________________________
10.What is the use of create test protocol? _____________________________
________________________________________________________________________

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 DFT Lab Manual
VLSI Test Seminar-Bangalore
(21-22 September 2019)

LAB-2: Scan Compression Logic Insertion

Insertion of scan logic with scan along with Scan compression. At the end of the
Lab, you will be able to:
a. Configure Scan compression
b. Scan compression with compression ratio of 10
c. Scan compression by configuring exact scan chain length
d. Insert scan with compression
e. Understand different types of Test Mode configuration.
Linux > cd labs
Linux> cp –r /home/dft/LAB-2 ./
Linux> cd LAB-2

DIRECTORY STRUCTURE
inputs/ => verilog netlist
scripts/ => scripts to invoke dc_shell and dofile for scan compression logic
reports/ => Directory to save all reports
outputs/ => To write out Verilog netlist with embedded compression logic
logs/ => To save log files

TO INVOKE THE SCAN COMPRESSION LOGIC INSERTION TOOL

Linux > source scripts/run

TO GENERATE SCAN COMPRESSION LOGIC

Dc_shell > source scripts/scan_compress.tcl

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 DFT Lab Manual
VLSI Test Seminar-Bangalore
(21-22 September 2019)

QUIZ:

1. Analyze the scan chain configuration in Internal_Scan mode and

Compression mode ____________________________________________
____________________________________________________________
2. Check the Scan chain length of all Scan chains ______________________
____________________________________________________________
3. What are the inputs for SCAN Compression? _______________________
____________________________________________________________
4. Command used for scan stitching and inserting compression? __________
____________________________________________________________
5. What are the output files from Scan Compression? ____________________
_____________________________________________________________
6. What are blocks / modules added after Scan compression? ______________

LAB-3: Boundary Scan (JTAG 1149.1) Implementation

Boundary scan logic insertion and Analysis of the inserted logic to operate in
different modes. Upon completion of the Lab, you will be able to:
a. Understand JTAG architecture
b. Understand different JTAG instructions
c. Insert Boundary scan logic using different boundary scan cells
d. Generate Boundary scan logic testbench for simulations

Linux > cd labs

Linux> cp –r /home/dft/LAB-3 ./
Linux> cd LAB-3

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 DFT Lab Manual
VLSI Test Seminar-Bangalore
(21-22 September 2019)

DIRECTORY STRUCTURE
inputs/ => verilog netlist
scripts/ => scripts to invoke BSD Compiler and Boundary scan logic generation
reports/ => Directory to save all reports
outputs/ => To write out JTAG logic inserted netlist
logs/ => To save log files

TO INVOKE BOUNDARY SCAN INSERTION TOOL

Linux > source scripts/run

TO GENERATE BOUNDARY SCAN LOGIC

Dc_shell > source scripts/bsd_insertion

QUIZ:
a. Check the instruction codes of all the instructions

b. Understand the TAP configurations

c. Analyze BSD inserted netlist

d. What are mandatory Instructions in JTAG?

e. What are mandatory pins in JTAG implementation?

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 DFT Lab Manual
VLSI Test Seminar-Bangalore
(21-22 September 2019)

LAB-4: Automatic Test Pattern Generation (ATPG) for

Stuck-at & Transition Fault Models and Simulation
Test pattern generation using Scan inserted netlist. At the end of the Lab, you will
be able to understand ATPG for various fault models, compression and non-
compression modes:
a. Read Scan inserted netlist in ATPG tool and read libraries
b. Build model
c. Run Design Rule Check (DRC)
d. DRC analysis and fix DRC issues
e. Scan chain tracking
f. Clock/Reset/ DRCs
g. Understand equivalent faults and fault collapsing
h. ATPG pattern generation for Stuck-at and At-speed fault models
i. ATPG pattern simulation flow (Zero Delay)
j. Stuck-at ATPG serial patterns simulation
k. Transition ATPG serial patterns simulation

STUCK-AT
Linux > cd labs
Linux> cp –r /home/dft/LAB-4 ./
Linux> cd LAB-4/Stuck

DIRECTORY STRUCTURE
inputs/ => verilog netlist, SPF, dofiles
scripts/ => scripts to invoke Tetramax tool and generate ATPG patterns
reports/ => Directory to save all reports
outputs/ => To write out ATPG patterns, Test coverage reports, Testbench
logs/ => To save log files

Sponsorship: ChipEdge Technologies Pvt. Ltd.

 DFT Lab Manual
VLSI Test Seminar-Bangalore
(21-22 September 2019)

TO INVOKE THE ATPG TOOL

Linux > source scripts/run
WITH DRC VIOLATIONS
tmax > source scripts/run_tmax.tcl
WITH DRC VIOLATIONS FIXED
tmax > source scripts/run_tmax_fixed.tcl
CONVERT STIL TO VERILOG
Don’t close the tmax session, Type the below command in tmax session
sh xterm &
source scripts/stil2ver.tcl
GENERATE SIMULATION EXECUTABLES FOR VCS SIMULATOR
source scripts/gen_simv.tcl
SIMULATE ATPG PATTERNS
source scripts/run_sim.tcl
Observe the simulation window

TRANSITION ATPG
Linux > cd labs
Linux> cd LAB-4/Transition

DIRECTORY STRUCTURE
inputs/ => verilog netlist, SPF, dofiles
scripts/ => scripts to invoke Tetramax tool and generate ATPG patterns
reports/ => Directory to save all reports
outputs/ => To write out ATPG patterns, Test coverage reports, Testbench
logs/ => To save log files

Sponsorship: ChipEdge Technologies Pvt. Ltd.

 DFT Lab Manual
VLSI Test Seminar-Bangalore
(21-22 September 2019)

TO INVOKE THE ATPG TOOL

Linux > source scripts/run
RUN ATPG
tmax > source scripts/run_tmax.tcl
CONVERT STIL TO VERILOG
Don’t close the tmax session, Type the below command in tmax session
sh xterm &
source scripts/stil2ver.tcl
GENERATE SIMULATION EXECUTABLES FOR VCS SIMULATOR
source scripts/gen_simv.tcl
SIMULATE ATPG PATTERNS
source scripts/run_sim.tcl
Observe the simulation window

QUIZ:
a. How many scan chains are present? ________________________________

b. What is the maximum scan chain length? ____________________________

c. Total number of faults = ____?

d. What is the test coverage with 100 atpg patterns? _____________________

e. Is this a serial simulation or parallel simulation? ______________________

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 DFT Lab Manual
VLSI Test Seminar-Bangalore
(21-22 September 2019)

LAB-5: Timing based (SDF) ATPG Pattern Simulations for

Stuck-at Model and Debug
ATPG pattern simulation for stuck-at fault model and debugging simulations
failures. At the end of the Lab, you should be able to understand:

a. ATPG pattern generation

b. ATPG pattern simulation using Timing information (SDF)
c. ATPG pattern simulation failure and debug

Linux > cd labs

Linux> cp –r /home/dft/LAB-5 ./
Linux> cd LAB-5

DIRECTORY STRUCTURE
inputs/ => verilog netlist, SPF, dofiles, SDF (standard delay format)
dig_top_pd.spf => spf file
scripts/ => scripts to invoke Tetramax tool and generate ATPG patterns
reports/ => Directory to save all reports
outputs/ => To write out ATPG patterns, Test coverage reports, Testbench
logs/ => To save log files

TO INVOKE THE ATPG TOOL

Linux > source scripts/run

RUN TMAX FOR PATTERN GENERATION

tmax > source scripts/run_tmax.tcl

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 DFT Lab Manual
VLSI Test Seminar-Bangalore
(21-22 September 2019)

CONVERT STIL TO VERILOG

Don’t close the tmax session, Type the below command in tmax session
sh xterm &
source scripts/stil2ver.tcl

GENERATE SIMULATION EXECUTABLES FOR VCS SIMULATOR

source scripts/gen_simv.tcl

SIMULATE ATPG PATTERNS

source scripts/run_sim.tcl

QUIZ:
a. Do you see any simulation failures?

b. How many failures with 100 patterns?

c. Is this serial simulation or parallel simulation?

d. Analyze the failures using interactive mode.

e. Do you see any timing violation affecting simulations?

If yes, SETUP or HOLD?

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