Chapter 1: Operators

1) Types of operators based on their usage w.r.t operanads

a) Unary – Used in front of one operand (~a)

b) Binary – Used between two operands (a && b)
c) Ternary – Used in pairs between 3 operands (a ? b : c)

2) Single line and multiple line comments are allowed

3) 0, 1, x and z are the four possible values a vector/scalar reg/wire/datatype can

have in Verilog. There are 8 possible drive strengths in verilog (only for value
levels 0 and 1, but not for x and z). They are supply, strong, pull, large, weak,
medium, small, highz (supply has the strongest degree and highz has the weakest)

4) -4’d2 is allowed, but it is illegal to have a – between base format and number as in
4’d-2

5) A ‘?’ is equivalent to ‘z’

6) \t (tab), \n (new line) and \b (blank space) are the 3 possible spaces in Verilog.
The space in the string (anything between “ “) is anyway a space 

7) Nets – wire, wand, wor, tri, triand, trior, trireg. Except trireg, nets have a default
value of ‘z’. ‘trireg’ defaults to ‘x’

8) Registers – default to ‘x’. It stores bits as an unsigned value (logic can interpret
sign)

9) Scalar => 1 bit, Vector => multiple bits.

reg [3:0] a;
reg [0:3] b;

a = 4’b1; // 1 goes into bit 0

b = 4’b1; // 1 goes into bit 3

10) Vector part select – useful in variable for loops

byte0 = data [31-:8]; // byte0 = data [31:24]

byte1 = data [24+:8]; //byte1 = data [31:24]

11) Register types also include integer, real and time.

integer – size depends on host machine (typically 32 bits), signed
real – default to ‘0’, round off to the nearest integer if assigned to an integer
 time – size depends on implementation.

12) Verilog arrays are allowed for reg, integer, time, real, realtime.

A verilog array has multiple elements which are 1-bit or n-bit wide

Eg1: reg mem [31:0]; //32 elements, each of 1-bit width

Eg2: reg [2:0] mem [31:0]; //32 elements, each of 3-bit width

A verilog vector has a single element which is of n-bit wide

Eg1: reg [2:0] mem; //1 element of 3-bits width

A verilog scalar has a single element which is of 1-bit wide

Eg1: reg mem;

13) parameter definition can be overridden at a) module instantiation or by b)

defparam.

localparam – if the parameters shouldn’t be overridden by anything. Typically,

the state encoding is defined as a localparam

14) $display – displays the string whenever called

15) $monitor – displays the string whenever any of the signals to be displayed
changes its value.

If there are multiple $monitor statements, the last one takes the preference
(overrides the previous ones)

$monitoron and $monitoroff are used to control $monitor statement (let’s say in a
particular time frame in the simulation).

$monitor is on by default.

16) $stop – used to suspend the simulation (let’s say at a time after which the designer
may want to debug the design)

17) $finish – used to terminate the simulation

18) `define is just a text replacement (`define S $stop)

19) $write is similar to $display except that it doesn’t have an in-built new line
character.
20) $display is invoked as many times as it is called. Each time it is called (or
invoked), the value of the variables at that instance are printed out.

21) $monitor is invoked once per time unit in which it is called. It can be present
more than one time per time unit. But, it is invoked only once per time unit and it
prints the value of the variables at the end of the time step.

22) $strobe is invoked as many times as it is called per time unit. Each time, it prints
the value of the variables at the end of the time step. It is to be understood that
there could be time units where none of the $display, $monitor, $strobe directives
are scheduled

23) Example

************************

reg [3:0] a;

initial begin

for(i=0; i<10; i=i+1) begin

a = i;

$abc(“i = %b”, i); //abc is monitor, display or strobe

// #1; //Optional delay

end

end

************************

With out optional delay

$display -> It is printed 10 times from 0 to 9

$monitor -> It is printed 1 time with i as 9 (value at the end of the time step)
$strobe -> It is printed 10 times, all the times with a value of 9.

With the optional delay of 1 time unit

$display -> It is printed 10 times from 0 to 9. Same for $monitor and $strobe
24) Sample code

Output:

25)
 Chapter 2: Gate level modeling

1) Basic gates/primitives – and, or, nand, nor, xor, xnor, buf, not, etc

2) Instance name is not compulsory while instantiating gates

3) If the gate needs more than 2 inputs, keep extending the port list

nand nand_3ip (OUT, IN1, IN2, IN3);

4) Truth tables of gate primitives (NOTE : No ‘z’ in the outputs)

5) buf instantiates a buffer (one input, one or more outputs)
not instantiates a not gate (one input, one or more outputs)

buf b1 (OUT, IN)

but b2 (OUT1, OUT2, IN)
not n1 (OUT1, IN1)

6) buf/not with additional controls (ctrl0 and ctrl1) are also available
bufif0, bufif1, notif0, notif1.

bufif0 (out, in,ctrl)

Note: If ctrl is not there (0, in case of *1 primitives and vice versa), output
is ‘z’.

7) Delays for gate primitives

Rise delay (RD) – Time taken for a transition from 0, x, z to 1

Fall delay (FD)- Time taken for a transition from 1, x, z to 0
Turn-off delay (TD) – Transition to ‘z’ from other values
 and #(1) a1 (out, i1, i2); //RD = FD = TD = 1
and #(1, 2) a1 (out, i1, i2); //RD = 1, FD = 2, TD = 1 (min of RD and FD)
and #(1, 2 , 3) a1 (out, i1, i2); //RD = 1, FD = 2, TD = 3
(Min : Typical : Max) delays (Min/Typical/Max delays can be specified
for each of the above 3 delays in the same way as mentioned above)

and #(1:2:3, 2:3:4 , 3:4:5) a1 (out, i1, i2);

8) wand and wor truth tables

9)
 Chapter 3: Data flow modeling

1) Continuous assignments

L.H.S -> Net (scalar or vector)

R.H.S -> Net/Reg/Function call
L.H.S is evaluated whenever any of the R.H.S operands change

2) Delays in continuous assignments

a) Regular assignment delay

assign #10 c = a & b;

Inertial delay: Any pulse of width < the regular assignment delay is not
propagated.

b) Implicit continuous assignment delay

wire #10 c = a & b;

c) Net declaration delay

wire #10 c;

3) a % b (modulo operation) takes the sign of the first operand, a.

4) Equality operators

a == b => Possible values – 0, 1, x. (Result ‘x’ if ‘x’ or ‘z’ in any of the

operands)
a != b => Possible values – 0, 1, x. (Result ‘x’ if ‘x’ or ‘z’ in any of the
operands)
a === b => Possible values – 0, 1. (Compares the operands including ‘x’ and ‘z’)
a !== b => Possible values – 0, 1. (Compares the operands including ‘x’ and ‘z’)

5) Reduction operators – and, or, nand, nor, xor, xnor. Can’t be not (will be bit-wise)

//x = 4’b1010
&x => 0
| x => 1 // 1 | 0 | 1 | 0
 Chapter 4: Behavioral modeling

1) 2 basic procedural blocks – initial and always

2) initial

a) Starts @ 0 time and executes only once through the simulation

b) All initial blocks are kicked off @ ‘0’ time.

3) always

a) Gets triggered whenever any variable in the sensitivity list changes

4) Procedural assignment

a) Any assignment in the always block is a procedural assignment

b) LHS of a procedural assignment is a reg, integer, real or a time variable or
a memory element (a bit select or part select of these is also allowed)
c) 2 types of procedural assignments – Blocking and Non-blocking

5) Blocking procedural assignments

a) Executed in the order they are specified in a sequential block (statement

blocks the execution of subsequent statements till it gets completed)
b) Represented by “=” operator
c) Ideal for combinational logic
d) Single step event (RHS evaluation and assignment in 1 step)

6) Non - blocking procedural assignments

a) Allow scheduling of statements without blocking execution of subsequent

statements.
b) Represented by “<=” operator
c) Ideal for sequential logic
d) Multiple step event (RHS evaluation and assignment in 2 steps)

7) Verilog stratified event queue (VSEQ)

The IEEE verilog specification/standard (1364-2005) talks of the way verilog

simulators need to schedule various events in each time step. The following is the
order of events that need to be scheduled in each time step.
 Step 1: Active events
a) Blocking assignments RHS evaluation and assignment (updation of the
LHS)
b) Non – blocking RHS evaluation
c) Continuous assignments – evaluation and assignments
d) $display events
e) Primitives

Step 2: Inactive events

a) #0 procedural assignments

Step 3:
a) Non – blocking assignment (evaluation done in Step 1)

Step 4:
a) $monitor events
b) $strobe events

8) Verilog Race condition

A verilog race condition occurs if two or more statements scheduled in the same
time step produce different end results by changing the order of execution of the
events as permitted by the Verilog standard

In this example, if the first always block is scheduled before the second one, y2 =
1 and y1 = 1 at the end of the simulation. If it is the other way round, y2 = 0 and
y1 = 0.

If in the above code, the blocking assignments are converted into non-blocking
assignments, it is not a race condition and y2 = 0 and y1 = 1 at the end of the
simulation. When reset is removed, and in the next clock cycle (time step), in the
active events queue, y1 is evaluated as 0 and y2 as 1. These values are stored in
some temporary variables. During step-3 of the event queue, the values are
assigned. Thus, the values get exchanged irrespective of the order in which the
two always blocks are scheduled
9) Sample Verilog codes and comments.

To implement a pipeline given below.

Value change @ ‘d’ should get reflected @ qn (n = 1 to 3) after n clock cycles.

Code 1:

Comments: Will not infer a pipeline. Will infer a single flop.

Simulation – fail, Synthesis - fail

Code 2:

Comments: Will work both w.r.t simulation and synthesis. But not a suggested
style (gets cumbersome with more assignments)
 Code 3:

Comments: Will not work. Verilog can schedule any always block before any
always block. So, will fail in Simulation. It will synthesize correctly.

If in the above codes, blocking assignments are replaced by non-blocking

assignments, all the 3 codes will simulate and synthesize correctly.

10) Coding guidelines

a) Use blocking to code combinational logic

b) Use non-blocking to code sequential logic
c) Never mix blocking and non-blocking assignments
d) When modeling latches, use non-blocking assignments
e) Don’t drive same reg from different always blocks
f) Use $monitor or $strobe for non-blocking assignments (variables assigned
by them) as $display in a time step will not be able to reflect the valaue as
it gets scheduled before a NB assignment.
g) Making multiple assignments to the same variable in the same always
block is discouraged (the last assignment wins!!)
h) Do not use #0 delays

11) Verilog – 2001 supports always @ (*), which is used to include all the variables
on the RHS in the always block into the sensitivity list

12) Timing and delays

Verilog simulator doesn’t move without any timing control. 3 types of timing
control in Verilog

a) Delay – based (regular, inter and zero delay)

#10 a = b + 1; //regular assignment delay

# (4:5:6) q = 0; // regular assignment delay
 y = #5 x + z; //Inter- assignment delay – Here (x+z) is calculated @ time 0
//and assigned @ time 5.
#5 y = x + z; //Regular- assignment delay – Here (x+z) is calculated @
time 5 and assigned @ time 5.

#0 a = b + 1; // 0- delay

b) Event – based (regular event, named event)

@ (posedge clk) // regular event

******************
//Named event

event abc; //Keyword event

always @ (posedge clk) begin

if (a)
-> abc; //Trigger the event

end

always @ (abc) begin // event defined above, used here

c = d;

end

******************

c) Level – sensitive timing control

wait(abc) #20 c = c + 1; //wait till the event abc happens

13) while loop (based on a logical expression), for loop, repeat loop ( a numerical
count or a signal. If a signal, its value is evaluated when the loop starts off),
forever loop (infinite loop. Use $finish, disable to stop the loop), if-else are
supported

14) Case statement is equivalent to an if-else-if logic. It compares 0, 1, x and z. If, in a

plain case, the expression and the item are of unequal width, the smaller of both is
bit filled with zeros to match the wider one. Case essentially does a (===) and not
a (==).
‘z’ is same as ‘?’ (or vice-versa) in case statements
 Casez statement treats all ‘z’ and ‘?” values in the both the case item and
expression as ‘x’s
Casex statement treats all ‘x’, ‘z’ and ‘?’ values in both the case item and
expression as ‘x’s.

A full case is a case statement for which it is not possible to find a binary string
that will not match any case item
A parallel case is a case statement for which it is possible to find one and only one
case item corresponding to each possible binary string.

15) Sequential blocks - grouped by begin…..end

Parallel blocks - grouped by fork……..join

These blocks can be named (fork: abc). They can be disabled by using disable

The following code is a Verilog race condition

*****************

fork

a = 1;
b = 0;
c = a + b;

join

*****************

16) Generate blocks (to instantiate a module number of times)

- Can have for loops, conditionals, case statements, etc. Instead of
logic, at each place, there will be a module instance

*****************
genvar i; //variable used inside a generate block

generate

for(i=0; i< (`INTCOL_DEPTH); i=i+1) begin: u_l_0

L l0 (.wren_in_n(we_n[i]),
.wsel_n(wsel_n),
.wren_out_n(we_gated_n[i]));

end

endgenerate

*****************
17)
 Chapter 5: Logic Synthesis

1) Logic synthesis is a two stage process

a) Logic optimization: Transform the high-level code into optimized gate level
representation. The code could be represented at the Gate-Level (verilog Gate-
level), but the synthesis tool can optimize even that with the gates available in its
library.
b) Technology mapping: Mapping the technology onto the optimized gate-level
netlist.

2) a) assign y = (a === 1’bx) ? 1’b1 : 1’b0; is not synthesizable (Comparison against

an unknown is not possible in H/W). It can be simulated.
b) assign y = (a == b) ? 1’bx : 1’b0; is synthesizable (Synthesis tool assigns a 1 or
0 if a = b). It can be simulated also.

3) The following code example where the output ‘f’ is assigned to the value of ‘c’
up-front is a good practice to avoid latch-inferences

4) The following code segment infers a gated latch (A level sensitive latch that
passes the input onto the output when the gate value is 1. It holds the value when
the latches’ gate input is ‘0’)
always @ (*) begin
if(a) b = c;
end

5) Case statements (without edge control like posedge or negedge in the sensitivity
lists of the always blocks) will infer a latch if all the cases are not specified. It’s a
good practice to have defaults

6) The Case statement

a) The first case alternative that matches is considered. All other matches are
ignored for the current pass.
b) Compares 0, 1, X, Z in both the expression and the alternative bit by bit. If
the widths (of expression and alternative) are different, the smaller
expression is padded to match the width of the larger expression.
c) Case essentially does a (===) and not a (==).

7) The Casex statement

 a) Treats all the X, Z and ? values in the case expression and case alternative
as don’t cares or wild cards, meaning that these elements in either the case
item or the expression will compare against anything.

8) The Casez statement

a) Treats all the Z and ? values in the case expression and case alternative as
don’t cares or wild cards, meaning that only ‘Z’ will compare against
anything. ‘X’ will compare only against an ‘X’.

9) The “full” case statement

a) A case statement is said to be full if it is not possible to find a binary string
for the case expression that wouldn’t map to any of the case items. For a
case statement to be non-full, it is obvious that the ‘default case’ item is
not present.
b) Normal verilog case statements can be made ‘full’ by adding a default
case.

10) The following code will cause a simulation-synthesis mismatch

Simulation will give ‘X’ when sel = 2’b11. Synthesis will optimize the ‘X’.
NOTE: to prevent simulation-synthesis mismatches, it is suggested that default
case item will not have X’s assigned to the outputs.

11) Synopsys has the full case directive “// synopsys full_case” which interprets a
full case statement. For simulation, it is nothing more than a comment. So, it is
ignored. It has the following impact on Synthesis. If the case statement is full,
there’s no impact of the directive. If the case statement is not full (not all cases
are covered), the outputs are assigned the value of X’s for all the uncovered case
items, thereby causing a simulation-synthesis mismatch.

12) The “parallel” case statement

 a) A parallel case statement is a case statement wherein it is possible to
match each possible binary string for the case expression to one and only
one case item. If it is possible to match a case expression to multiple case
items, it is not parallel.

13) The following code will result in a simulation-synthesis mismatch

This code infers priority logic when simulated, but will infer a non-priority
logic when synthesized (because of the parallel_case directive)

14) The parallel case directive will infer non-priority logic (typically) from the code.
If the case statement already has no overlapping case-items (parallel), the
directive doesn’t create any simulation-synthesis mismatch. If, on the other
hand, the case statement is not full, it causes a simulation-synthesis mismatch.

15) ‘For’ loop is allowed in synthesis, ‘repeat’ loop is not allowed.

16) If the sensitivity list contains an edge-sensitive specification, a latch will not be
inferred. It is inferred if the sensitivity list doesn’t contain any edge-sensitive
specification and if there exists at least one control path that doesn’t assign a
value to the left hand side variable (reg)
Chapter6: Functions and Tasks
1) Tasks

- Local to a module, have to be declared inside a module

- Used for code that need some delay control
- Can have inputs, outputs or inouts (any number of each of them)
- Cannot have wires (can have reg, time, integers, etc)
- Don’t have any always or initial blocks, but are called from them.

a) Definition

*********************
task abc;

input a;
input b;
output c;

#10 c = a & b;

endtask

*********************

b) Call to a task

*********************
module xyz;
reg a, b, c;

always @ (a or b) begin
abc(a,b,c); //no instance name
end

// Task definition comes here

// It is inside the module
// Can have the definition in a separate file also, just need to `include it

endmodule

*********************

c) Automatic (re-entrant) tasks

- Tasks are normally static.
- Same task called concurrently from 2 places => over write the
 task variables
- Automatic tasks cannot be referred using hierarchical referencing
as the simulator will not be able to understand to which copy of
the task is the user intending to probe.
- automatic keyword before the task name in task definition will
make it dynamic (separate copy of local variables per call)

task automatic abc;

------
------
------
endtask

2) Functions

- Local to a module, have to be declared inside a module

- Combinational code only (No non-blocking assignments)
- No delays, zero simulation time
- Exactly one output (no outputs in case of void functions)
- Only inputs (at least one input)
- Cannot have wires (can have reg, time, integers, etc)
- It is to be noted that to avoid latch inferences, all local variables in a
Function should be assigned some value or the other for every call.
- Don’t have any always or initial blocks, but are called from them

a) Definition

********************
function abc;

input a;

abc = a + 1;

endfunction

*********************

b) Call to a function

**********************
module xyz;

input x;
 output y;

reg y;

always @(x) begin

y = abc (x);

end

//Function definition should come here

endmodule

**********************

c) Automatic (recursive) functions

-Conceptually same as in an automatic task (separate copy per function

call)
- Automatic function items cannot be accessed by hierarchical refs.
- Concept is useful to write recursive functions.

d) Constant functions

- A function returning an integer, for example.

 Chapter7: Miscellaneous

1) Procedural continuous assignments (assign and deassign)

- Use assign and deassign

- To continuously drive the regs in a certain time period.
- Procedural continuous assignments override the effect of regular
procedural assignments
- If assign/deassign inside always block, these assignments
override the regular procedural assignments to the same reg from
other always blocks

2) Procedural continuous assignments (force and release)

- Controlled assignments to regs inside always blocks

- Used both for regs and wires
- Force overrides any other procedural (or procedural continuous)
assignments to the same variable, until it is released using release
3) defparam

- To redefine parameters (override them from the top module)

4) Parameters can also be overridden by passing the values from top while
instantiation

5) Conditional compilation
- `ifdef, `ifndef, `elsif, `else, `endif

6) Conditional execution
- $test$plusargs
 Looks if DISPLAY_VAR is set @ run time

- $value$plusargs

7) File I/O

- $fopen (open a file)

******************
integer a;

a = $fopen(“abc.h”);

******************

- $fclose (close the handle)

- $fdisplay, $fmonitor, $fwrite, $fstrobe (to write)
-
8) %t -> time, %m -> display current module hierarchy

9) $random returns a 32-bit signed number. $random(<seed>) is the way to

give the seed

10) $readmemb(“<filename>”, “memory_name”, “<start_addr>”); //binary

load into memory
$readmemh(“<filename>”, “memory_name”, “<start_addr>”); //hex load
into memory

11) Inertial delay

Delay in the continuous assignments (combinational). Inertial delay

models propagate only those input signals to the output which have
remained stable for a certain time equal to greater than the delay of the
model. In other words, outputs change till delay time units from the last
input change. If the inputs change in a time less than the delay, the outputs
 remain as they are. They only change (if the inputs change that way) if the
inputs remain unchanged till at least the delay of the model

Continuous assignments don’t queue up. They only keep track of the next
output change and the time it has to change. So, continuous assignments
properly model inertial delay

Examples

assign #12 {c0, sum} = (a + b + ci);

In this diagram, change in inputs at 15 has to trigger a change in output @

27. But, the inputs have not remained like that for at least 12 time units.
As the input change @ 21 has remained stable for at least 12 time units,
only that change is reflected at the output side.

In this way, inter-assignment delays cannot be used to model inertial

delays

Note: Delay in the RHS side of a continuous assignment is not suggested

to model inertial delays

12) Transport delay

Transport delay models propagate all the signals to the output after every
input signal change. These models essentially queue up the changes

Example
always @ (a or b or ci) begin

{c0, sum} <= #12 (a + b + ci); //Non blocking, delay on RHS

end

Why other assignments don’t work

Blocking, delay on the LHS

always @ (a or b or ci) begin

#12 {c0, sum} = (a + b + ci);

end

This will eat away all inputs changes if there are changes inside the delay
 Here, changes @ 24 get reflected @ the output @ 27. Changes @ 15, etc
are not reflected

Blocking delay on RHS

All input changes between the first change and the delay units from the first
change are lost. Output reflects the first change after the delay units and will
ignore all the changes in between.

Non – blocking delay on LHS

Same problem as in blocking LHS in procedural assignments

13) Code coverage

a) Line coverage – Have all the lines in the code been covered by the test
suite (suggested -> 100 p.c)
b) Toggle coverage – Have all the regs/wires changes their state from 0 to
1 and vice-versa (suggested -> 80 p.c)
c) FSM coverage – Have all the FSMs in the design changed their states
in all possible ways (suggested -> 100 p.c)
d) Combinational coverage – Have all the possible inputs driven to all the
possible combinational blocks (suggested -> 80 p.c)
Example -> a = b & c; //4 ways to get 0 or 1 on ‘a’ (all 4 covered??)

14) Tt
 Q and A

1) always @ (a)
begin
if(a)
$display(“Hello”);
end

If in the above code, ‘a’ goes to ‘X’ at some point in simulation, will the message
get printed?

No. ‘If’ treats ‘X’ and ‘Z’ as false. ‘repeat’ also treats ‘X’ and ‘Z’ as zeros.

2) Difference between c = a ? b : d; and if(d) c = b; else c = d;

The difference comes if the condition is an ‘X’. If treats ‘X’ as 0. Conditional

MUX treats it as ‘X’, but the result will be an ‘X’

3) What is a reverse case in Verilog?

If the case expression is a constant, it is called a reverse case. The care variables
are compared against that constant in priority, in that case

4) What would happen if a signal not included in the sensitivity list of an always block is
used on the R.H.S inside the always block?

The simulation will not toggle even if that signal changes (as it is not included in the
sensitivity list), but the synthesis tool will generate a net-list that will consider that. That
way there will be simulation-synthesis mismatches.

5) Which is updated first: A signal or a variable?

Signal

6) What is the difference between SPECPARAM and PARAMATER in verilog

SPECPARAM – can be used both in specify block and outside it and inside
regular modules.
PARAMETR – Only in modules, not in specify blocks.

7) What happens to the combinational logic whose output is not connected to any
port during synthesis?

Will be optimized out (removed) by the synthesis tool. Should be taken care of
during LINT phase
8) What value is sampled during simulation on an unconnected input port?

‘Z’ or high impedance.

9) What happens in simulation when 2 ports of unequal widths are connected?

The Most significant extra bits of the wider port are left floating (High Z is
driven).

10) What happens if multiple assignments are made to the same signal either through
blocking or through non-blocking assignments with out any conditional
qualifiers?

Although it is not suggested to write code that way, coding in such a way will
take the last assignment as final in simulation. It neglects the previous
assignments

11) How do you model asynchronous and synchronous resets in Verilog?

12) What happens w.r.t Synthesis if an integer is used in place of a reg variable?

Integer is a 32-bit signed quantity, where as a reg is an unsigned signal whose

width is explicitly mentioned. Depending on the assignments to the variables, the
remaining bits are optimized out by the synthesis tool. The integer will remain an
integer only of the values assigned to it are of 32-bits, otherwise some of the bits
will be lost.

13) When do you go for a case statement and when an IF-ELSE-IF kind of a coding?

If the control is based on one variable, then go for case. If the over all flow is
dependent on lot of conditions and variables, then go for IF-ELSE-IF although it
is not a strict rule, that’s the way it generally is.
14) How do you avoid a priority encoder in an IF-ELSE-IF structure

Using synopsys_parallel_case will infer a non-priority logic as long as there are

no overlapping case items.

15) In casex, both X and Z are treated as don’t cares and in casez, only Z is treated as
don’t care. What happens to X’s in casez?

In casex, both X and Z compare against anything. In casez, only Z compares

against anything and X compares only against X and not against other things.

16) What is the difference between assign-deassign and force-release?

force-release can be applied to regs, nets and variables, where as assign-deassign

can be applied only to nets

If both ‘force’ and ‘assign’ are used on the same variable, ‘force’ overwrites the
‘assign’ till it gets the corresponding ‘release’.

Once ‘release’d, the variable takes the previous value.

17) What happens if a non-constant is used to index an array?

It would get synthesized with all possible selects (non-constant indices possible)
taken as input of a multiplexer.

18) Is a non-constant fine in repetition operator? ( {a{b}})

No. The synthesis tool doesn’t understand how many times the internal variable
needs to be repeated.

19) What are the following operators

a) <<< -> Arithmetic shift left

b) >>> -> Arithmetic shift right
c) ** -> Power

20) Can an automatic task variable be referenced hierarchically?

No. Simulator will not have a clue to which instance of the task the user wants to
refer

21) What is the difference between fork-join in Verilog and SV

Verilog has only fork-join, SV jas fork-join, fork-join_all, fork-join_none.

22) How do we specify arguments on Verilog command line?

User defined command line options are preceded by a ‘+’

There are 2 system tasks used to probe through the command line

a) $test$plusarg

Returns a 1/0 depending on the availability of the command line argument.

$test$plusarg(“MYGPA”) or $test$plusarg(“MYSCHOOL”) will return a 1.

Something like $test$plusarg(“MYBRANCH”) will return a 0.

b) $value$plusarg

Once, the command line option is known using $test$plusarg , $value$plusarg

is used in the following way to read the value and store in a variable.

23) Draw the state diagram and the corresponding verilog code for a state machine
that detects a pair of 1’s or 0’s in a serial input. The circuit should essentially
output a 1 for one cycle, whenever the input is 1 or 0 for 2 successive cycles.
Answer for both Mealy and Moore state machines

MOORE FSM

Verilog code

---------------------------------
module fsm( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state;

reg outp;

always @( posedge clk, posedge rst )

begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end

2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
end

2'b10:
begin
if( inp ) state <= 2'b01;
else state <= 2'b11;
end

2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end

always @(posedge clk, posedge rst)

begin
if( rst )
 outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;

end

endmodule

--------------------------------

MEALY FSM

Verilog Code

module mealy( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state;

reg outp;

always @( posedge clk, posedge rst ) begin

if( rst ) begin
state <= 2'b00;
outp <= 0;
end
else begin
case( state )
2'b00: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
 end
else begin
state <= 2'b10;
outp <= 0;
end
end

2'b01: begin
if( inp ) begin
state <= 2'b00;
outp <= 1;
end
else begin
state <= 2'b10;
outp <= 0;
end

end

2'b10: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b00;
outp <= 1;
end

end

default: begin
state <= 2'b00;
outp <= 0;
end
endcase
end
end

endmodule

24) Difference between Behavioral and data flow modeling?

25) How many levels can be nested using `include?

16
26) What is the functionality of &&&?
27) How do we get all the data printed on the standard output into a file?

$log(“filename”);

28) Difference between parameter and `define?

29) What is the difference between a posedge and negedge?

Negedge => 1 to X, Z or 0 or X,Z to 0.

Posedge => 0 to 1, X, Z or X, Z to 1

30) What is the difference between $finish(0), $finish(1) and $finish(2)?

It has got to do with the messages printed at the very end of the simulation (when
finish kills the simulation)

0 -> Prints nothing

1-> Prints the Simulation time and location.
2-> Prints the Simulation time and location and memory status/utilization

31) Difference between $time, $stime and $realtime?

Thei$time systemofunctionereturns aniinteger thatoisqa 64-bitrtime,escaled toithe

timescaleounitjofqthe modulerthateinvoked it.

Thei$stime systemofunctionereturns aniunsigned integerothatqis ar32-bitetime,

 scaledito theotimescalejunitqof thermoduleethat invokediit. Ifothe
actual5simulation time5does notyfituin 32obits,ethe lowzorderx32 bits of the
current simulation time are returned.

Thei$realtime systemofunctionereturns aireal numberotimeqthat, liker$time,eis

scaledito theotimejunitqof thermoduleethat invokediit.

32) What does a function synthesize to?

Combinational logic

33) You have 2 clocks of same frequency, but with different phase. How do you find
out which clock is leading over the other?

Use a single D-FLOP. Feed one of the clocks (CLK1) to the D-Input and the other
(CLK2) to the clock input. If the output is high, CLK1 is leading else, CLK2 is
leading.

34) If your verilog function needs to return 2 values to the caller, what will you do?

Concatenate the 2 results and separate it out at the caller’s end.

35) How many times will the following loop run?

reg [3:0] k;
for(k=0; k<=15; k=k+1)
---------

Infinite times

36) Is it possible to disable a function using named blocks and ‘disable’ construct?

No. Not possible

37)