DATASHEET

CHARTERED FOUNDRY
PROCESS DESIGN KITS

The Virtuoso® custom design platform provides you with both tools and silicon-
accurate design methodologies. To maximize the advantages of the platform,
quality process design kits (PDK) are needed. Cadence and Chartered
Semiconductor Manufacturing have the solution — pre-defined Chartered Foundry
Process Design Kits (PDKs). Chartered Foundry PDKs are developed and tested at
Cadence by highly-skilled engineers — experienced designers familiar with the
Cadence tools used in a schematic- or netlist-driven design solution.

CHARTERED FOUNDRY SIMULATION • Chartered Foundry PDK Pcells are

created using high-level, relative
PDK DEVICES • Virtuoso Spectre Circuit Simulator and
®

Virtuoso Spectre RF Simulation Option object design (ROD) SKILL constructs

• RF/MS PDK list
• Virtuoso AMS Designer – Allow for complex Pcell functionality
– MIM caps
• Virtuoso UltraSim Full-chip Simulator • Auto-abutment for MOS transistors
– RF MOS devices (see Figures 3 and 4)
– Inductors – Specifies how the underlying
PARAMETERIZED CELLS
– Varactors • Parameterized cells (Pcells) are geometry of an instance of a
device generators Pcell changes when abuted
– NMOS transistors
with another Pcell
– PMOS transistors • The PDK includes Pcells for CMOS
single- and multigate transistors, – Results in two instances that are
– N+ diffused resistors merged to be both DRC and LVS
resistors, and capacitors
– P+ diffused resistors correct
– N-well resistor Chartered
Design flow

– Low value P+ polyresistor Spectre Virtuoso Schematic Editor

PDK models Virtuoso Spectre Circuit Simulator
– High value P+ polyresistor Virtuoso Spectre RF Simulation Option
Symbol library
– MOS capacitor
Analog design

Parameterized cells
SCHEMATIC SYMBOLS (Pcells)
Virtuoso Layout Editor
Virtuoso XL Layout Editor
• Provide a standard convention Tech files
for transistor-level simulation
Custom
(see Figure 2) physical design
Physical verification
• Drive the custom physical design process files
Diva
• Pass schematic design information Assura

seamlessly through to the physical Physical verification

design tools
Figure 1: Custom IC design flow
Process Design
Kit (PDK)
VIRTUOSO XL
Schematic driven LAYOUT EDITOR
Device parameters Virtuoso Schematic • The heart of the schematic-driven
Libraries, cells, and connectivity Editor
and views solution (see Figure 5)
• Includes basic connectivity of
connection layers, wells, substrate,
Cell physical design
and symbolic contacts
Device/cell
Advanced Advanced placement • The M factor will be used for device
Tech files, Pcells,
and symbol layout custom and route instance multiplier
connectivity editor router
Virtuoso XL – No conflict with the parameter used
Layout Editor
in cell operation

Cell physical verification Cell – Names are displayed on layout views

interactive to aid in schematic-layout instance
Interactive DRC/LVS physical
Verification rules: correlation
verification
DRC, LVS, and LPE
Diva – Flight lines are available in
Virtuoso XL Layout Editor to aid
Figure 2: Schematic-driven layout in layout

SUPPORTED CADENCE
TECHNOLOGY FILE PRODUCTS (IC/ICOA
• Users can modify the display.drf file 5.0 AND 5.1)
used onsite to achieve any desired
display • Virtuoso AMS Designer
• Virtuoso UltraSim Full-chip Simulator
ASSURA/DIVA PHYSICAL • Virtuoso Analog Design Environment
VERIFICATION DECKS • Virtuoso Spectre Circuit Simulator and
Figure 3: Before abutment
• Foundry technology-specific Spectre RF Simulation Option
Assura™/Diva® physical LVS developed • Virtuoso XL Layout Editor
and supported by Cadence
• Virtuoso Schematic Editor
• Assura/Diva DRC decks can
• Assura/Diva DRC and Assura/Diva LVS
be downloaded from
Verifier
www.cadence.com/partners/Foundry_
program/chartered.aspx
WHERE TO USE THE
RF/MS PDKS (CMOS)
Figure 4: After abutment • Custom RF
• Custom mixed-signal
• Custom analog or digital designs
• Custom cell design
• Standard digital cell design

FOR MORE INFORMATION

Email
chartered_Foundry_support@cadence.
com or log on to www.cadence.com

© 2004 Cadence Design Systems, Inc. All rights reserved.

Cadence, Diva, Virtuoso, Spectre, and the Cadence logo are
registered trademarks, and Assura is a trademark of Cadence
Design Systems, Inc. All others are properties of their respective
Figure 5: Virtuoso XL Layout Editor environment holders.
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