Raajdhani Engineering College: Department of Electronics & Communication Engineering Vlsi and Embedded Systems Lab
Raajdhani Engineering College: Department of Electronics & Communication Engineering Vlsi and Embedded Systems Lab
1. Design of schematic and simple layout for CMOS Inverter & perform parasitic
extraction and simulation.
2. Design of schematic and simple layout for CMOS NAND gate & perform parasitic
extraction and simulation.
3. Design of schematic and simple layout for CMOS NOR gate & perform parasitic
extraction and simulation.
5. Modeling and transient analysis of 2-inputs NAND & NOR gates using p-SPICE.
6. Design & implementation of 16-bit Arithmetic & Logic unit using VHDL.
1. Study of ARM7 & ARM9 Bit Processor Architecture and Pin Diagram.
Aim of the Experiment : To Design of schematic and simple layout for CMOS Inverter &
perform parasitic extraction and simulation.
THEORY: CMOS circuits use nFET & pFET transistors that are arranged as complementary
pairs . A Complementary pair consist of an nFET & pFET that have the gate ‘G’ electrodes
connected together to form a single terminal .The common gate signal control both the
transistors .However , since the transistors have opposite characteristics their pair give
useful characteristics that one of the transistor is on while the other is off.
pFET=ON pFET=OFF
nFET=OFF nFET=ON
Circuit Diagram:
Procedure:
1. Switch on the computer.
2. Open Microwind DSCH3
3. Create New File
4. Design The CMOS Circuit with the help of Tools
5. Simulate the Designed Circuit and observe the output.
6. Again Create New File and design the layout diagram.
7. Simulate and observe the graph obtained.
Observation table
OUTPUT: