LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

1. Lab #01: Introduction to Basic Logic Gate ICs on

Digital Logic Trainer and Proteus Simulation

Objective

Part 1
To know about the basic logic gates, their truth tables, input-output characteristics and
analyzing their functionality. Introduction to logic gate ICs, Integrated Circuits pin
configurations and their use.

Part 2
Learn to use Proteus Software for Simulation of Digital Logic Circuits.

Pre-Lab:

Background Theory:
The Digital Logic Circuits can be represented in the form of (1) Boolean Functions, (2)
Truth Tables, and (3) Logic Diagram. Digital Logic Circuits may be practically
implemented by using electronic gates. The following points are important to understand.

 Electronic gates are available in the form of Integrated Circuits (ICs) and they require
a power.
 Supply Gate INPUTS are driven by voltages having two nominal values, e.g. 0V and
5, 12V representing logic 0 and logic 1 respectively.
 The OUTPUT of a gate provides two nominal values of voltage only, e.g. 0V and 5,
12V representing logic 0 and logic 1 respectively. In general, there is only one output
to a logic gate except in some special cases.
 Truth tables are used to help show the function of a logic gate in terms of input values
combination with the desired output.
 Logic Diagram is used to represent the Digital Logic Circuit in the form of symbols
connected with each other.
 Digital Logic Circuits can be simulated in the virtual environment called simulation
software
The basic operations are described below with the aid of Boolean function, logic symbol, and
truth table.

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

AND gate:

Figure 1.1: AND gate

Table 1.1: Truth Table of 2 input AND gate

𝑨 𝑩 𝑭 = 𝑨.𝑩
0 0 0
0 1 0
1 0 0
1 1 1

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are
high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is
sometimes omitted i.e. AB.

OR Gate:

Figure 1.2: OR gate

Table 1.2: Truth Table of 2 input OR gate

𝑨 𝑩 𝑭=𝑨+𝑩
0 0 0
0 1 1
1 0 1
1 1 1

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs
are high. A plus (+) is used to show the OR operation.

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

NOT gate

Figure 1.3: NOT gate

Table 1.3: Truth Table of NOT gate

𝑨 𝑭=𝑨
0 1
1 0

The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter.

NAND gate

Figure 1.4: NAND gate

Table 1.4: Truth Table of 2 input NAND gate

𝑨 𝑩 𝑭 = 𝑨.𝑩
0 0 1
0 1 1
1 0 1
1 1 0

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The output
of NAND gate is high if any of the inputs are low. The symbol is an AND gate with a small
circle on the output. The small circle represents inversion.

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

NOR gate

Figure 1.5: NOR gate

Table 1.5: Truth Table of 2 input NOR gate

𝑨 𝑩 𝑭=𝑨+𝑩
0 0 1
0 1 0
1 0 0
1 1 0

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The output of
NOR gate is low if any of the inputs are high. The symbol is an OR gate with a small circle
on the output. The small circle represents inversion.

XOR gate

XOR

Figure 1.6: XOR gate

Table 1.6: Truth Table of 2 input XOR gate

𝑨 𝑩 𝑭 = 𝑨⊕𝑩
0 0 0
0 1 1
1 0 1
1 1 0

The 'Exclusive-OR' gate is a circuit which will give a high output if odd number of inputs
are high. An encircled plus sign “ ” is used to show the EOR operation.

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

XNOR gate

XNOR

Figure 1.7: XNOR gate

Table 1.7: Truth Table of 2 input XNOR gate

𝑨 𝑩 𝑭 = 𝑨⊕𝑩
0 0 1
0 1 0
1 0 0
1 1 1

The 'Exclusive-NOR' gate circuit does the opposite to the XOR gate. It will give a high
output if even number of inputs are high. The symbol is an XOR gate with a small circle on
the output. The small circle represents inversion.

Digital systems are said to be constructed by using logic gates. These gates are AND, OR,
NOT, NAND, NOR, XOR and XNOR. Logic gate ICs are available in different packages and
technologies. Two main classifications are as below:

1. 74 Series TTL Logic ICs

2. 4000 Series CMOS Logic ICs

74 series is TTL (Transistor-Transistor Logic) based integrated circuits family. Power rating
for 74 series is 5 to 5.5Volts. This circuitry has fast speed but requires more power than later
families. The Pin configuration of basic gates 2-input ICs for 74 Series is given in Figure 1.8:

Figure 1.8: TTL ICs’ pin configuration

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

Figure 1.8 shows the 4000 series is CMOS (complementary metal oxide semiconductors)
based integrated circuits. Power ratings are 3V to 15 Volts. CMOS circuitry consumes low
power, but it is not fast as compared to TTL.

Figure 1.9: Different CMOS ICs’ pin configuration

Quad 2-input gates

The ICs available in Lab to perform the Tasks are listed below:

In-Lab:

Part 1: Basic Logic Gate Integrated Circuits (ICs)

Equipment Required

 KL-31001 Digital Logic Lab

 Logic gates ICs
o 4001 quad 2-input NOR
o 4011 quad 2-input NAND
o 4070 quad 2-input XOR
o 4071 quad 2-input OR
o 4077 quad 2-input XNOR
o 4081 quad 2-input AND
o 4069 Six Inverting Buffer NOT

Procedure

1. Place the IC on the breadboard as shown in the Figure 1.10;

2. Using the power supply available at KL-31001 Digital Logic Lab trainer, connect
pin7 (Ground) and pin14 (Vcc) to power up IC.

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

o
Figure 1.10: IC placement on the breadboard
3. Select number of possible combinations of inputs using the slide switches SW0-SW3
(as shown in Tables 1.8 & 1.9) and note down the output with the help of LED for all
gate ICs. (You can use LD0-LD14 located on KL-31001 Digital Logic Lab)
(Note: Please make sure the Trainer board is off during the setup of circuit)

In-lab Task 1:
Verify all gates using their ICs on KL-31001 Digital Logic Lab trainer

Table 1.8: Observation Table for different gates

INPUTS OUTPUTS

𝑨 𝑩 𝑨𝑵𝑫 𝑶𝑹 𝑿𝑶𝑹 𝑵𝑨𝑵𝑫 𝑵𝑶𝑹 𝑿𝑵𝑶𝑹

0 0

0 1

1 0

1 1

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

Table 1.9: Observation Table for NOT gate

INPUT OUTPUT

𝑨 𝑩
0

Part 2 - Proteus (Simulation Software)

Proteus has many features to generate both analog and digital results over a virtual
environment. However, this lab will focus on tools that will be used in digital schematic
designs and verification of basic logic gates.

Procedure

The Proteus software for simulation is installed in Digital Design Lab. Please follow the
details below to figure out the usage of Proteus tools and process of simulation.

Figure 1.11: Interface of Proteus software window

Parts Browsing:

Proteus has many models of electronic equipment such as logic gates, many kinds of switches
and basic electronic devices. The equipment can be placed by clicking on it and then a new
window will pop-up as shown in Figure 1.12.

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

Finding Steps:

1. Type information of device such as “OR gate” in “Keywords’ box.

2. If some specific category is known, the device can narrow on focusing by selecting
catalogue in the “Category” box.
3. After the information is entered, the list of related devices will appear in the “Results”
window, so that needed device can be chosen and then click “OK” button to confirm
selection in Figure 1.13.

Figure 1.12: Pick Devices window in Proteus

Figure 1.13: Pick selected Devices window in Proteus

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

Power supply and input signal Generator

All the electrical circuits require power supplies. The power supplies for logic circuits are
represented in digital system design on Proteus because the schematic may be too
complicated to understand for simulation section. Therefore, power supplies will be needed
as input power for a system. Moreover, all the input generators, such as AC generator, DC
and pulse, are contained in this category and it will be shown when clicked. In addition,
“Ground” will not be available in this group. Because it is not an input signal it is just a
terminal junction. Therefore, it will be grouped in the terminal category as shown in Figures
1.14 & 1.15.

Figure 1.14: Power supplies window in Proteus Figure 1.15: Terminals window in Proteus

Logic State:

In addition, there is another input that usually used in the digital circuit, but it does not exist
in the real world as an equipment it is called as “LOGIC STATE”. It can be found in the
picking part section (type logic state and pick it as shown in Figure 1.16).

Figure 1.16: Logic State in Proteus

Placing Equipment:

Selecting all devices needed to be placed on the circuit window (Gray window) and make the
required connections. It can be done by following steps:
1. Click on and select the first device that will be placed.

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

2. Place mouse wherever the device is preferred to place and then click the left button of
the mouse. The device will be placed, if it is needed to be moved, click the right
button of the mouse on the device symbol to select the mouse. Then hold this device
with the left mouse button and move it to any desired place (Figure 1.17).

Figure 1.17: Placing the devices in Proteus

To make the connections between the devices, click on the source pin of a device and then
move the cursor to destination pin of a device. In this step, the pink line will appear, and it
will be a wire of the circuit after clicking the mouse on the destination pin of the circuit (as
shown in Figure 1.18).

Digi
Figure 1.18: Making connection between devices to make a circuit

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

After wiring all devices and connect all inputs according to the circuit, the simulation is ready
to run by clicking on Play button and stop button is used to stop the simulation.
3. Logic probe or LED can be used to observe the output state.

NOTE: The digital result on Proteus can be seen also in Small Square Box at the pin of the
equipment & state can be shown in four colors. (Red= Logic 1, Blue = Logic 0, Gray=
Unreadable and Yellow= Logic Congestion)

In-Lab Task 2:
Verify all the basic logic gates using the Proteus simulation tool and note down the values in
the Tables 1.10 & 1.11 with the corresponding logic symbol and Boolean function. Then
show the simulated logic circuit diagrams to your Lab Instructor.

Table 1.10: Observation Table for different gates

INPUTS OUTPUTS

𝑨 𝑩 𝑨𝑵𝑫 𝑶𝑹 𝑿𝑶𝑹 𝑵𝑨𝑵𝑫 𝑵𝑶𝑹 𝑿𝑵𝑶𝑹

0 0

0 1

1 0

1 1

Table 1.11: Observation Table for NOT gate

INPUT OUTPUT

𝑨 𝑩
0

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

Post-Lab Tasks:
1. Make a list of logic gate ICs of TTL family and CMOS family along with the ICs
names. (Note: at least each family should contain 15 ICs)

7400 Series 4000 Series

10

11

12

13

14

15

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

2. What is Fan-In and Fan-Out?

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LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

Critical Analysis/Conclusion

Lab Assessment

Pre-Lab /1

In-Lab /5

Data
Analysis
/4 /10
Data
Post-Lab /4 /4
Presentation

Writing
/4
Style

Instructor Signature and Comments

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LAB #02: Boolean Function Implementation using Universal Gates

2. Lab #02: Boolean Function Implementation using

Universal Gates

Objectives
 This lab is designed to simulate and implement any logic function using universals
gates (NAND/NOR).
 To build the understanding of how to construct any combinational logic function
using NAND or NOR gates only.

Pre-Lab:

Background theory:

Digital circuits are more frequently constructed with universal gates. NAND and NOR gate
are called universal gates. Any Boolean logic function can be implemented using NAND only
or NOR only gates. NAND and NOR gates are easier to fabricate with electronic components
than basic gates. Because of the prominence of universal gates in the design of digital
circuits, rules and procedures have been developed for conversion from Boolean function
given in terms of AND, OR, and NOT into its equivalent NAND and NOR logic diagram.

Read and understand the universal gates. List the truth tables of AND, OR, NOT, NAND,
NOR and XOR gates. Identify the NAND and NOR ICs and their specification for CMOS
and TTL families.

In lab:
This lab has two parts. In the first part, simulation and implementation of any logic
expression by using only NAND gates are done. In the second part, the same procedure is
done by using NOR gates only.

Part 1 - Implementing any logic expression by using only NAND gates

If we can show that the logical operations AND, OR, and NOT can be implemented with
NAND gates, then it can be safely assumed that any Boolean function can be implemented
with NAND gates.

Procedure
 Simulate NOT, AND, OR, XOR and XNOR gates in Proteus software, by using only
NAND gates. Verify their truth tables.
 Insert the IC on the trainer’s breadboard.
 Use any one or more of the NAND gates of the IC for this experiment.

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LAB #02: Boolean Function Implementation using Universal Gates

 One or more Logic Switches of the trainer (S1 to S9) can be used for input to the
NAND gate.
 For output indication, connect the output pin of the circuit to any one of the LEDs of
the trainer (L0 to L15).

In-Lab Tasks-Part-1

In-Lab Task 1.1: Verification of NOT function

 Connect the circuit as shown in Figure 2.1.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of a NOT gate. Record your observations in the Table2.1 below.

Figure 2.1: NOT gate using NAND gate

Table 2.1: Observation Table for NOT gate

INPUT OUTPUT

𝑨 𝑭

In-Lab Task 1.2: Verification of AND function

 Connect the circuit as shown in Figure 2.2.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observations in Table 2.2 below.

Figure 2.2: AND gate using NAND gates

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LAB #02: Boolean Function Implementation using Universal Gates

Table 2.2: Observation Table for AND gate

INPUTS OUTPUT

𝑨 𝑩 𝑭

0 0

0 1

1 0

1 1

In-Lab Task 1.3: Verification of OR function

 Connect the circuit as shown in Figure 2.3.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an OR gate. Record your observations in Table 2.3 below.

Figure 2.3: OR gate using NAND gates

Table 2.3: Observation Table for OR gate

INPUTS OUTPUT

𝑨 𝑩 𝑭

0 0

0 1

1 0

1 1

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LAB #02: Boolean Function Implementation using Universal Gates

In-Lab Task 1.4: Verification of XOR function

 Connect the circuit as shown in Figure 2.4.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an XOR gate. Record your observations in Table 2.4 below.

Figure 2.4: XOR gate using NAND gates

Table 2.4: Observation Table for XOR gate

INPUTS OUTPUT

𝑨 𝑩 𝑭

0 0

0 1

1 0

1 1

In-Lab Task 1.5: Verification of XNOR function

 Connect the circuit as shown in Figure 2.5.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an XNOR gate. Record your observations in Table 2.5 below.

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LAB #02: Boolean Function Implementation using Universal Gates

Figure 2.5: XNOR gate using NAND gates

Table 2.5: Observation Table for XNOR gate

INPUTS OUTPUT

𝑨 𝑩 𝑭

0 0

0 1

1 0

1 1

In-Lab Task 1.6: Implementation of any Boolean function (2-variables)

using only NAND gates

𝐹 (𝐴, 𝐵) = ______________________________________

(Note: Boolean function will be specified by Lab Instructor)

Table 2.6: Observation Table for the given Boolean function

Inputs Outputs
Calculated Observed
𝑨 𝑩
𝑭𝑪 𝑭𝑶
0 0

0 1

1 0

1 1

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LAB #02: Boolean Function Implementation using Universal Gates

Part 2 - Implementing any logic expression by using only NOR gates

If we can show that the logical operations AND, OR, and NOT can be implemented with
NOR gates, then it can be safely assumed that any Boolean function can be implemented with
NOR gates.

Procedure

 Simulate NOT, AND and OR gates in Proteus software, by using only NOR gates.
Verify their truth tables.
 Insert the IC on the trainer’s breadboard.
 Use any one or more of the NOR gates of the IC for this experiment.
 One or more Logic Switches of the trainer (S1 to S9) can be used for input to the
NOR gate.
 For output indication, connect the output pin of the circuit to any one of the LEDs of
the trainer (L0 to L15).

In-Lab Tasks-Part-2

In-Lab Task 2.1: Verification of NOT function

 Connect the circuit as shown in Figure 2.6.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an NOT gate. Record your observations in Table 2.7 below.

Figure 2.6: NOT gate using NOR gate

Table 2.7: Observation Table for NOT gate

INPUT OUTPUT

𝑨 𝑭

In-Lab Task 2.2: Verification of AND function

 Connect the circuit as shown in Figure 2.7.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.

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LAB #02: Boolean Function Implementation using Universal Gates

 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an AND gate. Record your observations in Table 2.8 below.

Figure 2.7: AND gate using NOR gates

Table 2.8: Observation Table for AND gate

INPUTS OUTPUT

𝑨 𝑩 𝑭

0 0

0 1

1 0

1 1

In-Lab Task 2.3: Verification of OR function

 Connect the circuit as shown in Figure 2.8.

 Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
 By setting the switches to 1 and 0, verify that the output (F) of the circuit conforms to
that of an OR gate. Record your observations in Table 2.9 below.

Figure 2.8: OR gate using NOR gates

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LAB #02: Boolean Function Implementation using Universal Gates

Table 2.9: Observation Table for OR gate

INPUTS OUTPUT

𝑨 𝑩 𝑭

0 0

0 1

1 0

1 1

Post-Lab:
Task 01: Simulate NAND, XOR and XNOR gates in Proteus software, by using only NOR
gates. Verify their truth tables.

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LAB #02: Boolean Function Implementation using Universal Gates

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LAB #02: Boolean Function Implementation using Universal Gates

Critical Analysis/Conclusion

Lab Assessment

Pre-Lab /1

In-Lab /5

Data
Analysis
/4 /10
Data
Post-Lab /4 /4
Presentation

Writing
/4
Style

Instructor Signature and Comments

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LAB #03: Introduction to Verilog and Simulation using XILINX ISE

3. LAB #03: Introduction to Verilog and Simulation

using XILINX ISE

Objective

Part 1
In this lab, Verilog (Hardware Description Language) is introduced with Xilinx ISE. Verilog
is used to model d i g i t a l systems. It is most commonly used in the design and
verification of digital circuits.

Part 2
Xilinx ISE is a verification and simulation tool for Verilog, VHDL, System Verilog, and
mixed- language designs.

Pre-Lab:

Background Theory:
Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers
many useful features:

 Verilog HDL is a general-purpose hardware description language that is

easy to learn and easy to use.
 It is similar in syntax to the C programming language. Designers with
C programming experience will find it easy to learn Verilog HDL.
 Verilog HDL allows different levels of abstraction to be mixed in the same
model. Thus, a designer can define a hardware model in terms of switches,
gates/structural, RTL, dataflow or behavioral code.
 Also, a designer needs to learn only one language for stimulus and
hierarchical design.
 Most popular logic synthesis tools support Verilog HDL. This makes it
the language of choice for designers.
 All fabrication vendors provide Verilog HDL libraries for postlogic
synthesis simulation.
 Thus, designing a chip in Verilog HDL allows the widest choice of vendors.
 The Programming Language Interface (PLI) is a powerful feature that
allows the user to write custom C code to interact with the internal data
structures of Verilog. Designers can customize a Verilog HDL simulator to
their needs with the PLI.

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LAB #03: Introduction to Verilog and Simulation using XILINX ISE

3.1 Level of Abstraction provided by Verilog

3.1.1 Switch level

This is the lowest level of abstraction provided by Verilog. A module can be implemented
in terms of switches, storage nodes, and the interconnections between them. Design at this
level requires knowledge of switch-level implementation details.

3.1.2 Gate (Structural) level

The module is implemented in terms of logic gates and interconnections between these
gates. Design at this level is similar to describing a design in terms of a gate-level/structure-
level logic diagram.

3.1.3 Dataflow level

At this level, the module is designed by specifying the data flow. The designer is aware of
how data flows between hardware registers and how the data is processed in the design.

3.1.4 Behavioral or algorithmic level

This is the highest level of abstraction provided by Verilog HDL. A module can be
implemented in terms of the desired design algorithm without concern for the hardware
implementation details. Designing at this level is very similar to C programming.

3.2 Syntax

3.2.1 Comments

Verilog comments are the same as in C++. Use // for a single line comment or /* … */ for
a multiline comment.

3.2.2 Punctuation

White spaces are ignored in Verilog. A semicolon is used to indicate the end of a command
line and commas are typically used to separate elements in a list. Like C++, Verilog is case
sensitive.

3.2.3 Identifiers

An identifier is usually a variable. You can use any letter, digit, the underscore, or
$. Identifiers may not begin with a digit and may not be the same as a Verilog keyword. As
in C++ variable names should be chosen to assist in documentation.

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3.2.4 Signal values

Signals in Verilog have one of four values. These are 0 (logic 0), 1 (logic 1), ?, X, or x (
don’t care or unknown), and Z or z for high impedance tri-state.

3.2.5 Constants

The generic declaration for a constant in Verilog is

[size][ 'radix] constant_value

In this declaration size indicates the number of bits and 'radix gives the number base (d =
decimal, b = binary, o = octal, h = hex). The default radix is decimal.

Examples:
16 //The number 16 base 10

4'b1010 //The binary number 1010

8'bx //An 8-bit binary number of unknown value

12'habc //The hex number abc = 1010 1011 1100 in binary

8'b10 //The binary number 0000 0010

3.3 Structure

3.3.1 Module

A module in Verilog is used to define a circuit or a subcircuit. The module is the

fundamental circuit building block in Verilog. Modules have the following structure: Note
that the module declaration ends with a semicolon but the keyword endmodule does not.

module module_name (port_name list);

[declarations]
[assign statements]
[initial block]
[always block]
[gate instantiations]
[other module instantiations]
endmodule

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LAB #03: Introduction to Verilog and Simulation using XILINX ISE

3.3.2 Ports

Ports in Verilog can be of type input, output¸ or inout. The module ports are given in
the port name list and are declared in the beginning of the module. Here is a sample
module with input and output ports.
module MyModule(yOut, aIn);
output yOut;
input aIn;

…
endmodule

The port names input and output default to type wire. Either can be a vector and the
output variables can be of re-declared to type reg. The output and input variables in a module
are typical names for the output and input pins on the implementation chip.

3.3.3 Signals

A signal is represented by either a net type or a variable type in Verilog. The net type
represents a circuit node, and these can be of several types. The two net types most often
used are wire and tri. Type nets do not have to be declared in Verilog since Verilog
assumes that all signals are nets unless they are declared otherwise. Variables are either of
type reg or integer. Integers are always 32-bits where the reg type of variables may be of
any length. Typically, we use integers as loop counters and reg variables for all other
variables. The generic form for representing a signal in Verilog is:

type [range] signal_name

The net types are typically used for input signals and for intermediate signals within
combinational logic. Variables are used for sequential circuits or for outputs which are
assigned a value within a sequential always block.

Examples:

wire w; //w is a single net of type wire

wire [2:0] wVect; //Declares wVect[2], wVect[1], wVect[0]
tri [7:0] bus; //An 8-bit tri state bus
integer i; //i is a 32-bit integer
reg r; //r is a 1-bit register
reg [7:0] buf; //buf is an 8-bit register
reg [3:0] r1, r2; //r1 and r2 are both 4-bit registers

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3.3.4 Most often used Operators

Symbol Comments
~ Ones complement unary operator
& AND
| OR
Bitwise

^ XOR
~& NAND
~| NOR
~^ XNOR
! Not unary operator also called logical negation
Logical

&& Logical AND

|| Logical OR
+ Add
Arithmetic

- Subtract
* Multiply
/ Divide
% Mod operator
> Greater than
Relational

< Less than

>= Greater than or equals
<= Less than or equals
>> Shift right
<< Shift left
Misc

?: (cond)?(statements if true):(statements if false)

{,} Concatenation
{m{}} Repetition where m is repetition number

In-Lab:

3.4 Xilinx ISE 13.2

Start ISE from the Start menu by selecting:
Start → All Programs → Xilinx ISE Design Suite 13.2 → ISE Design Tool →Project
Navigator or by double-clicking on Xilinx ISE Design Suite 13.2 icon

3.4.1 Creating a Project

 File → New Project (Figure 3.1)

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 Select the location for the project (Should be your dld_lab folder)
 Enter the name of the project
 Then click next

Figure 3.1: XILINX ISE 13.2 Interface

Figure 3.2: Create New project window

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Figure 3.3: Project Settings Window

 Set the project settings:

o Family to Spartan3E
o Device to XC3S500E
o Package to FG320
o Speed to -4
 Then click to Next
 Project Summary
 Then click finish

3.4.2 Adding a file to the project

Right click on Design Pane and select a New Source or Add Source (If file already exists).

 For New Source:

o Select Source Type (e.g. Verilog Module) and enters the file name
o Then click Next
o Give Port Names and direction of the module
o Then click Next
o Then click Finish

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LAB #03: Introduction to Verilog and Simulation using XILINX ISE

Figure 3.4: New Source Wizard window

Figure 3.5: Define Module window

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LAB #03: Introduction to Verilog and Simulation using XILINX ISE

 For Add Source:

o Right click on Design Pane and select an Add Source
o Browse the existing HDL file

Figure 3.6: Adding a Source to the project

Example: Gate-Level

module My_AND(yOut, aIn, bIn);

output yOut;
input aIn, bIn;

and G1(yOut,aIn,bIn); //AND gate instantiation

endmodule

Example: Dataflow

module My_AND(yOut, aIn, bIn);

output yOut;
input aIn, bIn;

assign yOut = aIn & bIn; //AND gate in dataflow description

endmodule

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3.5 Simulation result

 Click on Simulation icon as shown in Figure 3.7.

Figure 3.7: Simulation Window

3.5.1 Add test bench file

 Select Source Type (e.g. Verilog test fixture)

 Enter the file name (e.g. TB_Module_Name)
o Then click Next
o Then click Next
o Then click Finish
 Now add various value of input ports (e.g., A and B) as in Figure 3.8

Figure 3.8: Add new source file as a Verilog Test Fixture

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Stimulus Example:

module TB_My_AND; // Test bench has no inputs and outputs

// Inputs
reg aIn;
reg bIn;

// Outputs
wire yOut;

// Instantiate the Unit Under Test (UUT)

My_AND uut (yOut,aIn,bIn);

initial begin
// Initialize Inputs
aIn = 0; bIn = 0;

#10; // Wait 10 ns
aIn = 0; bIn = 1;

#10; // Wait 10 ns
aIn = 1; bIn = 0;

#10; // Wait 10 ns
aIn = 1; bIn = 1;

#10 $finish; //To finish the simulation

end
endmodule

3.5.2 ISE Simulator

 Click on ISE simulator it will open two options as shown in Figure 3.9
 Then double-click on Behavior check syntax and wait to verify by tick sign
 Then double-click on simulate behavior model, which will open a new window

Figure 3.9: ISE Simulator for simulation

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3.5.3 Simulation windows

Zoom to Full View

Figure 3.10: ISIM Simulation WAVE window

In-Lab Task 2:
Verify all the basic logic gates using the Xilinx ISE simulation tool and verify your
waveform with logic gates truth table.

Task 01: Write a Verilog code (Gate-Level) for NOT, OR, NOR, NAND, XOR and
XNOR.

Task 02: Write a stimulus/test bench for Task 01 and show the simulation results.

Post-Lab:
Task 01: Write a Verilog code for the given Boolean function* (e.g. 𝐹 = 𝑥 + 𝑥̅ 𝑦 + 𝑦𝑧̅ ):
a) Using Gate-Level model (Provide Gate Level diagram and Truth Table)
b) Using Dataflow model

Task 02: Write a stimulus/test bench for Task 01 and show the simulation results.
* (Note: Every student should opt different Boolean function)

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LAB #03: Introduction to Verilog and Simulation using XILINX ISE

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LAB #03: Introduction to Verilog and Simulation using XILINX ISE

Critical Analysis/Conclusion

Lab Assessment

Pre-Lab /1

In-Lab /5

Data
Analysis
/4 /10
Data
Post-Lab /4 /4
Presentation

Writing
/4
Style

Instructor Signature and Comments

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 LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

4. LAB #04: Implementation and Designing of Boolean

Functions by Standard Forms using ICs/Verilog

Objective
In this lab, we implement Boolean functions by using SoP (sums of product) and PoS
(products of sum).

Equipment Required
KL-31001 Digital Logic Lab Trainer, Breadboard, Logic gate ICs (NAND & NOR).

Pre-Lab:

Boolean Algebra
Boolean algebra is algebra for the manipulation of objects that can take on only two
values, typically true and false.

 It is common to interpret the digital value:

o 0 as false
o 1 as true

Boolean Function
A Boolean function typically has one or more input values and yields a result, based on these
input value, in the range {0, 1}. A Boolean operator can be completely described using a
table that lists inputs, all possible values for these inputs, and the resulting values of the
operation.

A Boolean function can be represented in a truth table and it can be transformed from an
algebraic expression into a circuit diagram composed of logic gates. In evaluating Boolean
equations AND operation is performed before OR operation unless OR operation is
enclosed with in brackets.

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LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

Basic Theorems
Table 4.1: Basic Boolean algebra theorems

Identity Name AND form OR form

Identity Law 𝑥. 1 = 𝑥 𝑥+0=𝑥

Null (or Dominance) Law 𝑥. 0 = 0 𝑥+1=1

Idempotent Law 𝑥. 𝑥 = 𝑥 𝑥+1=𝑥

Inverse Law 𝑥. 𝑥̅ = 0 𝑥 + 𝑥̅ = 1

Commutative Law 𝑥. 𝑦 = 𝑦. 𝑥 𝑥+𝑦 =𝑦+𝑥

Associative Law (𝑥. 𝑦). 𝑧 = 𝑥. (𝑦. 𝑧) (𝑥 + 𝑦) + 𝑧 = 𝑥 + (𝑦 + 𝑧)

Distributive Law 𝑥 + (𝑦. 𝑧) = (𝑥 + 𝑦). (𝑥 + 𝑧) 𝑥. (𝑦 + 𝑧) = (𝑥. 𝑦) + (𝑥. 𝑧)

Absorption Law 𝑥. (𝑥 + 𝑦) = 𝑥 𝑥 + (𝑥. 𝑦) = 𝑥

DeMorgan’s Law (𝑥. 𝑦) = 𝑥̅ + 𝑦 (𝑥 + 𝑦) = 𝑥̅ . 𝑦

Double Complement Law 𝑥̿ = 𝑥

Canonical Forms
Any Boolean function that is expressed as a sum of minterms or as a product of maxterms is
said to be in its canonical form.

In general, the unique algebraic expression for any Boolean function can be obtained from its
truth table by using an OR operator to combine all minterms for which the function is equal
to 1.

Minterm
A minterm denoted as 𝑚 , where 0 ≤ 𝑖 < 2𝑛, is a product (AND) of the 𝑛 variables
(literals) in which each variable is complemented if the value assigned to it is 0, and un
complemented if it is 1.

 1-minterms = minterms for which the function 𝐹 = 1.

 0-minterms = minterms for which the function 𝐹 = 0.

 Any Boolean function can be expressed as a sum (OR) of its 1-minterms.

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LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

A shorthand notation:

𝐹(𝑙𝑖𝑠𝑡 𝑜𝑓 𝑣𝑎𝑟𝑖𝑎𝑏𝑙𝑒𝑠) = (𝑙𝑖𝑠𝑡 𝑜𝑓 1-𝑚𝑖𝑛𝑡𝑒𝑟𝑚 𝑖𝑛𝑑𝑖𝑐𝑒𝑠)

 The inverse of the function can be expressed as a sum (OR) of its 0-minterms.

A shorthand notation:

𝐹 (𝑙𝑖𝑠𝑡 𝑜𝑓 𝑣𝑎𝑟𝑖𝑎𝑏𝑙𝑒𝑠) = (𝑙𝑖𝑠𝑡 𝑜𝑓 0-𝑚𝑖𝑛𝑡𝑒𝑟𝑚 𝑖𝑛𝑑𝑖𝑐𝑒𝑠)

Example:

Table 4.2: 3-variables Minterm example

𝒙 𝒚 𝒛 𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝑭 𝑭

0 0 0 𝑚 =𝑥𝑦𝑧 0 1
𝑚 =𝑥𝑦𝑧
0 0 1 0 1
𝑚 = 𝑥 𝑦𝑧
0 1 0 0 1
𝑚 = 𝑥 𝑦𝑧
0 1 1 1 0
𝑚 = 𝑥𝑦 𝑧
1 0 0 0 1
𝑚 = 𝑥𝑦 𝑧
1 0 1 1 0
𝑚 = 𝑥𝑦𝑧
1 1 0 1 0
𝑚 = 𝑥𝑦𝑧
1 1 1 1 0

𝐹 = 𝑥 𝑦𝑧 + 𝑥𝑦 𝑧 + 𝑥𝑦𝑧 + 𝑥𝑦𝑧 = 𝑚 + 𝑚 + 𝑚 + 𝑚

or

𝐹 (𝑥, 𝑦, 𝑧) = (3, 5, 6, 7)
Similarly,
𝐹 = 𝑥 𝑦 𝑧 + 𝑥 𝑦 𝑧 + 𝑥 𝑦𝑧 + 𝑥𝑦 𝑧 = 𝑚 + 𝑚 + 𝑚 + 𝑚

or

𝐹 (𝑥, 𝑦, 𝑧) = (0, 1, 2, 4)

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LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

Maxterm
A maxterm denoted as 𝑀 , where 0 ≤ 𝑖 < 2𝑛, is a sum (OR) of the 𝑛 variables (literals) in
which each variable is complemented if the value assigned to it is 1, and un complemented if
it is 0.

 0-maxterms = maxterms for which the function 𝐹 = 0.

 1-maxterms = maxterms for which the function 𝐹 = 1.

 Any Boolean function can be expressed as a product (AND) of its 0-maxterms.

A shorthand notation:

𝐹 (𝑙𝑖𝑠𝑡 𝑜𝑓 𝑣𝑎𝑟𝑖𝑎𝑏𝑙𝑒𝑠) = (𝑙𝑖𝑠𝑡 𝑜𝑓 0-𝑚𝑎𝑥𝑡𝑒𝑟𝑚 𝑖𝑛𝑑𝑖𝑐𝑒𝑠)

 The inverse of the function can be expressed as a product (AND) of its 1-maxterms.

A shorthand notation:

𝐹 (𝑙𝑖𝑠𝑡 𝑜𝑓 𝑣𝑎𝑟𝑖𝑎𝑏𝑙𝑒𝑠) = (𝑙𝑖𝑠𝑡 𝑜𝑓 1-𝑚𝑎𝑥𝑡𝑒𝑟𝑚 𝑖𝑛𝑑𝑖𝑐𝑒𝑠)

Example:

Table 4.3: 3-variables Maxterm example

𝒙 𝒚 𝒛 𝑴𝒂𝒙𝒕𝒆𝒓𝒎𝒔 𝑭 𝑭

0 0 0 𝑀 =𝑥+𝑦+𝑧 0 1
𝑀 =𝑥+𝑦+𝑧
0 0 1 0 1
𝑀 =𝑥+𝑦 +𝑧
0 1 0 0 1
𝑀 =𝑥+𝑦 +𝑧
0 1 1 1 0
𝑀 =𝑥 +𝑦+𝑧
1 0 0 0 1
𝑀 =𝑥 +𝑦+𝑧
1 0 1 1 0
𝑀 = 𝑥 +𝑦 + 𝑧
1 1 0 1 0
𝑀 =𝑥 +𝑦 +𝑧
1 1 1 1 0

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LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

𝐹 = (𝑥 + 𝑦 + 𝑧). (𝑥 + 𝑦 + 𝑧 ). (𝑥 + 𝑦 + 𝑧). (𝑥 + 𝑦 + 𝑧) = 𝑀 . 𝑀 . 𝑀 . 𝑀

or

𝐹 (𝑥, 𝑦, 𝑧) = (0, 1, 2, 4)

Similarly,

𝐹 = (𝑥 + 𝑦 + 𝑧 ). (𝑥 + 𝑦 + 𝑧 ). (𝑥 + 𝑦 + 𝑧). (𝑥 + 𝑦 + 𝑧 ) = 𝑀 + 𝑀 + 𝑀 + 𝑀

or

𝐹 (𝑥, 𝑦, 𝑧) = (3, 5, 6, 7)

Standard Forms

SoP (Sum of Products):

The term "Sum of Products" or "SoP" is widely used for the canonical form that is a
disjunction (OR) of minterms.

PoS (Product of Sum):

The term "Product of Sums" or "PoS" for the canonical form that is a conjunction
(AND) of maxterms.

Pre-Lab Tasks:
1. Express the Boolean function 𝐹 = 𝑥 + 𝑦𝑧 as a sum of minterms by using truth table.
2. Express 𝐹 = (𝑥 + 𝑦𝑧) as a product of maxterms.
3. Given the function as defined in the truth table (Table 4.4), express 𝐹 using sum of
minterms and product of maxterms.

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Table 4.4: Truth Table for F (Pre-Lab Task 3)

𝒙 𝒚 𝒛 𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝑴𝒂𝒙𝒕𝒆𝒓𝒎𝒔 𝑭 𝑭

0 0 0 𝑚 =𝑥𝑦𝑧 𝑀 = 𝑥+𝑦+𝑧 0 1
𝑚 =𝑥 𝑦 𝑧 𝑀 =𝑥+𝑦+𝑧
0 0 1 1 0
𝑚 = 𝑥 𝑦𝑧 𝑀 =𝑥+𝑦 +𝑧
0 1 0 0 1
𝑚 = 𝑥 𝑦𝑧 𝑀 = 𝑥+𝑦 +𝑧
0 1 1 1 0
𝑚 = 𝑥𝑦 𝑧 𝑀 =𝑥 +𝑦+𝑧
1 0 0 1 0
𝑚 = 𝑥𝑦 𝑧 𝑀 =𝑥 +𝑦+𝑧
1 0 1 0 1
𝑚 = 𝑥𝑦𝑧 𝑀 = 𝑥 +𝑦 + 𝑧
1 1 0 0 1
𝑚 = 𝑥𝑦𝑧 𝑀 =𝑥 +𝑦 +𝑧
1 1 1 0 1

In-Lab Tasks:

Circuit Implementation
1. First, make the circuit diagram of the given Task.
2. Select appropriate logic gate ICs which are needed.
3. Make connections according to the circuit diagram you made.
4. Connect the input to data switches and output to the logic indicator.
5. Follow the input sequence and record the output.

TASK: Implement the circuit for the given function “F”. Function’s output is given in Table
4.5. Finds its Boolean expression in SoP and PoS forms.

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LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

Table 4.5: Truth Table for F (In-Lab Task)

𝑨 𝑩 𝑪 𝑫 𝑭

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1

1 0 0 1 0

1 0 1 0 0

1 0 1 1 0

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

Boolean Equations:

Sum of Min-terms equation of F:

Reduced SOP form equation of F:

Product of Max-terms equation of F:

Reduced POS form equation of F:

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LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

Reduced form calculation:

Circuit Diagrams:

1. Sum of Min-terms form:

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LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

2. Reduced SoP form: (Implement circuit by NAND IC(s)):

3. Reduced PoS form: (Implement circuit by using NOR IC(s))

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LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

Table 4.6: Observation Table for In-Lab Task

Observed Outputs
𝑨 𝑩 𝑪 𝑫 𝑭
𝑭𝟏 𝑭𝟐 𝑭𝟑

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1

1 0 0 1 0

1 0 1 0 0

1 0 1 1 0

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

𝑭𝟏 : Output of sum of Min-terms form circuit.

𝑭𝟐 : Output of reduced SoP form circuit implemented using NAND gates.

𝑭𝟑 : Output of reduced PoS form circuit implemented using NOR gates.

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LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

Post-Lab Tasks:
1. Write a Verilog code for the sum of minterms circuit, 𝑭𝟏 , (Structural Level).
2. Write a Verilog code for the reduced SoP circuit, 𝑭𝟐 , (Structural Level).
3. Write a Verilog code for the reduced PoS circuit 𝑭𝟑 , (Structural Level).
4. Simulate and verify the outputs by making an appropriate stimulus for the above
modules.

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LAB #04: Implementation and Designing of Boolean Functions by Standard Forms using ICs/Verilog

Critical Analysis/Conclusion

Lab Assessment

Pre-Lab /1

In-Lab /5

Data
Analysis
/4 /10
Data
Post-Lab /4 /4
Presentation

Writing
/4
Style

Instructor Signature and Comments

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 LAB #05: Logic Minimization of Complex Functions using Automated Tools

5. Lab #05: Logic Minimization of Complex Functions

using Automated Tools

Objective

Part 1
In this lab, students will learn Karnaugh Map minimization and how to use logic
minimization automated tools for an excessive number of variables in a function.

Part 2
Minimized logic function results are verified by using Verilog Structural Level (Gate-Level)
description on Xilinx ISE Design tool.

Pre- Lab:

Background Theory:
We can simplify the equations and find a Boolean function of any truth table using K-Map.

K-Maps:

 3-Variables:

𝐵
𝐵𝐶
𝐴 00 01 11 10

0 𝑚 𝑚 𝑚 𝑚

𝐴 1 𝑚 𝑚 𝑚 𝑚

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LAB #05: Logic Minimization of Complex Functions using Automated Tools

 4-Variables:

𝐶
𝐶𝐷
𝐴B 00 01 11 10

00 𝑚 𝑚 𝑚 𝑚

01 𝑚 𝑚 𝑚 𝑚
𝐵
11 𝑚 𝑚 𝑚 𝑚
𝐴
10 𝑚 𝑚 𝑚 𝑚

In-Lab:

Part 1: Automated Tool (Karnaugh Map Minimizer) (for variable >4)

Figure 5.1: Karnaugh Map Minimizer Automated Tool Interface

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LAB #05: Logic Minimization of Complex Functions using Automated Tools

Equipment/Tools Required:
KL-31001 Digital Logic Lab, Breadboard, Logic gate ICs, K-map Minimizer automated tool
(Figure 5.1).

Procedure:

1. First, make the circuit diagram for the desired task or subtask given by the Lab
instructor.
2. Using k-map minimizer tool derive the simplified function:
a. Set the number of variables
b. Set the type of solution
c. Set the values of function ‘𝐹’. (Function values can be generated randomly) *
d. Click on solve button then the solution will come on solution screen.
3. Implement the circuit using logic gate ICs (which is/are needed) for the tasks.
4. Make connections according to the circuit diagram you made.
5. Connect the inputs to data switches and output to the logic indicator.
6. Follow the input sequence and record the outputs in Table 5.1.

In-Lab Task 1:
Implement the minimized function given below using logic gate IC(s).

𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ( , , , )

(Note: minterms will be specified by Lab Instructor)

Function in sum of Min-terms form:

Function in a simplified form using K-map:

Simplified calculation (K-map):

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LAB #05: Logic Minimization of Complex Functions using Automated Tools

Circuit Diagram of a min-terms form of the Function:

Number of gates/ICs used:

Circuit Diagram of a simplified Function:

Number of gates/ICs used:

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LAB #05: Logic Minimization of Complex Functions using Automated Tools

Truth Table:
Table 5.1: Observation Table for In-Lab Task

Observed Outputs
𝑨 𝑩 𝑪 𝑫 𝑭
𝑭𝟏 𝑭𝟐

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

𝑭𝟏 : Output of sum of Min-terms form circuit.

𝑭𝟐 : Output of simplified function circuit.

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LAB #05: Logic Minimization of Complex Functions using Automated Tools

Part 2: Verilog Design Task

Tools Required

K-map minimizer tool, Xilinx ISE Design tool.

In-lab Task 2
Using structural model, write a Verilog description for the 8-variable function ‘ F ’:

𝐹(𝐴, 𝐵, 𝐶, 𝐷, 𝐸, 𝐹, 𝐺, 𝐻) = ( , , , )

Procedure

 Function ‘ F ’ should be generated by Karnaugh Map Optimizer automated tool

 Function ‘ F ’ should be random
 Simulate and verify the output by making an appropriate stimulus on Xilinx ISE tool

Results

(Verilog Code & Simulation Wave Forms)

COMSATS Institute of Information Technology Page 67

LAB #05: Logic Minimization of Complex Functions using Automated Tools

COMSATS Institute of Information Technology Page 68

LAB #05: Logic Minimization of Complex Functions using Automated Tools

Post-Lab Tasks:
1. Using dataflow model, write a Verilog description for the 8-variable function ‘ F ’
(used in “In-Lab Task 2”):
2. Simulate and verify the output by making an appropriate stimulus on Xilinx ISE tool

Results

(Verilog Code & Simulation Wave Forms)

COMSATS Institute of Information Technology Page 69

LAB #05: Logic Minimization of Complex Functions using Automated Tools

COMSATS Institute of Information Technology Page 70

LAB #05: Logic Minimization of Complex Functions using Automated Tools

Critical Analysis/Conclusion

Lab Assessment

Pre-Lab /1

In-Lab /5

Data
Analysis
/4 /10
Data
Post-Lab /4 /4
Presentation

Writing
/4
Style

Instructor Signature and Comments

COMSATS Institute of Information Technology Page 71