IMPLEMATION AND PARAMETERS EXTRACTION
OF FULL ADDER USING DOMINO LOGIC
A Mini Project-based lab report submitted to
submitted in partial fulfilment of the award of degree
BACHELOR OF TECHNOLOGY
(E.C.E)
KLEF
Submitted by:
NAME ID. No
A. REVANTH 170040020
CH. SAKETH AVINASH 170040136
CH. KARTHIK 170040167
Under the esteemed guidance of
NAME OF FACULTY: Mr.B. KALI VARA PRASAD (Asst.Prof)
KLEF
Green Fields, Vaddeswaram,
Guntur Dist. -522502.
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KONERU LAKSHMAIAH EDUCATIONAL FOUNDATION
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Certificate
This is to certify that the Project Report entitled “DOMINO LOGIC IMPLEMENTATION
AND PARAMETER EXTRACTION OF FULL ADDER CIRCUIT” is being submitted by
A.REVANTH (170040020) CH.SAKETH AVINASH(170040136), CH.KARTHIK
(170040167), in partial fulfilment for the award of Bachelor of Technology in VLSI Skilling
during the academic year 2019-20.
Signature of the Supervisor Course Corrdinator
(Your Faculty Name) (Course Coordinator Name)
Signature of the HoD
(HoD Name)
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Declaration
I hereby declare that this project based lab report has been prepared by my batch in partial
fulfilment of the requirement for the award of degree “Bachelor of Engineering and Technology
in Department of Electronics and Communication Engineering” during the academic year 2019-
2020.
I also declare that this project based lab report is of my own effort and it has not been submitted
to any other university for the award of any degree.
1. A,REVANTH (170040020)
2. CH.SAKENTH (170040136)
3. CH.KARTHIK (170040167)
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ACKNOWLEGDEMENT
Apart from the efforts of ours, the success of any work depends largely on the encouragement
and guidelines of many others. We take this opportunity to express our gratitude to the people
who have been instrumental in the successful completion of this project based lab report.
We express our gratitude to our parents who have supported us in completion of our project
without any complexities.
We express our gratitude to our Project Guide K. Suresh Kumar, Asst.Professor, Dept of
Electronics & Communications Engineering. We can’t thank him enough for tremendous
support and help. We feel motivated and encouraged every time we attend his meeting. Without
his encouragement and guidance this Project would not have materialized.
We are thankful to our Head of the Department Dr. Suman Maloji, Professor, Dept of
Electronics & Communications Engineering who modeled us both technically and morally
for achieving greater success in life.
We would like to show our greatest appreciation to Dr. N. Venkatram, Dean Academics,
KLEF for his valuable suggestions and statements.
Finally, we owe a lot to the teaching and non-teaching staff of the Dept. of ECE for their direct
or indirect support in doing our Lab based project work.
1. A.REVANTH (170040020)
2. CH.SAKENTH (170040079)
3. CH.KARTHIK (170040091)
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CONTENTS
S.NO TITLE PAGE NO
1) CHAPTER:1 6
2) CHAPTER:2 7
3) CHAPTER:3 8
4) CHAPTER:4 10
5) CHAPTER:5 10
6) CHAPTER:6 10
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1.ABSTRACT
Adders are basic building blocks of any processor or data path application. For
the design of high performance processing units high speed adders with low
power consumption is a requirement. In this paper, we present a new architecture
using Manchester carry chain(MCC) in multi output domino CMOS logic. It
employs a novel MCC blocks in an hierarchical approach in the design of the
CSA. The proposed design is validated by implementation of16 and 32-bit adder
circuits in a standard 45nm CMOS process technology. This proposed work
evaluates the performance of the proposed designs in terms of delay, power
consumption and hardware overhead. The results are analysed and compared with
existing fast adder architectures to prove its efficiency. The simulation results
shows that the proposed architecture achieves two fold advantages in terms of
power-delay product (PDP) and hardware overhead.
Keywords - Manchester carry chain(MCC), multioutput Domino logic, PDP,
Speed.
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2.INTRODUCTION
As the requirement for high performance processor grows, there is a constant
need to enhance the performance of data path units. Addition is the most
commonly used arithmetic operation and the performance of VLSI processor is
enormously impacted by performance of resident adder. A high performance
adder with low power consumption designed
with minimum area plays an indispensable role in large portion of the hardware
circuits. For adding two binary numbers several types of adders have been
designed, for example ripple-carry, carry-skip, etc. The major speed restriction in
the conventional adder circuits, such as ripple carry adder (RCA) and carry save
adder arises from the long computation time required for generating the outputs .
CSA and carry look-ahead architectures have been suggested to reduce large
carry propagation delay of adders.The main advantage of CSA is it alleviate the
problem of carry propagation delay. This is realized by use of parallel structure
that results from multiple pairs of ripple carry adder (RCA) and final sum and
carry output is chosen by multiplexers . The main difference between a CSA and
RCA is that in a RCA the carry has to ripple through all full-adders, but in the
case of a CSA the carry has to pass through a single multiplexer.
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3.Figures
1.Circuit proposed
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3.SIMULATION RESULTS
Comparison
Circuit Power Delay(ns) Pdp(fj) No of
techniques dissipation(uw) transistor
CMOS 460 1.1 506 28
Transmission 352 0.78 27.45 22
gate
Domino 215 0.869 279 34
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4. Conclusion
. The proposed design technique has been applied for the implementation of 16-bit and 32-bit
adders. The proposed CSA design involves significantly less delay, power delay product and
hardware overhead when compared with the other adder structures. Hence, proposed CSA
design can be used for power-delay efficient devices with minimum hardware overhead.
Simulation results validate the efficiency of the proposed CSA design.
5. FUTURE ENHANCEMENT
This is already being implemented in many ways and enhancements are continuing on to
make it consume less transistors and area
6.REFERENCES:
http://www.iosrjournals.org/iosr-jece/papers/Vol.%2010%20Issue%203/Version-3/H010335563.pdf
https://www.ijcseonline.org/spl_pub_paper/5-IJCSE-PCMT-5.pdf
http://www.iraj.in/journal/journal_file/journal_pdf/1-345-149199805440-44.pdf
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