Experiment No. 6
Experiment No. 6
6
Experiment Date: 7th Sept 2019 Submission Date: 7th Nov 2019
Aim :
1. To write a Verilog program for implementation of full adder.
2. To write a Verilog program for implementation of full adder using structural
style of modelling.
3. To write a Verilog program for implementation of 3:8 decoder.
4. To write a Verilog program for implementation of 4 bit full adder using
structural style of modelling.
Software Used :
Intel Quartus II
Code :
A. Full Adder
module adder (i1, i2, cin, s, cout);
input i1, i2, cin;
output s, cout;
assign s = i1 ^ i2 ^ cin;
assign cout = (i1 & i2) | (cin & i2) | (cin & i1);
endmodule
endmodule
module HA (a,b,s,c);
input a,b;
output s,c;
assign s = a ^ b;
assign c = a & b;
endmodule
C. Decoder
module danidecoder (i, o);
input [2:0] i;
output [7:0] o;
reg [7:0] o;
always @ (i)
begin
case (i)
3'b000 : o = 8'b00000001;
3'b001 : o = 8'b00000010;
3'b010 : o = 8'b00000100;
3'b011 : o = 8'b00001000;
3'b100 : o = 8'b00010000;
3'b101 : o = 8'b00100000;
3'b110 : o = 8'b01000000;
3'b111 : o = 8'b10000000;
endcase
2
end
endmodule
D. 4 Bit Full Adder
module fulldaniadder(m, n, Cin, Sum, Cout);
input [3:0] m,n;
input Cin;
output [3:0] Sum;
output Cout;
wire t1, t2, t3;
FA F1 (m[0], n[0], Cin, Sum[0], t1);
FA F2 (m[1], n[1], t1, Sum[1], t2);
FA F3 (m[2], n[2], t2, Sum[2], t3);
FA F4 (m[3], n[3], t3, Sum[3], Cout);
endmodule
module HA (a,b,s,c);
input a,b;
output s,c;
assign s = a ^ b;
assign c = a & b;
endmodule
3
Waveforms :
A. Full adder
4
RTL View :
A. Full adder
Results :
1. A Verilog program for a full adder using structural style of modelling was
implemented.
2. 4 bit full adder was implemented using 4 full adders by structural style of
modelling in VHDL.
3. A Verilog program for 3:8 decoder using behavioural style of modelling was
implemented.