ADVANCED VLSI DESIGN

(MEL G623)
Project Report
On
DESIGN OF CLOCK AND DATA RECOVERY
CIRCUITS WITH FAST ACQUISITION AND
LOW JITTER

Submitted By:
Dilsya Joy 2017H1230220P

Apoorva Agarwal 2017H1230229P

Submitted To:
Dr. Anu Gupta

Electrical and Electronics Department

BITS Pilani (Pilani Campus)

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 ABSTRACT

Technology scaling and unprecedented growth in demand for ubiquitous,

fast, robust computing have been the driving forces leading the innovations in
high-speed interfaces. Today’s demands necessitate operation of transmission links
at speeds in the gigahertz range. At such accelerated rates, maintaining signal
integrity becomes a challenging task. It is imperative for creditable data links to
over high data accuracy at high speeds.
The clock and data recovery (CDR) module is responsible for reconstructing
the original transmitted bit-stream at the receiver. The data clock is generated by
using a phase locked loop (PLL) as a frequency synthesizer. It steps up the clock
frequency of a crystal clock to that of the data rate. The CDR takes the incoming
data and generates a clock using the data specs which can then be used by the data
resampler to sample the data accurately. This report looks into the basic principles
of operation of phase locked loops, Clock and Data recovery circuits and their
building blocks for a 10 Gbps link. It summarizes the challenges in design and also
presents a Cadence approach to the circuit design in 180 nm CMOS technology.

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 ACKNOWLEDGEMENTS

I would like to express my gratitude to my Professor Dr. Anu Gupta for guiding
me throughout this project with her invaluable knowledge. She was always
supportive of my work since I began studying VLSI courses at BITS Pilani.

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 TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . 6

CHAPTER 2 LITERATURE REVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Phase Detector (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 Charge Pump (CP) and Low Pass Filter (LPF) . . . . . . . . . . . . . . . . . 14
2.1.3 Voltage Controlled Oscillator (VCO) . . . . . . . . . . . . . . . . . . . . . . . . .16

CHAPTER 3 ALEXANDER PHASE DETECTOR. . . . . . . . . . . . . . . . . . . . . . . .17

3.1 Alexander Phase Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
3.1.1 Transistor level Alexander PD with TSPC Logic. . . . . . . . . . . . . . . .
.20
3.1.2 Transistor level Alexander PD with CML Logic. . . . . . . . . . . . . . . . .
.22

CHAPTER 4 CHARGE PUMP AND VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.1 Charge Pump . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .
28
4.1.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
4.2 Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..31

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 4.2.1 Harmonic Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.31
4.2.2 Relaxation Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
4.2.3 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.32
4.2.4 LC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33

CHAPTER 5 CDR BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .35

5.1 Complete CDR Architecture with TSPC . . . . . . . . . . .. . . . . . . . . . . . . 36
5.2 Complete CDR Architecture with CML. . . . . . . . . . .. . . . . . . . . . . . . . 37
5.3 Data Recovery with Noisy Data . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .39
5.4 Eye-Diagrams- Jitter Comparison . . . . . . . . . . .. . . . . . . . . . . . . . . . . . 40

CHAPTER 6 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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 LIST OF FIGURES

Fig. 1 Simplified Block Diagram of Digital Receiver

Fig. 2 Basic elements of the PLL based CDR
Fig. 2.2 Basic linear phase detector and output waveforms.
Fig. 2.3 Hogge Phase Detector and its output waveform.
Fig. 2.4 Charge Pump with Type-I LPF
Fig. 3.1 Alexander phase detector
Fig 3.2 Transistor Level Alexander Phase Detector
Fig. 3.3 Schematic of TSPC based D-FF
Fig. 3.4 Data Loss in TSPC D-FF
Fig. 3.5 CML based D-FF
Fig. 3.6 Simulation of CML based D-FF
Fig. 3.7 CML Based EXOR Gate
Fig. 3.8 Simulation of CML Alexander PD
Fig. 3.9 Clock Late
Fig. 3.10 Clock Early
Fig. 4.1 Schematic of Charge Pump
Fig 4.2 Charging of charge pump
Fig. 4.3 Discharging of charge pump
Fig. 4.4 Schematic of Ring Oscillator
Fig 4.5 Frequency VS Vcontrol
Fig. 4.6 Schematic of LC Oscillator
Fig. 5.1 CDR Architechture

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Fig. 5.2 Simulation of CDR with TSPC
Fig. 5.3 Simulation of CDR with CML
Fig. 5.4 Successful Sampling of noisy data
Fig 5.5 Unsuccessful sampling of high noise data
Fig. 5.6 Eye Diagram of Ring Oscillator
Fig. 5.7 Eye-Diagram of CDR with LC Oscillator
Fig. 5.8 Eye-Diagram of Modified CDR

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 CHAPTER 1

INTRODUCTION
In wire-linked communication systems, when data flows over a single wire without
any accompanying clock, the receiver of the system is required to process this data
synchronously. Therefore, the CDR circuits are used in the receiver of the system
to recover the clock or timing information from these data. Data bandwidth for
wire-linked communication systems is also increasing at a high rate. In 2007,
according to the International Technology Roadmap for Semiconductors (ITRS),
the non-return to zero (NRZ) data rate for high-performance differential pair point-
to-point nets on the package would reach 100 Gbps by the year 2019.
In such high-speed wire-linked communication systems, these data are
corrupted both by internal and external noise during its passage from transmitter to
receiver, resulting in jitter and skew in the data received at the receiver. Here, the
clock and data recovery circuit is necessary to extract the data transmitted by the
transmitter from the corrupted received signal and also to recover the accompany
clock timing information at the receiver side of the communication systems.
In a source asynchronous system, the transmitter and receiver use different clock
sources of the same frequency. The received data are first equalized in the receiver
input buffer and then fed to the CDR circuit for retiming before proceeding into the
deserializer module. Hence, there exists a frequency offset between the transmitted
data and the local clock on the receiver side due to natural device mismatches,
which creates the challenges for CDR circuit designers. Clock and data recovery
(CDR) has been widely used in data communication systems, including optical

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communication, backplane routing, chip-to-chip interconnects, and disk drive read
channels.

Fig. 1 Simplified Block Diagram of Digital Receiver

Binary data is commonly transmitted in the “nonreturn-to-zero” (NRZ) format.

The ability to regenerate binary data is an inherent advantage of digital
transmission. To perform this regeneration with the fewest bit errors, the received
data must be sampled at the optimum instants in time. Since it is generally
impractical to transmit the requisite sampling clock signal separately from the data,
the timing information is usually derived from the incoming data itself. The
random data received in these systems are both asynchronous and noisy, requiring
that a clock be extracted to allow synchronous operations. The recovered clock
both removes the jitter and distortion in the data and retimes it for further
processing. It is called clock and data recovery, and its general role in digital
receivers is illustrated in Fig. 1.
The clock generated in the circuit of Fig. 1 must satisfy the following
conditions:
 The frequency of the clock must be equal to the data rate.
 The clock must have appropriate timing with respect to the data,
allowing optimum sampling of the data by the clock; if the rising

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 edges of the clock occur in the midpoint of each bit, the sampling
occurs farthest from the data transitions, providing maximum margin
for jitter and other time uncertainty.
 The clock must exhibit a small jitter since the jitter of the clock
contributes to the retimed data jitter.
The data retiming circuit uses a Delay Flip Flop (DFF), which is triggered by the
recovered clock to retime the received data. The DFF samples the corrupted
received data and regenerates the data with less jitter and skew.
Both phase locked loop (PLL) and delay locked loop (DLL) have been widely used
in clock and data recovery. PLL solutions to CDR usually use narrow-band loop
filters to reduce jitter which results in longer acquisition times. Usually this is in
the ½ to 1 microsecond range. If the jitter is low, less coding is needed to reduce
the number of bit errors. DLL CDRs can lock to the data in just a few clock cycles
by means of phase selection but have high jitter that results in higher bit error rate.
Thus, more coding overhead is needed to reduce the number of bit errors.
Therefore, there are tradeoffs between fast acquisition and low jitter.

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 CHAPTER 2
LITERATURE REVIEW

In many systems, data are transmitted or retrieved without any additional time
reference, but the receiver must eventually process the data synchronously. Thus,
the time information (e.g. clock) must be recovered from the data at the receive
end. The common ways to recover the clock are with a phase locked loop or a
delay locked loop (DLL).

2.1 Phase Locked Loop

A PLL is a feedback system that operates on the excess phase of nominally
periodic signals. The basic topologies and a number of important parameters are
discussed for better understanding. A PLL is a negative feedback system where a
clock generated by the voltage control oscillator is phase and frequency locked to
an input data. Figure 2.1 shows basic elements of the PLL based CDR.
• Pre-Amplifier and Limiter
• Phase Detector (PD)
• Charge-Pump (CP) and Low Pass Filter (LPF)
• Voltage Controlled Oscillator (VCO)
The function of the Pre-Amplifier and Limiter is to generate a full voltage swing
from the input data, required by the phase detector. The functions of the PD, CP
and LPF, and VCO are discussed in following sections.

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 Fig. 2.1 Basic elements of the PLL based CDR

2.1.1 Phase Detector (PD)

The function of the phase detector is to measure the phase difference
between two incoming signals. Examples are clock and data signals, data and data
signals, and clock and pseudo random bit data (PRBS) signals. Various topologies
and designs for phase detectors already exist, such as the Alexander Phase
Detector, the Hogge Phase Detector, the Quad-rate Phase Detector, the Octant-rate
Phase Detector, etc.
Phase detectors are broadly classified into two classes: linear and binary
phase detectors. Linear phase detectors (PD) are used in low to medium speed
CDR applications, operating at few hundreds of megahertz (MHz) speed. Binary
phase detectors are used in high-speed CDR applications operating at hundreds of
gigahertz (GHz) speed. In the case of linear phase detectors, the output of the
phase detector is linearly proportional to the phase difference between two input
signals. One DFF with an XOR gate is enough to satisfy the requirement of linear
phase detector, but as the average value of the phase detector output is a function

12
of the data transition density of the input, this design fails to uniquely represent the
phase difference for various data patterns as shown in Figure 2.2, thus, this design
is data pattern dependent

Fig. 2.2 Basic linear phase detector and output waveforms.

One example of a linear phase detector is the Hogge Phase Detector. The
circuit implementation and output waveform is shown in Figure 2.3. The Hogge

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Phase Detector consists of two DFFs and two Exclusive OR (XOR) gates. The
function of a DFF is to produce a delayed replica of the input signal at its output.
The first DFF, named FF1, produces a delayed replica of the input data at the rising
edge of the clock and is then XORed with input data. The output of the XOR gate,
named X, gives the phase difference between two input signals. To avoid the
problem of data pattern dependency, the proportional pulses obtained at node X are
accompanied by reference pulses at node Y, which are generated by using an
additional DFF (FF2) and XOR gate. The reference pulses appear on the data edge
and have constant pulse width, thus avoiding the pattern dependency, as shown in
Figure 2.3.

Fig. 2.3 Hogge Phase Detector and its output waveform.

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 To summarize, this PD samples the data using the VCO clock for which a
DFF and a XOR gate perform the explicit function of edge detection. Then, we
produce a reference pulse, using the other DFF and XOR to eliminate the
ambiguity for different data transitions. Due to the Clock to Q delays of the flip-
flops, the Din and Clock must sustain a skew to equalize the widths of the output
pulses. This skew effect becomes significant at high speeds as the skew ΔT
becomes a significant fraction of the clock period. This might lead to a phase offset
after the loop is locked which degrades the clock phase margin and jitter tolerance.
To overcome this, we can widen the reference pulses by ΔT/2 or narrow the
proportional output pulses by the same amount. One of the disadvantages of the
Hogge PD is that there is a skew of TClk/2 between the two output pulses in the
locked condition. This causes a lot of disturbance in the VCO. As this is a linear
PD it sends out small average signals to the charge pump resulting in little activity
at the charge pump.
In binary phase detectors, the output is either logic one or zero. One example
of a binary phase detector is the Alexander Phase Detector. The Alexander Phase
Detector accepts two input signals (e.g. clock and data) and determines whether the
clock is earlier or later than the data. If the clock is earlier than the data, the early
node goes to logic one and the late node goes to logic zero. Otherwise, when the
clock is later than the data, the late node goes to logic one and early node goes to
logic zero. A more detailed explanation of the Alexander Phase Detector is
presented in Chapter 3.

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2.1.2 Charge Pump (CP) and Low Pass Filter (LPF)
The function of the charge pump is to convert the output voltage of the
phase detector to current. This current is then fed to a low pass filter, where the
capacitor is either charged or discharged depending on the phase detector output.
The circuit diagram of the charge pump with a Type-I LPF (capacitor) is shown in
Figure 2.4 and a Type-II LPF is shown in Figure 2.5.
In this project, the Alexander Phase Detector is used, where the output is
either early or late. The early and late nodes are connected to respective switches
of the charge pump circuit, as shown in Figure 2.5. When the early node is high,
closing the early switch, the capacitor starts charging and continues to charge until
the early node goes low, opening the early switch. Similarly, when the late node
goes high, the capacitor starts to discharge and will continue to discharge until the
late node goes low.

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 Fig. 2.4 Charge Pump with Type-I LPF
Designing a charge pump is not an easy task, because to achieve zero net
voltage on the capacitor, the charging current should be equal to the discharging
current. Even if the charging and discharging currents are designed to be close to
equal, there will still be leakage current through the charge pump circuit, resulting
in an offset voltage on the capacitor. One way to minimize this offset voltage is to
calibrate the charge pump circuit by using a feedback loop circuitry.

Fig. 2.5 Type-II LPF

The function of the low pass filter (LPF) is to convert the charge pump
current into control voltage. The Type-I LPF is replaced by Type-II LPF due to
trade-offs between the settling time, ripple on the control voltage, and the phase
error and stability. To minimize the ripples on the control voltage, the capacitor
from Figure 2.5 is replaced by the resistor (R) in series with the capacitor (C1),
both in parallel with the capacitor (C2), as shown in Figure 2.5. If the capacitor

17
(C2) is five to ten times less then capacitor (C1), then the Type-II LPF will still
approximately behave as a Type-I LPF.
2.1.3 Voltage Controlled Oscillator (VCO)
The function of the voltage control oscillator is to generate the clock signal
at its output, the frequency of which can be changed by varying the input control
voltage. Oscillators have wide applications in communication system ranging from
clock generation in microprocessors to carrier synthesis in cellular telephones.
Detailed working of Oscillators will be explained in chapter 4.

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 CHAPTER 3
ALEXANDER PHASE DETECTOR

3.1 Alexander Phase Detector

The Alexander PD is a binary phase detector and provides the inherent data
retiming for the CDR system. The Alexander PD consists of four DFFs and two
XOR gates as shown in Figure 3.1. The Alexander PD uses three data samples S1-
S3 that are sampled by the three consecutive clock edges. The Alexander PD
performs two functions:
1) Determines, whether there is any transition in the input data, and
2) Whether the clock is earlier or later than the input data.
When there is no transition in the input data, all the three samples will have equal
values and no action is taken by the Alexander PD. If the falling edge of the clock
leads (is “early”) then the first two samples S1 and S2 will have equal values and
the last sample S3 will have a value, unequal to that of first two samples.
Conversely, if the falling edge of the clock lags (is “late”) then the last two
samples S2 and S3 will have equal values and the first sample S1 will have a value,
unequal to that of last two samples. The decisions of the Alexander PD depend on
the values of the three samples (S1, S2, and S3) and are presented in Table 3.1.
In Figure 3.1, the first flip flop (FF1) samples the input data at S1 and S3 on
the rising edge of the clock and the second flip flop (FF2) delays the output of the
first flip flop (FF1) by one clock cycle. The third flip flop (FF3) samples the input

19
data at S3 on the falling edge of the clock and the fourth flip flop (FF4) delays the
output of the third flip-flop (FF3) by half a clock cycle.
As seen from the waveform of Figure 3.3, for the early case, the FF1
samples the high data level (logic one) at the first rising edge of the clock. At the
second rising edge of the clock, the FF2 performs two functions:
1) Produces the replica of the first sample (S1) delayed by one clock cycle, at
the output of the FF2, and
2) Samples the low data level (logic zero).
The FF3 samples the high data level (logic one) at the first falling edge of the
clock.
At the next rising edge of the clock, the FF4 produces the replica of the second
sample (S2) delayed by half a clock cycle, at its output. The clock phases of all the
four DFFs should be such that, the three samples S1, S2, and S3 reaches a valid
logic level for comparison at t = T1 and remains constant for one clock period.
Once the three samples S1, S2, and S3 reaches valid logic level and remain
constant for one clock period, the XOR gate produces a valid logic level at the
output. The same process is vice versed for the late case and shown in Figure 3.1.
S1 S2 S3 Decision
0 0 0 Cannot determine whether the clock is earlier or later than the data.

0 0 1 Clock is earlier than the data.

0 1 0 CDR is in the lock mode.

0 1 1 Clock is later than the data.

1 0 0 Clock is later than the data.

1 0 1 CDR is in lock mode.

1 1 0 Clock is earlier than the data.

1 1 1 Cannot determine whether the clock is earlier or later than the data.

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Table 3.1: Decisions of the Alexander PD.

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 Fig. 3.1 Alexander phase detector
3.1.1 Transistor level Alexander PD with TSPC Logic
The complete Alexander PD designed in cadence using TSMC 180nm
technology is as shown in Fig. 3.2. It consists of three Positive edge triggered D-
FF, one Negative edge triggered D-FF and two Exor gates all using TSMC logic.

Fig 3.2 Transistor Level Alexander Phase Detector

The sizes of the transistors used in TSPC logic are given in table 3.2. All
dimensions are given in micrometer. The circuit consists of alternating stages
called n-blocks and p-blocks and each block is being driven by the same clock
signal. The schematic of original TSPC flip-flop is shown in Fig.3.3. In this design
a single global clock signal needs to be generated and distributed in order to
simplify the design. Fig.3.3 presents positive edge triggered TSPC D-flip-flop. It is
operated as when the clock signal clk is LOW, the input is isolated from the output.

22
When clock makes a LOW-to-HIGH the output will latch the complement of the
input.
Transistor Size
PMOS 8/0.18
NMOS 4/0.18
Table 3.2: Dimension of TSPC D-FF

Fig. 3.3 shows the schematic of TSPC D flip-flop with 11 transistors, this edge
triggered flip-flop uses just a single clock signal for synchronization. Fig.1 shows
the positive edge triggered 11 transistors TSPC (True Single Phase Clocking) flip-
flop. During the ON period whatever is the value of input it becomes output.

Fig. 3.3 Schematic of TSPC based D-FF

This TSPC based implementation fails at higher data rates as it is not able to
sample the inputs at such higher rates. Fig. 3.4 shows that the TSPC D-FF was not

23
able to sample the data correctly at a data rate of 10Gbps. Thus the need for
another type of logic which was capable of wideband operations.

Fig. 3.4 Data Loss in TSPC D-FF

3.1.2 Transistor level Alexander PD with CML Logic

The high data rate needs all blocks to operate in current mode. In this work,
the concept of inductive peaking we also incorporated in each block to further
increase the speed and bandwidth. While the peaking technique improves the
sampling bandwidth of the M0-M1 pair, it also helps the regeneration of M2-M3
pair. The techniques improve the bandwidth by utilizing the resonance
characteristics of LC network. Current-mode circuits exhibit many intrinsic
advantages over their voltage-mode counterparts including large band-width, high
slew rate and low supply voltage requirement. A main drawback of these circuits is

24
their low current gain. To increase the current gain, the size of the transistor in the
output branch can be made large, however, at the cost of reduced bandwidth. The
schematic of CML D-FF is shown in Fig. 3.5.

Fig. 3.5 CML based D-FF

Fig. 3.5 shows a positive edge triggered D-FF. When the clock ck goes high
the data at the input is reflected at the output using either the M0 or M1 path
depending on the input. When clock goes low the data is retained at the output via
the M2-M3 path. The sizes of transistors are given in table 3.3.

25
 M0,M1 M2,M3,M4,M5 L R Iss
5/0.18 12/0.18 1p 300 10m
Table 3.3: Sizes of CML D-FF
The simulation of this D-FF showed that the data is retained even at data rate
of 10Gbps.

Fig. 3.6 Simulation of CML based D-FF

Fig 3.7 shows the schematic of EXOR gate based on CML Logic and table
3.4 gives its sizes.

NMOS L R Iss
12/0.18 1p 600 2.5m
Table 3.4: Sizes of CML EXOR gate

26
 Fig. 3.7 CML Based EXOR Gate

3.2 Simulation Results

The CML based Alexander phase detector was simulated in cadence.
Fig 3.8 shows the UP and DOWN signal generated depending on whether the
clock is early or late. Fig. 3.9 shows the clock signal arriving late or data arriving
early and the UP signal being generated.

27
Fig. 3.8 Simulation of CML Alexander PD

Fig. 3.9 Clock Late

28
Fig. 3.10 Clock Early

29
 CHAPTER 4
CHARGE PUMP AND VCO

4.1 Charge Pump

The output pulses of the PD drive the current mirror of a charge pump, as
shown in Fig. , to assure the charge to the filter will not vary with the VCO control
voltage. Decreasing the current level of the charge pump reduces the ripple on the
VCO control voltage and hence the jitter but at the expense of acquisition time and
range. A larger current is initially used to achieve acquisition with larger loop
bandwidth and then the charge pump can be switched to a smaller current to reduce
the jitter after lock is achieved. The smaller current also allows a smaller
implementation of the filter capacitor on the chip.

PMOS NMOS IDC

10/0.18 5/0.18 200u
Table 4.1 Sizes of Charge Pump

30
 Fig. 4.1 Schematic of Charge Pump

When the up pulses arrive, the upper circuit charges the capacitor C0 as the
transistor M21 is off. Similarly, when the down pulses arrive the lower circuit
discharges the capacitor C0 as the transistor M10 is off. Here current mirror is used
for charging and discharging. The voltage across the capacitor is the control
voltage (vcontrol) for the VCO.
The transistor sizes are as shown in table 4.1.

31
4.1.1 Simulation Results

Fig 4.2 Charging of charge pump

Fig. 4.3 Discharging of charge pump

32
 As the results show, when continuous up pulses are applied as in Fig 4.2,
piecewise linear increase is observed in vcontrol. Similarly, when continuous down
pulses are applied as in Fig. 4.3, piecewise linear decrease is observed in vcontrol.

4.2 Voltage Controlled Oscillator

A Voltage controlled oscillator is an oscillator with an output signal whose
output can be varied over a range, which is controlled by the input DC voltage. It is
an oscillator whose output frequency is directly related to the voltage at its input.
The oscillation frequency varies from few hertz to hundreds of GHz. By varying
the input DC voltage, the output frequency of the signal produced is adjusted.
According to the type of waveform produced voltage controlled oscillators are
categorized into two groups namely harmonic oscillators and relaxation oscillators.

4.2.1 Harmonic Oscillator

Harmonic or linear voltage controlled oscillator produces the sinusoidal
output waveform. Crystal and LC oscillators are the examples of this type of VCO.
In this VCO, voltage across the diode varies the varactor diode’s capacitance.
Hence the varactor changes capacitance of the LC circuit thereby the frequency
changes.
With respect to the power supply, temperature and noise frequency stability is
much better for these oscillators compared with relaxation oscillators. But the
disadvantage of this oscillator is that it cannot be implemented easily on a
monolithic IC.

33
4.2.2 Relaxation Oscillator

These VCOs are used to generate a triangle or sawtooth waveform. These

can be easily implemented on monolithic ICs which can be tunable over a wide
range of frequencies. These oscillators again classified into emitter coupled VCO,
grounded capacitor VCO and delay based ring VCO. In this project, LC oscillator
and delay based ring VCO are compared.

4.2.3 Ring Oscillator

A ring oscillator is a device composed of an odd number of NOT gates

whose output oscillates between two voltage levels, representing true and false.

34
 Fig. 4.4 Schematic of Ring Oscillator

The NOT gates, or inverters, are attached in a chain; the output of the last
inverter is fed back into the first. Because a single inverter computes the logical
NOT of its input, it can be shown that the last output of a chain of an odd number
of inverters is the logical NOT of the first input. This final output is asserted a
finite amount of time after the first input is asserted; the feedback of this last output
to the input causes oscillation. A real ring oscillator only requires power to operate;
above a certain threshold voltage, oscillations begin spontaneously. To increase the
frequency of oscillation, two methods may be used. Firstly, the applied voltage
may be increased; this increases both the frequency of the oscillation and the
power consumed, which is dissipated as heat.
The schematic for a 3 stage ring oscillator is shown in Fig. 4.4. Width of the
Pmos and Nmos are in the ratio Wp:Wn=12:0.18.
The output at the third stage gets inverted as odd numbers of stages are used and
this output is fedback to the first stage. Therefore the output of the third stage
keeps on changing after each cycle and this results in oscillations.

4.2.4 LC Oscillator
An LC oscillator is actually a feedback oscillator which uses capacitors and
inductors in its feedback network. It can be built from a transistor, an operational
amplifier, a tube, or some other active (amplifying) device. Oscillation is brought
about by applying a portion of the amplifiers’ output signal to its input. That
feedback signal must be applied in phase with the original input signal. The
amplifier is usually an inverter that provides 180o of phase shift by itself, and an
additional 180o of phase shift must be provided through some other means.

35
 In an LC oscillator circuit, the feedback network is a tuned circuit (often
called a tank circuit). The tuned circuit is a resonator consisting of an inductor (L)
and a capacitor (C) connected together. Charge flows back and forth between the
capacitor's plates through the inductor, so the tuned circuit can store electrical
energy oscillating at its resonant frequency. There are small losses in the tank
circuit, but the amplifier compensates for those losses and supplies the power for
the output signal. LC oscillators are often used at radio frequencies, when a tunable
frequency source is necessary, such as in signal generators, tunable radio
transmitters and the local oscillators in radio receivers. Typical LC oscillator
circuits are the Hartley, Colpitts and Clapp circuits.
The LC-tank VCO incorporated in this design is shown in Fig. 11. The bias
current, inductors, and device sizes are properly chosen such that it reaches optimal
performance. The resistor is used to slightly lift up the output common-mode level
of by 200 mV so as to relax the voltage headroom of the subsequent buffers
(realized as differential pairs). The table 4.2 shows the sizes of transistors.

36
Fig 4.5 Frequency VS Vcontrol

37
 Fig. 4.6 Schematic of LC Oscillator

M0-M1 M2-M3 R0 C1 L0-L1 IDC

12/0.5 12/0.18 75 2p 2.7n 300u
Table 4.2 Sizes of LC Oscillator

The LC oscillator has been simulated for Vcontrol vs frequency and the sensitivity
obtained is 900Mhz/1V and the result shown in Fig 4.5.

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 CHAPTER 5
CDR BLOCK

The final CDR block is as shown below.

Fig. 5.1 CDR Architechture

The simulation results for various architectures are as shown below:

39
5.1 Complete CDR Architecture with TSPC

Fig. 5.2 Simulation of CDR with TSPC

As the result shows, the complete architecture when simulated with TSPC based
PD is not able to reproduce the data at high data rate of 7Ghz.

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5.2 Complete CDR Architecture with CML

Fig. 5.3 Simulation of CDR with CML

The complete architecture when simulated with CML based PD faithfully

reproduces the data at 7Ghz working frequency with a dealy of 30 ps.

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5.3 Data Recovery with Noisy Data

Fig. 5.4 Successful Sampling of noisy data

Fig 5.5 Unsuccessful sampling of high noise data

42
As the results show, when a small noise of 100mV(p-p) is present in the circuit
then the data is recovered. If the noise is increased, then at 900mV(p-p), the circuit
is no longer able to reproduce the data correctly.

5.4 Eye-Diagrams- Jitter Comparison

Fig. 5.6 Eye Diagram of Ring Oscillator

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 Fig. 5.7 Eye-Diagram of CDR with LC Oscillator

A rectifier block is further introduced in the circuit to reduce jitter caused by

charge pump. The rectifier is a simple capacitor in feedback path of a unity gain
amplifier. In order to reduce the spikes in the charge pump output it was needed to
increase the capacitance. Bit increasing the capacitance reduced the swing of
Vcontrol. So the concept of miller capacitance was used.
Here the capacitance realized at the input side of the amplifier would be of a
large value which helped in reducing the jitter of the entire CDR Architecture as a
whole.

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 Fig. 5.8 Eye-Diagram of Modified CDR

The results of the eye diagrams are compared in the table and as can be seen the
jitter in architecture with LC oscillator and rectifier block is the least.
Eye Opening
Architecture Jitter
(Vertical)
CDR with Ring
26.844ps 1.5V
Oscillator(~4GHz)

CDR with LC 10.29ps 1.7V

Oscillator (~7GHz)
Improved CDR 2.295ps 1.5V
(~7GHz)
Table 5 Jitter Comparison

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 CHAPTER 6
CONCLUSION

The CDR system in this report is modelled and simulated in Cadence

Virtuoso in 180 nm technology node. This CDR with Alexander phase detector
allows binary phase comparison up to 7 Gb/s without causing dead zone. CML
based PD gives a better performance than TSPC based PD. Peaking technique is
utilized in CML latch to extend the bandwidth and maintain the signal integrity.
The LC oscillator provides better noise performance than ring oscillator as can be
seen from table 5. The regulator further improves the noise performance by
providing a clean voltage to the VCO, Providing superior performance with
reasonably low power consumption, this design demonstrates a promising future
for CMOS high-speed communications.
Future work involves designing a phase detector and charge pump that can
work at 10 GHz with a jitter of 1 ps.

46
 REFERENCES
[1] P. Yue and M. Rodwell, “mm-wave IC design: The transition from III-V to CMOS circuit techniques,
short course, RF and high speed CMOS,” in Proc. IEEE Compound Semiconductor Integrated Circuit
Symp. (CSICS), Nov. 2006.
[2] Y. M. Greshishchev and P. Schvan, “SiGe clock and data recovery IC with linear-type PLL for 10-
Gb/s SONET application,” IEEE J. Solid- State Circuits, vol. 35, no. 9, pp. 1353–1359, Sep. 2000.
[3] J. D. H. Alexander, “Clock recovery from random binary data,” Elec- tron. Lett., vol. 11, pp. 541–542,
Oct. 1975.
[4] C. R. Hogge, “A self-correcting clock recovery circuit,” J. Lightw. Techol., vol. 3, no. 12, pp. 1312–
1314, Dec. 1985.
[5] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear
phase detector,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 761–768, May 2001.
[6] H. Noguchi et al., “A 40-Gb/s CDR circuit with adaptive decision-point control based on eye-opening
monitor feedback,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2929–2938, Dec. 2008.
[7] Y. Amamiya et al., “A 40 Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for
optical transmission systems,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers,
Feb. 2009, pp. 358–359.
[8] 40 Gb/s and 100 Gb/s Ethernet Task Force, IEEE P802.3ba [Online]. Available:
http://www.ieee802.org/3/ba/index.html
[9] A. Pottbacker et al., “A Si bipolar phase and frequency detector for clock extraction up to 8 Gb/s,”
IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1747–1751, Dec. 1992.
[10] S. B. Anand and B. Razavi, “A 2.75 Gb/s CMOS clock recovery circuit with broad capture range,” in
Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2001, pp. 214–215.
[11] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary
phase/frequency detector,” IEEE J. Solid- State Circuits, vol. 38, no. 1, pp. 13–21, Jan. 2003.
[12] B. Razavi, Design of Integrated Circuits for Optical Communications. New York: McGraw-Hill,
2002.

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