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Multiplexer, Demultiplexer and Encoder With Simulation and RTL Schematic

Hey myself Junaid, contact me at [email protected] for any doubts regarding these. keep learning :)

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Junaid ahmed
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703 views

Multiplexer, Demultiplexer and Encoder With Simulation and RTL Schematic

Hey myself Junaid, contact me at [email protected] for any doubts regarding these. keep learning :)

Uploaded by

Junaid ahmed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 26

1.

MULTIPLEXER

 Aim: To design a 2x1 multiplexer using all modelling styles


 Software used: Xilinx.

1.1 MUX 2x1 using data flow modelling:


 Verilog program:

 RTL Schematic:

 Simulation result:

1
1.2 MUX 2x1 using structural modelling:
 Verilog program:

 RTL Schematic:

 Simulation result:

1.3 MUX 2x1 using behavioral modelling:

2
 Verilog program:

 RTL Schematic:

 Simulation result:

1.4 MUX 4x1 using data flow modelling:

3
 Verilog program:

 RTL Schematic:

 Simulation result:

1.5 MUX 4x1 using structural modelling:


 Verilog program:

4
 RTL Schematic:

 Simulation result:

1.6 MUX 4x1 using behavioral modelling:


 Verilog program:

5
 RTL Schematic:

 Simulation result:

1.7 MUX 4x1 using 2x1:


 Verilog program:

6
 RTL Schematic:

 Simulation result:

1.8 MUX 8x1 using data flow modelling:


 Verilog program:

7
 RTL Schematic:

 Simulation result:

1.9 MUX 8x1 using structural modelling:


 Verilog program:

8
 RTL Schematic:

 Simulation result:

9
1.10 MUX 8x1 using behavioral modelling:
 Verilog program:

 RTL Schematic:

 Simulation result:

10
1.11 MUX 8x1 using 4x1 and 2x1:
 Verilog program:

 RTL Schematic:

 Simulation result:

1.12 MUX 16x1 using 8x1 and 2x1:


 Verilog program:

 RTL Schematic:

 Simulation result:
2. DEMULTIPLEXER
2.1 DEMUX 1x2 using data flow modelling:
 Verilog program:

 RTL Schematic:

11
 Simulation result:

2.2 DEMUX 1x2 using structural modelling:


 Verilog program:

 RTL Schematic:

12
 Simulation result:

2.3 DEMUX 1x2 using behavioral modelling:


 Verilog program:

 RTL Schematic:

13
 Simulation result:

2.4 DEMUX 1x4 using data flow modelling:


 Verilog program:

14
 RTL Schematic:

 Simulation result:

2.5 DEMUX 1X4 using structural modelling:


 Verilog program:

15
 RTL Schematic:

 Simulation result:

2.6 DEMUX 1X4 using behavioral modelling:


 Verilog program:

16
 RTL Schematic:

 Simulation result:

2.7 DEMUX 1x8 using data flow modelling:


 Verilog program:

17
 RTL Schematic:

 Simulation result:

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2.8 DEMUX 1X8 using structural modelling:
 Verilog program:

 RTL Schematic:

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 Simulation result:

2.9 DEMUX 1X8 using behavioral modelling:


 Verilog program:

 RTL Schematic:

 Simulation result:

21
2.10 DEMUX 1x8 using 1x4:
 Verilog program:

 RTL Schematic:

 Simulation result:

3. ENCODER:
3.1 Encoder 4x2 using data flow modelling:
 Verilog program:

 RTL Schematic:

22
 Simulation result:

3.2. Encoder 4x2 using structural modelling:


 Verilog program:

23
 RTL Schematic:

 Simulation result:

3.3. Encoder 4x2 using behavioral modelling:


 Verilog program:

24
 RTL Schematic:

 Simulation result:

3.4 Encoder 8x3 using data flow modelling:


 Verilog program:

25
 RTL Schematic:

 Simulation result:

26

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