Floorplaning Guidelines

Macro/Memory placement

Mandatory

 NO memory rotation allowed. If the aspect ratio of the memory creates floorplan problems, it may be
possible to request a memory with different aspect ratio.
 NO abutting of memories on any sides allowed. A minimum distance of 0.7um (half the halo) must exist

Recommended

 Minimum distance between macros which are not abutted = 20u ; more if pin density is high.
 Vertical Channels: Minimum of 20u is recommended: 8u for halo/macroring/tap-cap cells + 10u for a buffers
 Increase distance for channels with macro pins facing from both directions
 Minimum distance between macros with no pins in the channel = min 6.9u (left/right/top/bottom). This
allows buffers in the channel
 However, it is recommended to use at least 9um top/bottom, otherwise the IO ring will not be fully created
and power to top/bottom channels will not be connected
 Minimum distance between macros and subchip (die) edge when there are no pins = 8.5u
(left/right/top/bottom)
 Increase distance when pins are present, to allow for routing and VDD/VSS
 Halo size around macros = 1.5u
 Align all macro edges between adjacent macros
 Add soft blockages between macros
 Make sure signal pins are clearing the isolation ring for route connection
 First check flylines i.e. check net connections from macro to macro and macro to standard cells.
 If there is more connection from macro to macro place those macros nearer to each other preferably nearer
to core boundaries.
 If input pin is connected to macro better to place nearer to that pin or pad.

Thin Memories

In Topaz, memories thinner than 52.92um may not get power connections to M9 for the VDDNWA and VDDAR
supplies. To work around this issue, the M8 pins can be extended by setting the variable "pnrVars(cfg,extendM8pin)"
to 1 in the "fp_subchip_floowplan.tcl" file before creating the floorplan. This will extend M8 pins left and right of the
thin memories to meet the 52.92um width requirement. Make sure the extension does not conflict or short adjacent
memories.

Note that the flow will generate an ERROR during floorplanning if Thin memories are found, and the
pnrVars(cfg,extendM8pin) variable is not set.

Clock Elements

 Review Clock Pin/Mux/Root Gaters placement

 Pre-place SSTM muxes and Clock gaters next to clock pins, and set FIXED state

A script to help find SSTM muxes and Clock gaters is available.

Reviews

 Review IO buffer locations for sufficient power supply and congestion

 Check for unassigned pins. They will be at the origin, and can be found in the pin editor
 Check that each memory has an Endcap ring
  Check that pins are facing towards the core, not to the subchip boundary
 Check that the vertical channels in-between memories have both, VDD and VSS, power stripes to power cells
in the channel

space btw macros are calcukated distance=(number of pins* pich)/(total number of available metals/2)

The formula to calculate spacing between two macro is (width+spacing x number of pins /vertical routing layers) +
spacing. It is better adding an additional spacing because you can avoid violation with the side of macros.

Tips for macro Placement

1. Place macros around chip periphery.

If you don’t have reasonable rationale to place the macro inside the core area, then place macros around the chip
periphery. Placing a macro inside the core can invite serious consequence during routing due to a lot of detour
routing, because macros are equal to a large obstacle for routing. Another advantage to placing the hard macros
around the core periphery is it's easier to supply power to them, and reduces the change of IR drop problems to
macros consuming high amounts of power.
2. Consider connections to fixed cells when placing macros.
When you decide macro position, you have to pay attention to connections to fixed elements such as I/O and
perplaced macros. Place macros near their associate fixed element. Check connections by displaying flight lines in
the GUI.
3. Orient macros to minimize distance between pins.
When you decide the orientation of macros, you also have to take account of pins positions and their connections.
4. Reserve enough room around macros.
For regular net routing and power grid, you have to reserve enough routing space around macros. In this case
estimating routing resources with precision is very important. Use the congestion map from trialRoute to identify
hot spots between macros and adjust their placement as needed.
5. Reduce open fields as much as possible.
Except for reserved routing resources, remove dead space to increase the area for random logic. Choosing different
aspect ratio (if that option is available) can eliminate open fields.
6. Reserve space for power grid.
The number of power routes required can change based on power consumption. You have to estimate the power
consumption and reserve enough room for the power grid. If you underestimate the space required for power
routing, you can encounter routing problems.

Power Planning

Total dynamic core current (mA)

= total dynamic core power / core voltage

= 236.2068mW / 1.08V
= 218.71 mA

Core PG ring width

= (Total dynamic core current)/ (No. of sides * maximum current density of the metal layer used (Jmax) for
PG ring)
=218.71 mA/(4*49.5 mA/μm)
~1.1 μm
Placement:

 Pre-placement Optimization optimizes the netlist before placement, HFNs are collapsed. It can also downsize
the cells.
 In-placement optimization re-optimizes the logic based on VR. This can perform cell sizing, cell moving, cell
bypassing, net splitting, gate duplication, buffer insertion, area recovery. Optimization performs iteration of
setup fixing, incremental timing and congestion driven placement.
 Post placement optimization before CTS performs netlist optimization with ideal clocks. It can fix setup, hold,
max trans/cap violations. It can do placement optimization based on global routing. It re does HFN synthesis.
 Post placement optimization after CTS optimizes timing with propagated clock. It tries to preserve clock
skew.

CTS

Multiple clocks-->synthesize seperately-->balance the skew-->optimize the clock tree

Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup
requirement with in the launch and capture timing path

The .ctstch file generated by FE is the easiest thing to start with. Then you may want to customize it by
allowing only certain buffers/inverters (as you mentioned), or using a NONDEFAULT rule for routing the
clock tree, using different values for insertion delay/skew/transition, etc. The test will be to see how timing
looks after your clock trees are in and you have done a postCTS optimization. If you are not meeting
timing, is it due to the clock tree? Should some of your clocks be grouped (balanced together)?

I would recommend using a double-width double-space NONDEFAULT rule if you have the room. This will
improve insertion delay and make the clock less vulnerable to noise. A lot of designers use only inverters
to build the tree. This helps with duty cycle. Another common thing is to limit the buffer/inverter list to just
3 or 4 buf/inv sizes. You may have to run CTS a few times with different settings to get the best results.
You'll also want to make sure that everything you intend to be a leaf cell is getting reached, and that you
exclude anything you don't want a clock tree built to. I believe the .ctstch file is created based on the SDC
constraints, but you can't always tell from those what the true intent of the clocking was.

Inorder to avoid duty cycle variation in clock we go for inverters instead buffers. if the duty cycle varies
obviously the effective clock period changes.so timing violations will be occured.

Difference between normal buffer and clock buffer:

Clock net is one of the High Fanout Net(HFN)s. The clock buffers are designed with some special property
like high drive strength and less delay. Clock buffers have equal rise and fall time. This prevents duty cycle
of clock signal from changing when it passes through a chain of clock buffers.

Normal buffers are designed with W/L ratio such that sum of rise time and fall time is minimum. They too
are designed for higher drive strength

Skew: The difference in the arrival of clock signal at the clock pin of different flops
Local Skew : Source and Destination flop insertion delay is called local skew.
Global Skew : Max insertion delay minus Min Insertion Delay is called Global Skew.
skew between two synchronous pins without considering logic relationship.

How do you optimize skew/insertion delays in CTS

 Better skew targets and insertion delay values provided while building the clocks.
 Choose appropriate tree structure – either based on clock buffers or clock inverters or mix of clock
buffers or clock inverters.
 For multi clock domain, group the clocks while building the clock tree so that skew is balanced
across the clocks.
(Inter clock skew analysis).

Latency: the delay from the clock definition point to the clock pin of the register"
Uncertainty : the amount of skew and the variation in the arrival clock edge. Pre CTS uncertainty is clock
skew and clock Jitter. After CTS we can have some margin of skew + Jitter
Jitter: The short-term variations of a signal with respect to its ideal position in time

After CTS hold slack should improve. Clock tree begins at .sdc defined clock source and ends at stop pins of flop.
There are two types of stop pins known as ignore pins and sync pins. ‘Don’t touch’ circuits and pins in front end (logic
synthesis) are treated as ‘ignore’ circuits or pins at back end (physical synthesis). ‘Ignore’ pins are ignored for timing
analysis. If clock is divided then separate skew analysis is necessary.

If clock is skewed intentionally to improve setup slack then it is known as useful skew.
Rigidity is the term coined in Astro to indicate the relaxation of constraints. Higher the rigidity tighter is the
constraints.

In Clock Tree Optimization (CTO) clock can be shielded so that noise is not coupled to other signals. But shielding
increases area by 12 to 15%. Since the clock signal is global in nature the same metal layer used for power routing is
used for clock also. CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment and HFN
synthesis. We try to improve setup slack in pre-placement, in placement and post placement optimization before
CTS stages while neglecting hold slack. In post placement optimization after CTS hold slack is improved. As a result of
CTS lot of buffers are added. Generally for 100k gates around 650 buffers are added.

1) ckECO -latency

2) ckECO -area (Reduces clock tree power by 30%)

3) ckECO -fixDRVOnly (Buffer transition fix after area reduction)

4) ckECO (General tree clean-up)

5) ckECO (General tree clean-up - with more buffers)

6) ckECO -localSkew

Route:
Global Route assigns nets to specific metal layers and global routing cells. Global route tries to avoid congested
global cells while minimizing detours. Global route also avoids pre-routed P/G, placement blockages and routing
blockages.
Track Assignment (TA) assigns each net to a specific track and actual metal traces are laid down by it. It tries to make
long, straight traces to avoid the number of vias. DRC is not followed in TA stage. TA operates on the entire design at
once.
Detail Routing tries to fix all DRC violations after track assignment using a fixed size small area known as “SBox”.
Detail route traverses the whole design box by box until entire routing pass is complete.
Search and Repair fixes remaining DRC violations through multiple iterative loops using progressively larger SBox
sizes.

Antenna

Increased net length can accumulate more charges while manufacturing of the device due to ionisation
process

Insert antenna diode

Cross talk

Switching of the signal in one net can interfere neigbouring net due to cross coupling capacitance.This
affect is known as cross talk. Cross talk may lead setup or hold voilation.

-Double spacing=>more spacing=>less capacitance=>less cross talk

-Multiple vias=>less resistance=>less RC delay
-Shielding=> constant cross coupling capacitance =>known value of crosstalk
-Buffer insertion=>boost the victim strength

Crosstalk in Signal Line:

Crosstalk is a capacitive and inductive interference caused by the noise voltage developed on signal
lines when nearby lines change state

It is a function of the separation between signal lines, the linear distance that signals lines run parallel
with each other. The faster edge rates of today's logic devices greatly increase the possibility of
coupling or crosstalk between signals. To maximize speed, crosstalk must be reduced to levels where
no extra time is required for the signal to stabilize. Signals such as clocks, that are highly sensitive to
crosstalk should be isolated by reference planes from signals on other layers and/or by extrawide line-
to-line spacing

Special Requirement for Crosstalk Avoidance:

I. Data buses : Crosstalk between buses tends to be data-patterns-sensitive and it is worse when
all addresses or data lines change in the same direction at the same time. Signals common to a
given bus can run next to other signals in the bus, but not with other buses or signals.
II. Memory address and data signals : A data-to-address-line cross-coupling may upset address
lines sufficiently to cause write signals to incorrect memory locations. Therefore, high-speed
memory address and data signals need to be isolated by reference planes and by extra-wide
line-to-line spacing from other signals, particularly other memory chip-selects, address line, and
data buses.
III. Clock signals and Strobes : To meet crosstalk limits, clock signals must be isolated and confined
between reference layers. Other signals must not be mixed with clocks. Clock signals on a given
layer must have extra spacing between lines. Clock signals of different frequencies must have
extra-wide spacing, as clock signals and other signals if they are to be mixed.

Design Issues for Noise:

I. Reduce coupling noise

II. Increase driver strength

 III. Increase spacing between wires or route signal lines alternately with power or ground.

IV. Constraint-driven routing

V. Reducing power supply noise

VI. Ensure that power grid is sized correctly for the load it is serving to reduce IR drop

VII. Add on-chip decoupling capacitance to reduce delta-I noise. With increasing use of dynamic circuits,
there is less NWELL capacitance on-chip.

VIII. When employing cores, one must be sensitive to the quality of the interconnects which will carry
signals between cores and the ASIC portion of the network

Approaches to Crosstalk Avoidance :

Analysis

Efficient mode for filtering and driver for physical design

Mixture of static/ dynamic analysis tools needed

Interconnect Planning

Present routing methodology increasingly inadequate

Mixture of planning & constrained synthesis needed

Efficient Noise metrics

Noise avoidance routing

Clocking - managing skew, interconnect vs. device variability

Buffer Insertion - needs to better integrated into design methodology

Use of design guidelines necessary in practice

Basic Approaches in Crosstalk Avoidance

 Segregation / Spacing / Ground Shielding

Grounded
Shields

Shielding
Segregation : Dividing many (noisy) and less(quiet) signal transition wire and merging group by
group.(use with shielding)

Spacing : the method that signal wire to shun each other, when signal net is close to each other
(routing channel is not wide)

Shielding : blocking signal line with ground line to minimize signal interference to the other
wire.(ground bounce occurs and must broaden the ground line)

 Net Ordering

Net ordering is used for minimize crosstalk-critical region between each lines. When, long line and long
line is close together, crosstalk between them is more larger than long line and short line. So, we must
change the permutation of track for minimizing crosstalk.

L L
S S

S S
S S

L L L L

L L S S

L L L L

 Layer Assignment

When using more than 3 layer in channel routing, adjacent signal wire in same layer results crosstalk.
For example, left figure makes more crosstalk than right.

Layer assignment problem is solved by integer linear programming or dynamic programming method.

Unodered net Ordered net

Layer1 Layer3
Layer2
 Pattern Routing

In global routing, global interconnection wires have more long and thick wire than local
interconnection wire.
Q 2
Q 1

Pattern routing method

Make wire pattern satisfying design specification.

Choose corresponding wire pattern.

Minimize total crosstalk. Q 3

Q 4
IR -Drop

IR drop is the drop in VDD voltage level due to current flows in the metal interconnect lines.

Static IR drop refers to the drop due to current flow when the circuit is at a steady state i.e. no inputs are switching.

Static In-Design Rail Analysis provides multiple analysis features: rail integrity checking, resistivity analysis,
static IR drop analysis, and static electromigration (EM) analysis. For example, users can do rail checking to
get connectivity and resistivity information. If there is high resistivity in the map, it can either be a
connection issue or a missing pad. A connection issue can be caused by unconnected cell instances,floating
geometries (disconnected wires and vias), and possible missing vias. Missing pads can be resulted from the
fact that the area is too far away from the supply voltage and a pad needs to be added

Dynamic IR drop refers to voltage drop due to currents flowing when the circuit is switching i.e.
performing some function. Dynamic IR drop is greater than statis IR drop since the current flowing in the
metal interconnect is greater than when the circuit is in a steady state.

In-Design Rail Analysis can minimize peak dynamic IR drop at a minimum decap insertion cost. This cost is
based on the available area for decap insertion and is measured so as to minimize the needed capacitance,
area and leakage. It first looks at the preplaced filler cells in the design and then virtually replaces all of
them with decap cells. The filler area is used as the candidate area for decap cell swapping. It considers
user-target peak reduction and leakage to reduce the number of inserted decap cells. When analysis is
complete, In-Design Rail Analysis provides suggestions for decap insertion, and an ECO file is generated.
With the tight integration between IC Compiler and PrimeRail, the ECO file can be used as an input to IC
Compiler which automatically inserts these new cells and places them while swapping out the existing filler
cells. The placed decap cells are guaranteed to be DRC clean.

Dynamic IR drop depends on the switching time of the logic, and is less dependent on the a clock period
Typically, high IR drop impact on clock networks causes hold-time violations, while IR drop on data path
signal nets causes setup-time violations.

Filler cells just continue the VDD and VSS rails.

Decoupling cells also have a capacitor in them between the two rails.

Using standard cells in place of fillers may also cause some extra routing congestion because the inputs of
each spare cell will need to be routed to ground. Also, note that decap cells have power leakage as well

Toggle Rate Requirements

The current toggle rates used in Dynamic IR analysis for Topaz are: 100% for clock/memories, and 30% for
all other signals.
There is a requirement from the customer that certain interfaces (excluding DFT-related ports/signals)
must use a 100% signal toggle rate. We need to update our Dynamic IR runs to include this new constraint,
i.e., set the toggle rate for all interface signals to 100%. Please follow the instructions below (section "How
to override the default toggle rate") to modify your Dynamic IR and include this new constraint.
What signals/instances should be at 100%
From each interface output flow, through the output buffer(s), to each output port.
From each input port, through the input buffer(s), to the interface flop.
For subchips with pass-thru or 1 flop (e.g., DORM in Sapir), all logic from input to output (e.g., buffers,
muxes, flops)
DFT-related signals should not be included, i.e. they should remain at default of 30%

What to Fix
 The current spec for Topaz is that the maximum Dynamic IR drop is 7.5% (of 0.9v. See the sign-off
spreadsheet). This is 67.5mV.
Any violation over 50mV (i.e., a drop of 117.5mV or more) must be fixed. If you can not find a way to fix it,
please bring it up for review asap
Any violation between 0mV and 50mV should be fixed. If the fix is too complicated, time consuming, or
otherwise perturbing timing, please bring it up for review. Santiago, Mahesh, and TI will help decide if
instead of fixing the violation, an “extra” timing margin can be applied to the violating instance.

When to defer the fix to the Full-Chip IR report

Due to the limited view of the Cover Cell at the subchip level, we may see higher IR drop at the subchip
level than at the full-chip level. Please apply the following guidelines when reviewing your violations:
If your violation is close to the subchip edge, and far away from VDD/VSS, we need to review full-chip IR to
see if it’s a real violation
If your violation is in an area far away form VDD/VSS because of having VDDAR/VDDNWA power on-top,
we need to review full-chip IR to see if it can be fixed by modifying the full-chip cover cell
Violations inside the subchip, close to VDD/VSS, are expected to be real and need to be fixed.

For Dynamic IR drop first u try to dec the strength for the non critical paths(not a good practice as this
might cause many timing violations). Best would be to put de cap cells but at the cost of more leakage and
area.

IR-Drop Solutions:
1. Reduce the current consumption of the cell
2. Add more supply voltage pads
3. Reduce the wire resistance
4. Use multiple power layers
Using more metal layers will reduce resistance of power network and hence IR drop.

5. Add decoupling capacitors

I. Decoupling capacitors acts as local charge storage and is helpful in mitigating the voltage drop at
supply points by providing charge. It reduces current drawn from power supply and Hence IR drop.
II. Decaps filter out current spikes resulting from simultaneous switching of signals.

Extraction :
Cell.index, laff, cell_lef ,fpcf ,pgFill.gdsii , gdsii ,def, final.v , CornerTable

Lef. Metal fill gdsii, gdsii, Top.def(covercell) , set COUPLE_TO_GND: No -- > SBPF (netlist)

Timing:
Top netlist , technology, constraints , Parasitics netlist.

DRC check :

.gdsii -> .laff , metalStack, tech file,

LVS Check:

Netlist + laff -> gdsii(layout) , schemetic Topcell

setup equation
Tclk > Tclktoq + Tlogic + Tsetup + Tskew + Tjitter

high vt --> low vt

delay high --> delay low

hold equation
Tclktoq + Tlogic - Tskew > Thold

key things to note from above equations

a) once the silicon comes back , if u have setup time problem , u can increase the clock period (Tclk) to fix it ,
whereas if u have hold time problem , its a more serious problem and u will need a new metal fix tapeout .

b) PLL jitter (Tjitter ) is not used in holdtime equation , since hold time violation is based on same clock edge .
(whereas setup time vioation depends on 2 consecutive clock edges)
c) above equaitons have clock skew in pessimistic directions . U can play around with clock skews to get extra margin
by skewing them in favourable direction to decrease violation .

Q: If we send data from one clock(say slow clk) domain to other clock domain(say fast clk), then what kind of
constraint we have to give while doing synthesis or STA. Please refer the diagram given here.
There is a general guideline that when ever the data crossing the clk domain in your design, give cosntraints
set_false_path -from clk1 -to clk2.

Ans: if 2 clocks are from two different sources then they are asynchronous, that means they have different
jitter values,this value is included in the uncertainity.. so they dont have the same staring edges.so we will
keep them as the false paths we need to check them by placing the synchronizers in between them
it will be done in actual process

Ans1: I think we need to set_falsepath command in this case, becasue doent matter how much delay between
different clock domains it takes we need to specify that path as false path.
The paths between the clock domains we remove the timing constraints, mean we have to set false path only, if u
set multicycle(2) path command, then tool again try to optimize the path for 2 clock cycles, but we dont want to
optimize at all

Ans2: So far we are clear that if they are from same source and have a deterministic relationship, we can time them
in STA, and make sure that there is no setup/hold violation on the data transfer.

But, if they are not coming from same clock source, and we infer that these clock domains are asynchronous, we
should not blindly false_path them.
If its a async crossing,
a) there should be either a synchronizer on this path ( I can see combo cloud in figure, so this is not a part of
synchronizer crossing for sure),
b) or should be a data path qualified by a control path which is synced separately.
c) or should be a static signal, which only changes once in a while in manner that its new value is not important for a
few cycles, while it settles down to correct value.
What is false path? Give an example?
Ans: The paths in the circuit, which are never exercised during normal circuit operation for any set of inputs.

Apath can exist between two multiplexed logic blocks that are never selected at the same time, so that path is not
valid for timing analysis.

Example: give MUX example

What are multi-cycle paths? Give example.
Ans: Multi-cycle paths are paths between registers that take more than one clock cycle to become stable

An input delay is specifying an arrival time at an input port relative to a clock edge

An output delay represents an external timing path from an output port to a register. The maximum output delay
value should be equal to the length of the longest path to the register data pin, plus the setup time of the register.
The minimum output delay value should be equal to the length of the shortest path to the register data pin, minus
the hold time

What is metastability? When/why it will occur?Different ways to avoid this?

Metastable state: A un-known state in between the two logical known states.This will happen if the O/P cap is not
allowed to charge/discharge fully to the required logical levels.
One of the cases is: If there is a setup time violation, metastability will occur,To avoid this, a series of FFs is used
(normally 2 or 3) which will remove the intermediate states.

What is Latchup ?

The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a PNP and an NPN
transistor stacked next to each other. During a latchup when one of the transistors is conducting, the other one
begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and
some current flows through it - which usually means until a power-down. The SCR parasitic structure is formed as a
part of the totem-pole PMOS and NMOS transistor pair on the output drivers of the gates.

What is body effect? Write mathematical expression? Is it due to parallel or serial connection of MOSFETs?
Ans1: Increase in Vt (threshold voltage), due to increase in Vs (voltage at source), is called as body effect. It is due to
serial connection.

Die size calculation :

Required Inputs:

Technology used eg. 0.18 Micron etc

Total Number of standard cells
One standard cell area
Number of IO pads
Pad height
Core utilization allowed eg.0.7 (i.e.70 %)

Calculations:
Total standard cell area = no. of standard cells * one standard cell area (Alternatively this can be directly obtained
from the DC area report).

Core size = Standard cell area / Utilization (Assuming there are no hard macros; If there are then add this also )
= X um * Y um.

Die area = [Core width + PG ring width + core offset + 2 * pad height ] *
[Core height + PG ring width + core offset + 2 * pad height ]
= A um * B um
=AB um2

What happens to delay if you increase load capacitance?

delay increases.

What happens to delay if we include a resistance at the output of a CMOS circuit?

Increases. (RC delay)

What are the limitations in increasing the power supply to reduce delay?
The delay can be reduced by increasing the power supply but if we do so the heating effect comes because of
excessive power, to compensate this we have to increase the die size which is not practical.

How does Resistance of the metal lines vary with increasing thickness and increasing length?
R = ( *l) / A.

What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus?
In the serially connected NMOS logic the input capacitance of each gate shares the charge with the load capacitance
by which the logical levels drastically mismatched than that of the desired once. To eliminate this load capacitance
must be very high compared to the input capacitance of the gates (approximately 10 times).

Why do we gradually increase the size of inverters in buffer design when trying to drive a high capacitive load? Why
not give the output of a circuit to one large inverter?

We cannot use a big inverter to drive a large output capacitance because, who will drive the big inverter? The signal
that has to drive the output cap will now see a larger gate capacitance of the BIG inverter.So this results in slow raise
or fall times .A unit inverter can drive approximately an inverter thats 4 times bigger in size. So say we need to drive
a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64 so that each inverter sees a same ratio of
output to input cap. This is the prime reason behind going for progressive sizing.

What is slack?
'Slack' is the amount of time you have that is measured from when an event 'actually happens' and when it 'must
happen'.. The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually
happen'.
When something 'must happen' can also be called a 'deadline' so another definition of slack would be the time from
when something 'actually happens' (call this Tact) until the deadline (call this Tdead).
Slack = Tdead - Tact.
Negative slack implies that the 'actually happen' time is later than the 'deadline' time...in other words it's too late
and a timing violation....you have a timing problem that needs some attention.

What is glitch? What causes it (explain with waveform)? How to overcome it?
The following figure shows a synchronous alternative to the gated clock using a data path. The flip-flop is clocked at
every clock cycle and the data path is controlled by an enable. When the enable is Low, the multiplexer feeds the
output of the register back on itself. When the enable is High, new data is fed to the flip-flop and the register
changes its state

What is difference between setup and hold time. The interviewer was looking for one specific reason , and its really a
good answer too..The hint is hold time doesn't depend on clock, why is it so...?
Setup violations are related to two edges of clock, i mean you can vary the clock frequency to correct setup violation.
But for hold time, you are only concerned with one edge and does not basically depend on clock frequency.

Consider two similar processors, one with a clock skew of 100ps and other with a clock skew of 50ps. Which one is
likely to have more power? Why?
Clock skew of 50ps is more likely to have clock power. This is because it is likely that low-skew processor has better
designed clock tree with more powerful and number of buffers and overheads to make skew better

Metal ECO :

source FF/vars.tcl
source FF/procs.tcl
source ../flow/procs/eco_procs.tcl

 Identify the cell to be added and select the equalent fill_eco cells near to the term that needs to be fixed.
 For example if you want to add EEN_BUF_2 at hier1/hier2/A

meco_select_fillers_matching_cell EEN_BUF_2

 capture the LLX and LLY of nearest fill_eco cell that you have identified near hier1/hier2 instance and also
the name of fill_eco instance

setEcoMode -spreadInverter true

setEcoMode -honorDontTouch false
setEcoMode -honorDontUse false
setEcoMode -prefixName ECO_METAL_ECO
setEcoMode -refinePlace false
setEcoMode -updateTiming false

ecoAddRepeater -term hier1/hier2/A -cell EEN_BUF -loc x y ( llx and lly of nearest fill eco cell )
setEcoMode -reset

 Delete the fill eco cell and legalize the newly added instance. ( see below command )

meco_replace_filler_with_instance <fill_eco_instance_name> <instance that is added by above ecoAddRepeater>

 if you find any gaps near any of the newly added instances, perform cpd_insert_filler

 perform the eco route.

ACC eco :

/data/F781985/top/FN-1/12Jun201/anilk/FN1_P1_D1/edi_route/dump/dump_max/final_ports_with_slack (9 ports
)
/data/F781985/top/FN-1/12Jun201/anilk/FN1_P1_D1/edi_route/dump/dump_min/final_ports_with_slack ( 50 ports
)

In max case few ports are there which might present in min case too , but need to fix only ones based on the
max case magnitude .
Max case delay Table

< -25ps -- > one EEN_BUF_2

> -25ps  two EEN_BUF_2

Min case delay Table

< -12ps -- > one EEN_BUF_2

> -12ps  two EEN_BUF_2

Decoupling Capacitor Insertion

One of the most widely used techniques to solve power supply noise is to add decoupling capacitance
(decap) cells in the affected areas. It is very helpful if the analysis tool can make some suggestions where
decoupling capacitors can be used more efficiently to minimize power supply noise. It will be even better if
the tool can do something further than just the analysis, such as placing the decap cells to achieve a certain
user-predefined percentage of voltage drop reduction.As shown in Figure 13-2, PrimeRail is capable of
maximizing voltage drop reduction with minimum cost in terms of available decap resources. The tool first
looks at the available filler cells in the design and then virtually replaces them with decap cells. The tool
considers the cell's capacitance value versus leakage as a cost function to meet the user-provided target
reduction. It can take several iterations during the analysis to find the optimal solution. When the analysis is
complete, PrimeRail provides suggestions for decoupling capacitor insertion, and you can choose which
suggestion is the best fit and perform the actual decoupling capacitor insertion.

Figure 13-2 Examples for Inserting Decoupling Capacitors

When the insertion is complete, rerun rail analysis to verify the insertion results. You can also examine the
inserted decap cells by displaying the decap density map.

Note that in PrimeRail, inserting a decap cell is not effective in the following cases:

 The power and ground network is not properly routed; that is, some instances are “isolated” from the
rest of the network. The effective resistance from the ideal voltage source to such instances is so high
that the dynamic voltage drop is dominated by large resistance. In this case solving the voltage drop
problem requires the unrealistically large capacitance in order to reduce the voltage drop.
 The power and ground network is close to ideal; that is, there is a very small effective parasitic
resistance. It usually happens on a very conservative power and ground net design or flip-chip
packaging. The dynamic voltage drop is dominated by a large peak inductance. To solve this
problem, reduce the peak current instead of adding more capacitors.
 The inductive noise is a dominant factor in the dynamic voltage drop flow. In this case the number of
affordable decoupling capacitors inserted is much less than what is needed to reduce the noise
effectively.

It is also important to know the following aspects of this feature so that their expectation is set correctly:

 The decoupling capacitor insertion flow in PrimeRail works at the block level. This means that the
tool will not dive into a soft macro to perform decap insertion.
 Because the Prime-Rail tool is used for sign-off, the decap insertion flow is expected to be used as
part of the ECO flow.
 PrimeRail does not generate any ECO file but can insert decoupling capacitors within its
environment.

Decap Insertion Flow

Figure 13-3 illustrates the flow of inserting decoupling capacitors in PrimeRail.

Figure 13-3 Decoupling Capacitor Insertion Flow

The following are the known assumptions in the PrimeRail decap insertion flow.
  During the decap insertion flow, it is recommended that you do not include any packaging in the
package file or the tap file. Because package parasitics can introduce oscillation in voltage drop
waveforms, inserting decoupling capacitance cells might not be efficient to reduce the magnitude of
the oscillation.The Decap Insertion dialog box accepts a list of cell master names, separated by a
comma (,) or a white space. Wildcard usage is supported. Decap insertion can be performed only on
a net basis, which means that if you want to insert decap cells for multiple power and ground nets,
you have to run the decap insertion flow for each power and ground network separately.After
running instantiation, you must save the Milkyway database before exiting from PrimeRail.

Design Requirement

In addition to the requirement of a normal dynamic analysis, you need to prepare the following information
specifically for performing decoupling capacitor insertion in PrimeRail:

 A FRAM view for filler and decap cells.

 The SPICE .subckt file and model information for decap cells for the library characterization
purpose.
 A design that has filler cells added by IC Compiler. If it is a multiple-VDD design, you can consider
decap insertion by area.

If you do not have the .subckt information for the decap cells, you must provide the capacitance value. This
is the minimum requirement because a dummy .subckt file can be created using that value. If you want to
define the DC leakage in addition to the decap value, you can add one resistor connected from vdd to vss,
where R = Vdd / leakage_current.The following is an example of such a dummy .subckt file:

.subckt decap1 vdd vss

C_dcap1 vdd vss 10f
R_leak vdd vss 1.38e9
.ends

Before Insertion—Finding Peak Voltage Drops

Before you insert a decap cell in a design, you need to complete the following steps:

1. Add fillers to the design by using any place and route tools, such as IC Compiler.

If you are doing placement and routing in IC Compiler, the command used to insert filler cells is
insert_stdcell_filler. For more information about this command, see the command man
pages or the IC Compiler documentation.

2. Run pgLibCharacterize or pgPreCharacterize to characterize intrinsic capacitance and

leakage current for filler and decap cells in PrimeRail.

Capacitance values for decap cells are needed and can be characterized in PrimeRail. Besides
intrinsic capacitances, the leakage current (which is optional) can also be characterized for leakage
consideration as a cost function during the decap analysis. Run pgLibCharacterize with the
Gate Intrinsic Parasitic and Filler Cell Leakage options. Note that for these filler and decap cells, the
.subckt ports usually contain only power and ground ports; it does not make sense to select any other
options, like Current Waveform during library characterization in the Library Characterization dialog
box.Also, make sure you specify the same PVT information for decap characterization as you will be
using it for analysis. Characterizing decap cells with a different temperature than the one used during
analysis will result in incorrect analysis results. When characterization is complete, write out the
intrinsic parasitic and filler cell leakage information to an output file and verify if it has the correct
PVT information and the characterized data.
 Note:

The SPICE netlist for filler and decap cells is required for characterizing leakage currents.

If you run the pgLibCharacterize command, the characterization result is automatically saved
to the file called filler.leakage. When characterization is done, the tool automatically links the
characterization to the library.

If you run the pgPreCharacterize command, the characterization result file is saved to a user-
specified file, which you need to manually link to the library by using the pgLinkCharacterize
command.

For more information about library characterization, see Chapter 6, “Library Characterization for
Cell-Level Dynamic Analysis” in this user guide.

3. When filler cells are added to the design, regenerate the rail database and extract the parasitic
information. This includes the following steps:
a. Run poPurgeRail to remove the existing rail database.
b. Run poCalculatePower to regenerate the power database and current waveforms at
power ground ports of the standard cells.

For more information, see “Calculating Power and Current Waveforms”.

c. Rerun power and ground net extraction with filler cell port instances with the
poExtractPGParasitics command.

Performing power and ground net extraction in the decoupling capacitor insertion flow is the
same as in any normal cell-level dynamic analysis flow. The only difference is you need to
define the poIncludeFiller switch before running poExtractPGParasitics. By
default, filler cells are ignored for any kind of analysis. You need to define the
poIncludeFiller switch to ensure the power and ground ports of the filler cells are
extracted as part of the parasitic network.

define poIncludeFiller 1

For more information about running extraction, see “Extracting Power and Ground
Parasitics” in this user guide.

d. When all the previous steps discussed in this section are finished, run poRailAnalysis to
perform rail analysis. Or, you can perform rail analysis with the pgDecapInsertion
command when inserting decoupling capacitors.

Analyzing Decap Cell Replacements

PrimeRail is capable of analyzing which filler cells are to be replaced by decap cells before the replacement
is actually done. The tool iterates through different decap replacements until the user-defined target is met
and runs rail analysis to verify the result. During the iteration process, the tool prints multiple DECAP
messages that give detailed information about the virtual replacements. Based on this information you can
choose which iteration to instantiate.

Considering Leakage Current

Before invoking the pgDecapInsertion command, use the LEAKAGE_FACTOR switch to specify a
cost function which determines the balance between decoupling capacitances versus leakage currents, like
define LEAKAGE_FACTOR 0.5

The following formula expresses the cost function calculation in PrimeRail:

(1.0-leakage_factor) x total_decap_cap + leakage_factor x

total_decap_leakage

Set LEAKAGE_FACTOR within [0.0, 1.0]. Otherwise the tool resets the value to 0.0. The objective of
decap insertion is to minimize the voltage drop value using the minimum cost.

By default, LEAKAGE_FACTOR is “0.0” and this means the cost function is to consider only the
capacitance values associated with the decap cells. The larger the value of LEAKAGE_FACTOR is, the
greater the effect of leakage current is in cost function calculation. When LEAKAGE_FACTOR is set to
1.0, the cost function is the total leakage current of decap cells.

For a value between 0.0 and 1.0, the cost function is a weighted sum of capacitance and leakage current.
You can adjust the value between total capacitance and total leakage as necessary.

Note:

When using the LEAKAGE_FACTOR switch, be sure not to define PWL current waveforms in the user-
defined elements file for decap cells during decap insertion flow. The tool is unable to distinguish between
PWL tables inserted by the user-defined elements file and PWL leakages inserted during decap insertion
flow. As a result, the overlapping PWL tables for the same decap cell master (or instance) will be ignored.

Tips

The following tips are useful in the decap insertion flow:

 Use axgListSummary to write out the design’s master cell information.

 Make a note of peak voltage information for some top cell instances (like 4 to 5). If the peak happens
in different areas, the cell instances need to be chosen from both locations.
 Run pgMap to display voltage drop map and also save the voltage waveform information.
 Record the reported core and effective capacitance values during rail analysis.

Analyzing Filler Cell Replacements

To analyze filler cell replacements before actual inserting the decap cells,

1. Enter pgDecapInsertion or choose Cell-level Analysis > Optimization – Decap Insertion.

The Decap Insertion dialog box opens, as shown in Figure 13-4.

Figure 13-4 Decap Insertion Dialog Box

2. Enter the names of the filler cell masters to be replaced with decap cell masters. Use a comma (,) or a
space to separate master names.

Note that the filler cell masters must be placed or routed in IC Compiler. For more information, see
step 1 in “Before Insertion—Finding Peak Voltage Drops”.

3. Enter the names of the decap cell masters used to replace filler cells. Use a comma (,) or a space to
separate master names.
4. Enter the name of the power or ground net to be analyzed. You can analyze only one net at a time.

The name must be consistent with the power or ground net name specified in the P/G Rail Analysis
dialog box.

5. Specify the percentage of reduction you want the decap insertion flow to meet.
6. Select Re-Run Rail Analysis if you want to rerun the rail analysis to generate a reference voltage
drop value. By default, this option is off.
7. Select the insertion mode.
o Analysis only – When selected, PrimeRail uses iterations to determine which filler cells can
be replaced with decap cells to satisfy the preset target, and it performs rail analysis to verify
the result. The decap cell to be replaced will have the same or a smaller footprint than the
filler cell. PrimeRail automatically determines which decap cells can be used for replacing
certain filler cells. However, the cell instantiation does not actually happen in this mode. That
is, the filler cells are not actually replaced with decap cells; it is more like a virtual decap cell
replacement.

During analysis PrimeRail iterates among different decap replacements until the target is met.
The tool prints the messages to the log file to reflect the iterative process, with the prefix
DECAP.

In this mode PrimeRail does not automatically replace decap cells using the last iteration.
Instead it gives you the option of deciding which iteration to instantiate.

Iteration Example:

DECAP: After inserting all filler cells to design, the voltage

drop
DECAP: reduction is 13.796% (328.634 mV -> 283.295 mV),
which is less than user target 30%
DECAP: Decap insertion is not effective for reducing voltage
 drop
DECAP: decap insertion analysis succeeded

Explanation:

As discussed earlier, at first attempt the tool will replace all the filler cells to see the
maximum voltage drop reduction. In this example, the target reduction is too high or the
decap resource is not enough; even all the filler cells are replaced. The method of simply
inserting decap cells cannot solve the voltage drop problem. PrimeRail will not run further to
make the iterations to meet this target.

Iteration Example:

DECAP: After insert all filler cell to design, the voltage

drop
DECAP: reduction is 40%, which is greater than user target 10%
DECAP: Will reduce the amount of cap to meet target.

Explanation:

The decap resource is enough to solve the voltage drop problem and the preset target
reduction can be met. PrimeRail will use the decap resource as less as possible to meet the
target.

o Instantiate Only: When selected, PrimeRail instantiates the decap cell replacement. For more
information, see “Instantiating Decoupling Capacitors”.

Note:

You need to run the “Analysis Only” mode first so that PrimeRail can use the
iterations to determine which filler cells are to be replaced in order to meet the target
for what-if rail analysis.

8. Click OK or Apply.

Instantiating Decoupling Capacitors

When virtual decap cell replacement is done in the Analysis Only insertion mode (pgDecapInsertion),
you can choose which iteration to instantiate based on the DECAP message printed during decap cell
replacement.

After instantiation is done, be sure to save the cell before closing PrimeRail. Otherwise PrimeRail will not
save the instantiation result (or decap replacement) in the Milkyway database.

To instantiate decoupling capacitors,

1. Enter pgDecapInsertion to open the Decap Insertion dialog box (see Figure 13-4).
2. Select Instantiate Only as the insertion mode and specify the number of iterations to be used. This
option lets you decide which decap insertion pattern is instantiated (according to the iteration
numbers shown as messages in the log file during the Analysis Only mode).
3. Specify other options as necessary.
4. Click OK or Apply.

After instantiation is done, a message is printed to the log file:

DECAP: replace cell xofiller!FILL1!1 HNId 2330 from master FILL1 to
master FILLDCAP1
DECAP: replace cell xofiller!FILL1!2 HNId 2331 from master FILL1 to
master FILLDCAP1
DECAP: replace cell xofiller!FILL1!3 HNId 2332 from master FILL1 to
master FILLDCAP1
-----more messages in PR_LOG_DETAIL/PrimeRail.log.03_14_14_13.decap-----
DECAP: total 817 filler cell instances are replaced during decap
instantiation
DECAP: decap insertion instantiation succeeded

A detailed message is saved to the PR_LOG_DETAIL directory. In the message, the tool prints out the filler
cell instance name, the filler cell master name, and the replacement decap cell master name.

Verifying Insertion Results

You can quickly check the status (master cells count) of decap and filler cells with the
axgListPRSummary command. To display the decap map and the voltage drop map, run pgMap to see
the improvement on voltage drop effects.If you want to verify the rail analysis result, run aprPGConnect
on the newly added cells and poPurgeRail to purge the RAIL view. Then rerun dynamic analysis,
including poExtractPGParasitics, poCalculatePower, and poRailAnalysis.When decap
insertion is done, run DRC check in your place and route tool to make sure no violation exists in the design.
PrimeRail does not perform any DRC check.

Displaying Decap Density Maps

You can display a decap density map to check for the decoupling capacitors used in the design.

When displaying a decoupling capacitance map, the tool draws the following types of decoupling capacitors
on the map:

 Node capacitors on the power and ground nets

 Intrinsic capacitors for the cell instances
 Capacitors inserted through the user-defined elements file

To display a decoupling capacitance density map,

1. Enter pgMap in the command window or choose Cell-level Analysis > Display – Display Cell-level
Maps.
2. In the Display Map dialog box that appears (see Figure 13-6), select which analysis results you want
to display from the Results list.

When done, click the Load button to load the data to memory. You must load the data before
displaying a map. Click Remove to remove the data.

3. In the Map Options section, select Decap from the pull-down menu to display a decoupling
capacitance density map.
o Map Configuration – Specify additional options for map display in the Map Configuration
dialog box that appears.

Color Configuration – Define the color of each step to be shown on the map in the Display
Color Setup dialog box that appears.

o Density Mode – Enter the dimension of the window to display the map. You can display the
decoupling capacitance map only on a window basis.
 4. Display Options – Select the options related to the decoupling capacitance map.
o Show Text – Show decoupling capacitances on the map.
o Pads – Highlight the pads used as ideal voltage sources in rail analysis.
o Legend – Display the upper and lower bound values of the metal and via layers in the map.
Click Select Layer to choose the layer whose upper and lower bound values are to be shown
in the map.
o Violations In Red – Indicate violations in red on the map.
o Peak Position In Blink – Show a blinking rectangle where the maximum value is located.
o With Solid Fill Pattern as Default – Draw the map with the shapes filled with a solid color.
o Floating Metals In Grey – Show floating metals on the map.
5. Click OK or Apply in the Display Map dialog box. The tool displays the results in the cell editing
window.

Querying Decap Values by Area

When the decoupling capacitance density map is displayed, you can check for the decoupling capacitance
values by area for the design. To do this, click Query at the top of the Display Map dialog box and then click
a spot in the cell editing window. PrimeRail writes the values to the log and the command window.

The following is an example of querying decoupling capacitance values:

[ Decap map] - area query

Map = Decap
--------------------------------
Node 3508: layer = metal1, bBox = (120.400 249.740) (120.760
250.800)
Decap Value = 0.000792
Node 3509: layer = metal1, bBox = (120.400 247.330) (120.760
249.740)
Decap Value = 0.000426
Node 6559: layer = metal1, bBox = (121.400 249.740) (121.800
250.800)
Decap Value = 0.0504
---------------------------------------------------
Total cap under selected area = 0.0516 pF

Crosstalk Vs Timing Violations

If the aggressor and victim are moving in the same direction, the victim net switches faster. This
may lead to hold violation.

There will be a setup violation if both the aggressor and viction are switching in different direction.
(In this case, there is a crosstalk induced delay as the victim net switches slowly)

Its bcoz of coupling capacitance between them....

Here when victim switches in same direction with aggressor then victim signal speeds up leading
it to cause HOLD VIOLATION in SIGNAL PATH.....
if it is a clock path then it causes SETUP VIOLATION.... if the net speedup occurs in the (capture)
clock path, the clocks will be skewed and could lead to a setup violation

When the switching windows of the aggressor and victim nets overlap and the nets switch in
opposite directions, crosstalk will increase the delay of the victim net, which may result in setup
violations. When the nets switch in the same directions, crosstalk will reduce the delay of the
victim net, which may result in hold violations

if the victim is transitioning very slowly. It can happen the aggressor produces such a
bump on the victim that we have a double switching