CML Microcircuits

CMX808A
Family Radio CTCSS ‘Type 2’
COMMUNICATION SEMICONDUCTORS Encoder and Decoder
D/808A/6 September 2003

1.0 Features
• Unique CTCSS ‘Type 2’ Operation • High Performance Encode/Decode
• Fast Decode on all Tones (140ms) • Flexible Multiple Decode Options
• Tones from 60Hz to 251Hz • Sub-Audio Tone Rejection Filter
• Tone Cloning • 48 Programmable CTCSS Tones
• Low Power Operation (1.3mA at 3.0V) • Compact 20-pin TSSOP Package

Applications

• Family Radio Service

(FRS) Handportables
• Amateur Radio
Equipment
• General Mobile Radio
Service (GMRS)
• Short Range
Business Radio

1.1 Brief Description

This device is a unique product for the designer of family radio transceivers. Offering leading edge
performance while also being highly cost effective. The device is simple to interface to a host of
µControllers via the serial programming interface. A full range of 48 tones can be generated and detected
by the device. The decode time has been vastly improved from that offered by other solutions. Fast
response and de-response gives the user of a family radio transceiver faster switching times and a
reduction in the annoying squelch tail often found in CTCSS based systems. The device has very low
power consumption operating at a minimum of 3.0V.

A unique feature of the device is its ability to look for 7 different CTCSS codes simultaneously. This allows
FRS designers to offer equipment which can look for personal, family or open channel codes at the same
time. For example a soccer team coach can call each of the 11 players individually or the team as a
group. Codes can be used as Paging codes, open chat mode codes as well as personal and family
codes. These features allow FRS designers to differentiate their products from that of the competition in
unique ways to gain market share in this highly competitive application. The CMX808A opens the way to
rapid development of new family radio applications.

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

CONTENTS
Section Page

1.0 Features ................................................................................................ 1

1.2 Block Diagram .................................................................................... 3

1.3 Signal List ............................................................................................ 4

1.4 External Components ..................................................................... 6

1.5 General Description ......................................................................... 7

1.5.1 Software Description ................................................................. 7

1.6 Application Notes ........................................................................... 14

1.6.1 General...................................................................................... 14
1.6.2 Transmitter ............................................................................... 14
1.6.3 Receiver (Decode).................................................................... 14
1.6.4 Tx Tone Table........................................................................... 15
1.6.5 Rx Tone Table........................................................................... 16

1.7 Performance Specification ......................................................... 17

1.7.1 Electrical Performance ............................................................ 17
1.7.2 Packaging ................................................................................. 21

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1.2 Block Diagram

Figure 1 Block Diagram

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

1.3 Signal List

Package Signal Description

E3 P4

Pin No. Pin No. Name Type

1 1 XTALN O/P The inverted output of the on-chip oscillator.

2 2 XTAL/CLOCK I/P The input to the on-chip oscillator, for external

Xtal circuit or clock.

3 3 SERIAL CLOCK I/P The "C-BUS" serial clock input. This clock,
produced by the µController, is used for transfer
timing of commands and data to and from the
device. See "C-BUS" Timing Diagram (Figure
4).

4 4 COMMAND DATA I/P The "C-BUS" serial data input from the
µController. Data is loaded into this device in
8-bit bytes, MSB (D7) first, and LSB (D0) last,
synchronised to the SERIAL CLOCK. See
"C-BUS" Timing Diagram (Figure 4).

5 5 REPLY DATA O/P The "C-BUS" serial data output to the

µController. The transmission of REPLY DATA
bytes is synchronised to the SERIAL CLOCK
under the control of the CSN input. This 3-state
output is held at high impedance when not
sending data to the µController. See "C-BUS"
Timing Diagram (Figure 4).

6 6 CSN I/P The "C-BUS" data loading control function: this

input is provided by the µController. Data
transfer sequences are initiated, completed or
aborted by the CSN signal. See "C-BUS"
Timing Diagram (Figure 4).

7 7 IRQN O/P This output indicates an interrupt condition to

the µController by going to a logic "0". This is a
"wire-ORable" output, enabling the connection
of up to 8 peripherals to 1 interrupt port on the
µController. This pin has a low impedance
pulldown to logic "0" when active and a high-
impedance when inactive. An external pullup
resistor is required.

An interrupt is effective if not masked out by the

IRQ MASK (bit 0 in the SUB-AUDIO CONTROL
register $80).

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1.3 Signal List (continued)

Package Signal Description

E3 P4

Pin No. Pin No. Name Type

8 8 NC ) No internal connection. Do not make

9 NC ) any connection to these pins.

9 10 A/D CAP O/P An internal reference voltage for the A to D,

decoupled to VSS by an external capacitor.

11 NC No internal connection. Do not make any

connection to this pin.

10 12 Vss Power The negative supply rail (ground).

11 13 VBIAS O/P A bias line for the internal circuitry, held at ½

VDD. This pin must be decoupled by a
capacitor mounted close to the device pins.

12 14 RX AMP IN I/P The inverting input to the Rx input amplifier.

13 15 RX AMP OUT O/P The output of the Rx input amplifier and the
input to the audio filter section.

14 16 RX AUDIO OUT O/P Output of the Rx audio filter section.

17 NC No internal connection. Do not make any

connection to this pin.

15 18 TX AUDIO IN I/P Input to the Tx audio filter section.

16 19 TX AUDIO OUT O/P Output of the Tx audio filter section.

17 20 VOLUME IN I/P Input to the audio volume control.

18 21 TX SUB AUDIO OUT O/P Output of the CTCSS tone generator.

19 22 VOLUME OUT O/P Output of the audio volume control.

23 NC No internal connection. Do not make any

connection to this pin.

20 24 VDD Power The positive supply rail. Levels and voltages

are dependent upon this supply. This pin
should be decoupled to VSS by a capacitor.

Notes: I/P = Input

O/P = Output

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

1.4 External Components

C1 22pF ±20% R1 1MΩ ±5%

C2 22pF ±20% R2 22kΩ ±10%
C3 0.1µF ±20% R3 100kΩ ±10%
C4 0.1µF ±20% R4 Note 1 ±10%
C5 100pF ±20%
C6 0.1µF ±20%
C7 Note 1 ±20%
C8 0.1µF ±20% X1 4.0MHz ±100ppm

Note: 1. R3, R4, C5 and C7 form the gain components for the Rx Input Amplifier. R4 should be
chosen as required by the signal level, using the following formula:

R3
Gain = −
R4

C7 x R4 should be chosen so as not to compromise the low frequency performance of this

product.

Figure 2 Recommended External Components

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1.5 General Description

The CMX808A is a programmable CTCSS ‘Type 2’ encoder and decoder for Family Radio, see Figure 1.

The receiver of the CMX808A decodes a user-programmable set of up to 7 tones with minimum software
intervention; the band-pass filter is designed to filter out the CTCSS sub-audio tones. A high resolution
tone encoder performs accurate generation of CTCSS tones.

Each function, and the routing of signals, is flexible and may be configured or controlled by the user's
software.

1.5.1 Software Description

Address/Commands
Instructions and data are transferred, via "C-BUS", in accordance with the timing information given
in Figure 6.

Instruction and data transactions to and from the CMX808A consist of an Address/Command
(A/C) byte which may be followed by either:

(i) a further instruction or data (1 or 2 bytes) or

(ii) a status or Rx data reply (1 byte)

8-bit Write Only Registers

HEX REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADDRESS/ NAME (D7) (D6) (D5) (D4) (D3) (D2) (D1) (D0)
COMMAND

$01 GENERAL N/A N/A N/A N/A N/A N/A N/A N/A
RESET
CTCSS CTCSS DECODER BANDWIDTH CTCSS
$80 SUB-AUDIO TX DECODER MSB LSB 0 IRQ
CONTROL ENABLE ENABLE BIT 3 BIT 2 BIT 1 BIT 0 MASK
AUDIO ATTENUATION
$82 AUDIO TX BPF RX BPF BPF MSB LSB
CONTROL ENABLE ENABLE UN-MUTE BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

16-bit Write Only Registers

HEX REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADDRESS/ NAME (D7) (D6) (D5) (D4) (D3) (D2) (D1) (D0)
COMMAND
CTCSS CTCSS CTCSS TX FREQUENCY
TX FREQ. TX 0 0 MSB
$83 (Byte 1) NOTONE BIT 12 BIT 11 BIT 10 BIT 9 BIT 8
CTCSS CTCSS TX FREQUENCY
TX FREQ. LSB
(Byte 2) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CTCSS RX CTCSS TONE ADDRESS CTCSS FREQUENCY
PROGRAM 0 MSB LSB MSB
$84 (Byte 1) BIT2 BIT 1 BIT 0 BIT 11 BIT 10 BIT 9 BIT 8
CTCSS RX CTCSS FREQUENCY
PROGRAM LSB
(Byte 2) BIT 7 BIT6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

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Write Only Register Description

GENERAL RESET (Hex address $01)

The reset command has no data attached to it. It sets the device registers to zero (all powersaved) with
the exception of Bits 2, 1 and 0 of the SUB-AUDIO STATUS register $81.

SUB-AUDIO CONTROL Register (Hex address $80)

This register is used to control the functions of the device as described below:

CTCSS TX ENABLE These two bits enable and disable the CTCSS decoder (Rx) or transmitter (Tx)
and DECODER according to the table below:
ENABLE
(Bits 7 and 6)
Tx Rx Function
Bit 7 Bit 6
0 0 Tx disabled, Rx disabled
0 1 Tx disabled, Rx enabled
1 0 Tx enabled, Rx disabled
1 1 Tx enabled, Rx enabled

CTCSS DECODER These four bits set the bandwidth of the CTCSS tone decoder according to the
BANDWIDTH table below:
(Bits 5, 4, 3 and 2)
BANDWIDTH
Bit 5 Bit 4 Bit 3 Bit 2 Will Will Not
Decode Decode
1 0 0 0 ±1.1% ±2.4%
1 0 0 1 ±1.3% ±2.7%
1 0 1 0 ±1.6% ±2.9%
1 0 1 1 ±1.8% ±3.2%
1 1 0 0 ±2.0% ±3.5%
1 1 0 1 ±2.2% ±3.7%
1 1 1 0 ±2.5% ±4.0%
1 1 1 1 ±2.7% ±4.2%

(Bit 1) Reserved for future use. This bit should be set to "0".

CTCSS IRQ MASK When this bit is set to "1" it enables the interrupt.
(Bit 0) When this bit is set to "0" the interrupt is masked.

AUDIO CONTROL Register (Hex address $82)

This register is used to control the functions of the device as described below:
Note: TX BPF ENABLE (Bit 7) and RX BPF ENABLE (Bit 6) should not be enabled at the same time.
TX BPF ENABLE When this bit is "1" the audio band-pass filter is enabled and the output of the
(Bit 7) filter is switched to TX AUDIO OUT. The output is then controlled by BPF UN-
MUTE. See Bit 5 below.
When this bit is “0” the audio band pass filter is disabled (powersaved) and the
output of the filter is disconnected from TX AUDIO OUT, which is then in a high
impedance state.

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

RX BPF ENABLE When this bit is “1” the audio band-pass filter is enabled and the output of the
(Bit 6) filter is switched to RX AUDIO OUT. The output is then controlled by BPF UN-
MUTE. See Bit 5 below.
When this bit is “0” the audio band-pass filter is disabled (powersaved) and the
output of the filter is disconnected from RX AUDIO OUT, which is then in a high
impedance state.
BPF UN-MUTE When this bit is “1” and TX BPF ENABLE is “1” the audio band-pass filter output
(Bit 5) is switched to the TX AUDIO OUT pin. When this bit is “0” the output of the filter
is disconnected from TX AUDIO OUT, which is then in a high impedance state.
This control, along with TX BPF ENABLE, allows the filter to power up and settle
internally before switching the output on, when coming out of powersave.
When this bit is “1” and RX BPF ENABLE is “1” the audio band-pass filter output
is switched to the RX AUDIO OUT pin. When this bit is “0” the output of the
filter is disconnected from RX AUDIO OUT, which is then in a high impedance
state. This control, along with RX BPF ENABLE, allows the filter to power up
and settle internally before switching the output on, to avoid clicks when coming
out of powersave.
AUDIO ATTENUATION These five bits are used to set the attenuation of the audio volume control
(Bits 4, 3, 2, 1, and 0) according to the table below:
Bits Audio
4 3 2 1 0 Attenuation
0 0 0 0 0 Off (VBIAS)
0 0 0 0 1 48.0dB
0 0 0 1 0 46.4dB
0 0 0 1 1 44.8dB
0 0 1 0 0 43.2dB
0 0 1 0 1 41.6dB
0 0 1 1 0 40.0dB
0 0 1 1 1 38.4dB
0 1 0 0 0 36.8dB
0 1 0 0 1 35.2dB
0 1 0 1 0 33.6dB
0 1 0 1 1 32.0dB
0 1 1 0 0 30.4dB
0 1 1 0 1 28.8dB
0 1 1 1 0 27.2dB
0 1 1 1 1 25.6dB
1 0 0 0 0 24.0dB
1 0 0 0 1 22.4dB
1 0 0 1 0 20.8dB
1 0 0 1 1 19.2dB
1 0 1 0 0 17.6dB
1 0 1 0 1 16.0dB
1 0 1 1 0 14.4dB
1 0 1 1 1 12.8dB
1 1 0 0 0 11.2dB
1 1 0 0 1 9.6dB
1 1 0 1 0 8.0dB
1 1 0 1 1 6.4dB
1 1 1 0 0 4.8dB
1 1 1 0 1 3.2dB
1 1 1 1 0 1.6dB
1 1 1 1 1 0dB

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

CTCSS TX FREQUENCY Register (Hex address $83)

This is a 16-bit register. Byte (1) is sent first. When the CTCSS transmitter is enabled, the bits 0 to 12
control the frequency of the transmitted CTCSS tones according to the formula below.

fXTAL (Hz)
A=
16 x fTONE (Hz)

where A is the binary number programmed into the 13 bits.

When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the
number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming bits
0 to 12 to "0" sets the output to VBIAS. Powersave is achieved by disabling the Tx (Bit 7 in the SUB-
AUDIO CONTROL register $80).

CTCSS RX PROGRAM Register (Hex address $84)

This is a 16-bit register. Byte (1) is sent first. The two bytes are used to program the centre frequencies of
up to 7 tones in the sub-audio band that will be decoded by the receiver.

Each tone is identified by its address in Bits 6, 5 and 4 of byte (1). The remaining 12 bits contain the data
representing the tone frequency according to the formula below. If a tone is not required the 12 bits should
be set to zero.

Byte 1 Byte 2
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 <----------------------- N -----------------------> <----------------------- R ----------------------->
0 0 0 1
0 0 1 0 N is the binary representation of the R is the nearest 6-bit binary
0 0 1 1 following decimal number (n): representation of (r), where:
0 1 0 0
0 1 0 1 n = INT (948982 x fTONE / fXTAL) r = ((237245/fXTAL) - (n/(4 x fTONE))) x 8400
0 1 1 0

Example: To program 100Hz when using the recommended 4.0MHz Xtal.

n = INT (948982 x 100 / 4.0 x 10^6)

= INT (23.72) = 23

∴ N = 010111 (binary)

r = ((237245 / 4.0 x 10^6) - (23 / (4 x 100))) x 8400

= 15.21 (round up if exactly halfway)
= 15

∴ R = 001111 (binary)

Thus the 12-bit code is 010111001111.

The Hex address represented by Bits 6, 5 and 4 in byte (1) is used as the code to indicate which tone has
been decoded. This code appears in Bits 2, 1 and 0 of the SUB-AUDIO STATUS register $81. The 7
programmed tones use Hex addresses $0 - $6. Address $7 should not be used.

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

TONE CLONING Register (Hex address $9C)

This register enables and disables tone cloning as shown below:

$9C = $01 enables tone cloning.

$9C = $00 disables tone cloning.

Figure 4 shows the tone cloning routine.

8-bit Read Only Registers

HEX REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADDRESS/ NAME (D7) (D6) (D5) (D4) (D3) (D2) (D1) (D0)
COMMAND
CTCSS RX TONE
$81 SUB-AUDIO 0 0 0 0 TONE MSB LSB
STATUS DECODE BIT 2 BIT 1 BIT 0

Read Only Register Description

SUB-AUDIO STATUS Register (Hex address $81)

Reading the SUB-AUDIO STATUS register clears the interrupt (IRQN).

This register is used to indicate the status of the device as described below:

(Bits 7, 6, 5 and 4) Reserved for future use. These will be set to "0" but should be ignored by user's
software.

TONE DECODE This bit indicates the status of the tone decoder. A "1" indicates a tone has been
(Bit 3) detected (TONE DECODE) and a "0" indicates the loss of the tone (NOTONE).

TONE DECODE means that a tone has been decoded and its characteristics are
defined by the bandwidth (see SUB-AUDIO CONTROL register $80, Bits 5, 4, 3
and 2) and the CTCSS RX TONE number (see SUB-AUDIO STATUS register
$81, Bits 2, 1 and 0).

When Bit 6 in the SUB-AUDIO CONTROL register $80 is set to "0" the TONE
DECODE Bit 3 will be set to "0".

Identification of a valid tone which is not in the pre-programmed list of up to 7

tones will cause the decoder to move to the TONE DECODE state with the RX
TONE address of "111" in Bits 2, 1 and 0; indicating a valid but unrecognised
tone. Loss of tone will cause the NOTONE timer to be started. If loss of tone
continues for the duration of the time-out period, then the decoder will move to
NOTONE state and the identification of pre-programmed tones will start again.
The time-out period is not user adjustable.

CTCSS RX TONE These three bits hold a Hex number. Numbers $0 to $6 represent the address
(Bits 2, 1 and 0) of the CTCSS tone decoded according to the tones programmed in the CTCSS
RX PROGRAM register $84. The Hex number $7 indicates the presence of any
tone that is not described by CTCSS DECODER BANDWIDTH (Bits 5, 4, 3 and
2 in the SUB-AUDIO CONTROL register $80) and CTCSS FREQUENCY (Bits
11 to 0 in the CTCSS RX PROGRAM register $84).

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

The flow chart shows the decoder and transmitter modes of operation for the example below:

1. Decoder, e.g. Address 0 = 100Hz, bandwidth = ±2.7%, interrupt enabled.

2. Transmitter, e.g. Tx = 100Hz. .

Note: $8X is the Hex address/command.

Figure 3 Tx/Rx enabled

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

The flow chart shows the tone cloning routine. The first programmed tone set ($0-$6) will decode after
typically 140ms, subsequent tone sets will decode almost instantly (i.e. the information is available at the
Reply Data Output in less than 100µs).
Note: $8X and $9C is the Hex address/command.

Figure 4 Tone Cloning

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

1.6 Application Notes

1.6.1 General
The CMX808A is intended for use in radio systems where sub-audio signalling is required for functions
such as Family Radio Service (FRS) Handportables, Amateur Radio Equipment, General Mobile Radio
Service (GMRS) and Short Range Business Radio.

The facility to decode any of up to 7 programmed tones allows FRS designers to offer equipment which
can look for personal, family or open channel codes at the same time. Codes can be used as paging
codes, open chat mode codes as well as personal and family codes.

Adjustable decoder bandwidths permits certainty and signal to noise performance to be traded when
congestion or range limits the system performance.

1.6.2 Transmitter
The transmitter is enabled with Bit 7 in the SUB-AUDIO CONTROL register $80.

The Tx frequency is set using bits 0 to 12 in the CTCSS TX FREQUENCY register $83, using the formula
below:

fXTAL (Hz)
A=
16 x fTONE (Hz)

where A is the binary number programmed into the 13 bits.

When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the
number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming bits
0 to 12 to "0" sets the output to VBIAS. Powersave is also achieved by disabling the Tx (Bit 7 in the SUB-
AUDIO CONTROL register $80).

1.6.3 Receiver (Decode)

The CTCSS Receiver (Decoder) should first be set up according to the desired characteristics. This
entails setting the CTCSS DECODER BANDWIDTH in the SUB-AUDIO CONTROL register $80, also
programming the centre frequencies of the desired tones in the CTCSS RX PROGRAM register $84. (It
can hold up to 7 different tones). Any tone can be in any location. During operation when the device is
receiving, the tones are scanned in the sequence of their location, i.e. $0 first and $6 last and once a tone
is detected the remaining tones are not checked. Therefore if two tones are close enough in frequency for
their bandwidths to overlap then the one in the lowest location will be detected.

The CTCSS IRQ MASK in the SUB-AUDIO CONTROL register $80 should also be set as required.

The CTCSS DECODER ENABLE in the SUB-AUDIO CONTROL register $80 should then be set to "1".

The TONE CLONING register $9C should be set as required.

When the receiver detects a change in its present state an interrupt will be generated. The change that
occurred can be read from Bit 3 of the SUB-AUDIO STATUS register $81 and if a tone is indicated by
these bits then the number of that tone can be read from Bits 2, 1 and 0 of the same register. The
interrupt is cleared by reading the SUB-AUDIO STATUS register.

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

1.6.4 Tx Tone Table

The following table lists the commonly used CTCSS tones and the corresponding values for programming
the CTCSS TX FREQUENCY register $83.

STANDARD TONES
Freq. Byte 1 Byte 2 Freq. Byte 1 Byte 2 Freq. Byte 1 Byte 2
(Hz) (Hex) (Hex) (Hz) (Hex) (Hex) (Hz) (Hex) (Hex)
67.0 0E 93 103.5 09 6F 162.2 06 05
69.3 0E 18 107.2 09 1C 167.9 05 D1
71.9 0D 95 110.9 08 CE 173.8 05 9E
74.4 0D 20 114.8 08 82 179.9 05 6E
77.0 0C AF 118.8 08 38 186.2 05 3F
79.7 0C 41 123.0 07 F1 192.8 05 11
82.5 0B D6 127.3 07 AC 203.5 04 CD
85.4 0B 6F 131.8 07 69 210.7 04 A3
88.5 0B 09 136.5 07 28 218.1 04 7A
91.5 0A AC 141.3 06 E9 225.7 04 54
94.8 0A 4D 146.2 06 AE 233.6 04 2E
97.4 0A 07 151.4 06 73 241.8 04 0A
100.0 09 C4 156.7 06 3B 250.3 03 E7

NON-STANDARD TONES
Freq. Byte 1 Byte 2 Freq. Byte 1 Byte 2 Freq. Byte 1 Byte 2
(Hz) (Hex) (Hex) (Hz) (Hex) (Hex) (Hz) (Hex) (Hex)
62.5 0F A0 183.5 05 52 199.5 04 E5
64.7 0F 18 189.9 05 24 206.5 04 BB
159.8 06 1C 196.6 04 F8 229.1 04 43

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

1.6.5 Rx Tone Table

The following table lists the commonly used CTCSS tones together with the values for programming the
CTCSS RX PROGRAM register $84.

N.B. The values for byte 1 and 2 below apply to tone address 0 only. These values will vary depending
on the location they are programmed into.

STANDARD TONES
Freq. Byte 1 Byte 2 Freq. Byte 1 Byte 2 Freq. Byte 1 Byte 2
(Hz) (Hex) (Hex) (Hz) (Hex) (Hex) (Hz) (Hex) (Hex)
67.0 03 DC 103.5 06 0B 162.2 09 86
69.3 04 0D 107.2 06 48 167.9 09 CA
71.9 04 42 110.9 06 86 173.8 0A 43
74.4 04 52 114.8 06 C4 179.9 0A 88
77.0 04 87 118.8 07 03 186.2 0B 02
79.7 04 98 123.0 07 43 192.8 0B 48
82.5 04 CF 127.3 07 83 203.5 0C 03
85.4 05 06 131.8 07 C4 210.7 0C 4A
88.5 05 18 136.5 08 06 218.1 0C C7
91.5 05 50 141.3 08 48 225.7 0D 45
94.8 05 8B 146.2 08 8A 233.6 0D C4
97.4 05 C2 151.4 08 CD 241.8 0E 43
100.0 05 CF 156.7 09 42 250.3 0E C3

NON-STANDARD TONES
Freq. Byte 1 Byte 2 Freq. Byte 1 Byte 2 Freq. Byte 1 Byte 2
(Hz) (Hex) (Hex) (Hz) (Hex) (Hex) (Hz) (Hex) (Hex)
62.5 03 9C 183.5 0A C6 199.5 0B C3
64.7 03 CB 189.9 0B 41 206.5 0C 0A
159.8 09 4C 196.6 0B 87 229.1 0D 83

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Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

1.7 Performance Specification

1.7.1 Electrical Performance

1.7.1.1 Absolute Maximum Ratings

Exceeding these maximum ratings can result in damage to the device.

Min. Max. Units

Supply (VDD - VSS) -0.3 7.0 V
Voltage on any pin to VSS -0.3 VDD + 0.3 V
Current into or out of VDD and VSS pins -30 +30 mA
Current into or out of any other pin -20 +20 mA

E3 Package Min. Max. Units

Total Allowable Power Dissipation at Tamb = 25°C 300 mW
... Derating 5 mW/°C
Storage Temperature -55 +125 °C
Operating Temperature -40 +85 °C

P4 Package Min. Max. Units

Total Allowable Power Dissipation at Tamb = 25°C 800 mW
... Derating 13 mW/°C
Storage Temperature -55 +125 °C
Operating Temperature -40 +85 °C

1.7.1.2 Operating Limits

Correct operation of the device outside these limits is not implied.

Notes Min. Max. Units

Supply (VDD - VSS) 3.0 5.5 V
Operating Temperature -40 +85 °C
Xtal Frequency 3.9996 4.0004 MHz

 2003 CML Microsystems Plc 17 D/808A/6

Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

1.7.1.3 Operating Characteristics

For the following conditions unless otherwise specified:
Xtal Frequency = 4.0MHz
Audio Level 0dB ref. = 308mVrms at 1kHz
VDD = 3.0V to 5.0V, Tamb = -40°C to +85°C.
Composite Signal = 308mVrms at 1kHz + 75mVrms Noise + 31mVrms Sub-Audio Signal
Noise Bandwidth = 5kHz Band Limited Gaussian
Notes Min. Typ. Max. Units

DC Parameters
At VDD = 3.0V
IDD (powersaved) 2 - 0.2 0.3 mA
IDD (Encoder or Decoder only Operating) 2 - 1.3 2.0 mA

At VDD = 5.0V
IDD (powersaved) 2 - 0.5 0.8 mA
IDD (Encoder or Decoder only Operating) 2 - 3.2 4.8 mA

"C-BUS" Interface
Input Logic "1" 70% - - VDD
Input Logic "0" - - 30% VDD
Input Leakage Current (Logic "1" or "0") -1.0 - 1.0 µA
Input Capacitance - - 7.5 pF
Output Logic "1" (IOH = 120µA) 90% - - VDD
Output Logic "0" (IOL = 360µA) - - 10% VDD
"Off" State Leakage Current (Vout = VDD) 3 - - 10.0 µA

AC Parameters
CTCSS Decoder
Sensitivity (Pure CTCSS Tone) 5 - -26.0 - dB
Response Time (Composite Signal) - 140 - ms
De-Response Time (Composite Signal) - 145 - ms
Frequency Range 60.0 - 251 Hz

CTCSS Encoder
Frequency Range 60.0 - 251 Hz
Tone Frequency Resolution - - 0.3 %
Tone Amplitude Tolerance 1 -1.0 0 +1.0 dB
Total Harmonic Distortion - 3.0 - %

Audio Band-Pass Filter

Passband 6 350 - 3000 Hz
Passband Gain (at 1.0kHz) 6 - 0 - dB
Passband Ripple (w.r.t. gain at 1.0kHz) 6 -2.0 - +0.5 dB
Stopband Attenuation 6 30.0 - - dB
Residual Hum and Noise - -50.0 - dBp
Alias Frequency - 62.5 - kHz

Audio Attenuator
Nominal Adjustment Range 0 - 48 dB
Attenuation Accuracy -1.5 - 1.5 dB
Step Size - 1.6 - dB

 2003 CML Microsystems Plc 18 D/808A/6

Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

Notes Min. Typ. Max. Units

Output Impedances
TX SUB-AUDIO OUT (Enabled) - 2.0 - kΩ
TX/RX AUDIO OUT (Enabled) - 600 - Ω
TX/RX AUDIO OUT (Disabled) - 500 - kΩ
VOLUME OUT (Enabled) 7 - 600 - Ω

Rx Amplifier
Open Loop Gain (I/P = 1mV at 100Hz) - 70.0 - dB
Unity Gain Bandwidth - 5.0 - MHz
Input Impedance (at 100Hz) 10.0 - - MΩ
Output Impedance (Open Loop) - 6.0 - kΩ

Xtal/Clock Input
Pulse Width ('High' or 'Low') 4 40.0 - - ns
Input Impedance (at 100Hz) 10.0 - - MΩ
Gain (I/P = 1mVrms at 100Hz) 20.0 - - dB

Notes: 1. At VDD = 5.0V only. Signal levels or currents are proportional to VDD.
2. Not including any current drawn from the device pins by external circuitry.
3. IRQN pin.
4. Timing for an external input to the XTAL/CLOCK pin.
5. With input gain components set as recommended in Figure 2.
6. See filter response (Figure 5).
7. Small signal impedance VDD = 5.0V and Tamb=25°C. A minimum load resistance of
6kΩ is suggested.

1.7.1 Electrical Performance (continued)

5

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50
10 100 1,000 10,000 100,000
Frequency (Hz)

Figure 5 Audio Band-Pass Filter Frequency Response

 2003 CML Microsystems Plc 19 D/808A/6

Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

1.7.1 Electrical Performance (continued)

Timing Diagrams

Figure 6 "C-BUS" Timing

For the following conditions unless otherwise specified:

Xtal Frequency = 4.0MHz, VDD = 3.0V to 5.0V, Tamb = -40°C to +85°C.

Parameter Notes Min. Typ. Max. Units

tCSE "CS-Enable to Clock-High" 2.0 - µs
tCSH Last "Clock-High to CS-High" 4.0 - µs
tHIZ "CS-High to Reply Output 3-state" - 2.0 µs
tCSOFF "CS-High" Time between transactions 2.0 - µs
tNXT "Inter-Byte" Time 4.0 - µs
tCK "Clock-Cycle" time 2.0 - µs

Notes: 1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the
peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB
(Bit 7) first, LSB (Bit 0) last.
2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge.
3. Loaded commands are acted upon at the end of each command.
4. To allow for differing µController serial interface formats "C-BUS" compatible ICs are able to
work with either polarity SERIAL CLOCK pulses.

 2003 CML Microsystems Plc 20 D/808A/6

Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

1.7.2 Packaging

Figure 7 Mechanical Outline: Order as part no. CMX808AE3

Figure 8 Mechanical Outline: Order as part no. CMX808AP4

 2003 CML Microsystems Plc 21 D/808A/6

Family Radio CTCSS 'Type 2' Encoder and Decoder CMX808A

Handling precautions: This product includes input protection, however, precautions should be taken to prevent device
damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No
IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and
this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure
compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.

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