FPGA Implementation of Self-Reconfigurable Fuzzy

Logic Controller
Hedi Abdelkrim, Slim Ben Othman, Slim Ben Saoud
Laboratoire des Systèmes Avancés LSA EPT
Carthage University
La Marsa, Tunisia
[email protected], [email protected], [email protected]

Abstract—Nowadays, new system design requirements the various operating modes that real application case deal,
are increasing more and more. Even though, the SoC FPGA controller should perform real-time parameter tuning to obtain
based is a good choice given their flexibility, the good performances [6]. Enhancing existing system on Chip
Reconfigurable System on Chip (RSoC) is a better flexible (SoC) with partial reconfiguration capabilities has opened a real
solution that allows chip Partial Reconfiguration (PR). In opportunity to designers [7] to best solve problem facing with
this study, we present a PR design approach of FPGA based real conditions utilization. In fact, due to special environment
Fuzzy Logic Controller (FLC) for electromechanical conditions, designers often need to change functionalities or
system. In order to enhance flexibility and performance of adapt some parameters on the fly. With the reconfigurable
System on Chip (RSoC), it becomes possible doing that without
the considered system, a self-reconfigurable system is
turning off the system. It is possible to change only a portion of
designed. Based on Zynq Processor of the Zedboard, the
the chip while the remaining part continue turning on.
system switches between different versions of the HW speed
FLC. Experimental results were validated and the Based on our literature review, several recent projects are
efficiency of the approach was confirmed. dealing with the implementation of fuzzy logic controller. In [2]
and [8], the authors describe FPGA implementation of a fuzzy
Keywords—Dynamic Partial Reconfiguration; Implementation; logic trajectory tracking controller. In [9], the paper presents a
FPGA; Zynq Processor; Fuzzy Logic Controller; Reconfigurability; speed control scheme using a FLC. Others in [10] describe a
reconfigurable implementation of a FLC. For authors in [11],
I. INTRODUCTION the purpose is to implement a FLC for level control. In [12],
Today, the fuzzy logic adjustment lends itself particularly more complex system is proposed with adaptive neuro-fuzzy
well to two areas of applications, which correspond respectively structure controller.
to the design of controllers for processes that are difficult to In this paper, we propose embedded systems able to self-
model and the design of nonlinear controllers for modelled adapt parameters and precisely change FPGA configuration
processes, [1]. depending on the environment conditions change and based on
In the first case, we must apply a heuristic process based on a user-defined scheme. A dynamic partial reconfigurable FLC
the expertise and experiences of the operators. However, it is is designed and implemented on a zedboard to control a DC
often necessary to take a long and difficult approach to obtain motor speed.
good results. In the second case, non-linear characteristics are
In the section 2, we focus on the system drive specifications
used to improve the performance of conventional settings that
and the FLC components. Section 3 presents the system design,
operate in a linear way. hardware and software flows are also detailed and
In addition, fuzzy systems offer designers of implementation results are given.
microelectronic circuits the ability to use non-linear controllers
for their applications. Fuzzy controllers are traditionally II. DRIVE CONTROL STRUCTURE
implemented on a microprocessor [2] [3], but also on dedicated
VLSI circuits like the CMOS case described by Ota [4] and A. Motor Control Specifications
Wilamowski [5]. The considered process is a low power DC permanent
magnet Motor (DCM) associated with a 4-quadrant chopper. It
A fuzzy controller does not handle a well-defined
is composed by (1) the process to control including the
mathematical relationship (control algorithm), but uses
converter circuit, the electric motor and load equipment and
inferences with multiple rules, based on linguistic variables.
different sensors and (2) the digital control unit, which is
These inferences are then processed by fuzzy logic operators.
composed of the digital controller, based on fuzzy logic and the
Currently, the versatility of the FPGAs made them one of necessary interfaces for sensors and control signals generation,
the major solution used in complex system design. It is possible to be implemented on FPGA. The drive system (in fig.1) is
to combine several complex functions in the same chip. With based on a nested closed loop managing the motor speed. The

978-1-5386-4449-2/18/$31.00 ©2018 IEEE.

151
speed control algorithm will be based on an evaluation of input p
parameters the error İ and change of error dİ/dt as shown on
figure 1.
¦ μ .V
j =1
j j
*
X =R p
(1)
¦μ j =1
j

With: XR the barycenter abscissa, Vj and μj respectively the

abscissa and the ordinate of the center point of the fuzzy output
sets.

Fig. 1. System Bloc design 4) The system Simulation

We have designed various versions of the FLC based on
B. Fuzzy Logic Controller previous work result [13] and by changing different parameters.
The FL algorithm does not handle a specific mathematic In fact, we first varied the number of linguistic variables, then
statement, but uses inference rules based on linguistic variables. modified the form of the membership functions. Similarly, we
used two methods for inference, one method with a complete
As any system based on fuzzy logic, the speed control that rule table and one with an incomplete rule table. Different
we propose to design is divided into 3 phases namely simulation tests were done on Matlab to validate the controller
fuzzification, inference and defuzzification. Fuzzification parameters.
consists of transforming entries into linguistic variables by
means of membership functions. For the case of our application, The result illustrated in Figure 2 represents a zoom on the
we opted for triangular functions. Inference links the input results obtained by a step reference (ȍref = 250rad/s). We
linguistic variables to the output variables, expressed in turn as notice that the system response when using 5 linguistic
linguistic variables (the inference engine used is Max-min from variables gives a better result than the one with 3 linguistic
Mamdani). Finally, defuzzification consists of translating variables. Indeed, with 3 linguistic variables we obtain a static
linguistic variables into numerical variables. error equal to 1.4%, whereas with 5 linguistic variables we
obtain a static error of the order of 0.16%.
The three steps below define the FLC.
In the chosen application case, a 2% threshold εth is tolerated
1) Fuzzification: The membership functions may have while system turning on. So the FLC with 3 linguistic variables
different forms such as triangular or trapezoidal. In this paper, can be adopted for this purpose.
we use triangular membership functions. The physical
quantities "X" are to be normalized quantities "x" belonging to
the interval [-1,1]. In general, we introduce for a variable 'x': 3,
5 or 7 sets, represented by membership functions. The number
of sets depends on the resolution of the desired control.
Sets are characterized by standard designations whose
symbolic meaning is indicated as follows: NB Negative Big,
NS Negative Small, NZ Near Zero, PS Positive Small, PB
Positive BIG.
2) Inference: The control strategy depends essentially on
the inferences adopted. They link input variables to output
variables "Xr", which in turn is expressed as a linguistic
variable. Mainly, the following three forms can present the
Inference: a linguistic description, an inference table or an
inference matrix. There are several methods that determine the
realization of different operators in an inference, thus allowing Fig. 2. Simulation System response
its digital processing, for fuzzy logic tuning, one of the
following methods is generally used: Max-min inference In the next section, we describe the different steps followed
method (used in this paper), Max-prod inference method or to implement a reconfigurable FLC on FPGA and give
Sum-prod inference method. experimental results.
3) Defuzzification: Since the system to be controlled III. SYSTEM DESIGN AND IMPLEMENTATION
requires a physical quantity, it is necessary to predict the
The experimental concept description is depicted in figure
transformation of the linguistic variable into a crisp value. This 3. Three main parts describe the system. 1) A PC user interface
transformation is called defuzzification. In this application, we allows choosing the reference and gives the possibility to
used the centroid method as given by the relation in the equation retrieve the motor speed through UART communication with
1. FPGA board, particularly with the embedded processor. 2) The

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Hardware Fuzzy Logic Controller Intellectual Property (Hw Modules (RM) based respectively on 3 and 5 linguistic
FLC IP) has 3 inputs: the speed reference (from PS), the variables version of the FLC. The design can be dynamically
encoder signals (a and b) and 2 outputs (chopper pwm signals). reconfigured using PS sub-system and Processor Configuration
Mainly it consists of 3 parts (figure 4): the FLC calculation and Access Port (PCAP) resource.
data formatting bloc and the pulse width modulate (pwm)
generator 3) The set DC Motor, Chopper and Encoder
represents the operative part. DDR3 PL
Memory Memory
Controller
7000 Series FPGA Board
ARM Hw FLC IP
a
DC RS232 UART Cortex-
Hardware b

AXI IPIC
Interconnect
PS Motor A9 pwm1
PC Fuzzy Logic

Block
pwm2

AXI
UART Device Decoupler
User Interface Ccontroller Configuration RP
IP Pwm Signals Chopper
a PS
(Hw FLC IP) b Encoder RP: Reconfigurable Partition

Fig. 5. Design description

Fig. 3. Experimental concept The ARM Cortex-A9 PS of the Zynq 7000 is used to create
the reconfigurable peripheral (Hw FLC IP) and to interface
Based on a time stamp, the encoder signals a and b are used user. The static logic part of this IP consists of the processor
to calculate the motor speed. subsystem, the AXI Interconnect, the AXI IPIC of the
reconfigurable peripheral and the remaining parts of the FLC.
ε
20bits register As shown in the figure 6, there is one RP in the FLC, which
ε is the fuzzification. The remaining parts are included in the
Error and
Ÿref static portion.
13bits register error change
calculation dε/dt
Ÿ Bloc FLC
13bits register ε
PWM Įdig Fuzzification
Speed generator ___________
pwm1
pwm2

Calculation dε/dt RP Inference

a b
Rules Table
Fig. 4. Hw FLCP IP description

A. Partial reconfiguration scenario

One of the main purposes of this work is to validate our Įdig
approach proposed which is to switch between different
Generate
control angle Defuzzification
configurations depending on the targeted system performance.
For the case study treated, the processor constantly compares
the static error with the 2% threshold. If any additional load is Fig. 6. FLC design
applied on the motor shaft or in the case of the presence of a
resistive torque, that the FLC can’t compensate (error>2%) for C. Controller Design consideration
a period Thold (defined from the user interface), the processor The FLC already tested in the simulation section was
initiates a partial reconfiguration of the controller. Indeed, written and tested under Matlab environment. For real machine
while keeping the system active, the RM with 5 linguistic tests, the whole fuzzy controller design will be written in VHDL
variables will be implemented. in order to be hardware implemented on the FPGA. Thus, some
In this section, we first give a brief description of the modifications need to be done to adapt the controller designed.
hardware used and second we describe the design flow We need an encoding techniques for the data. We choose to use
including the partial reconfiguration consideration. bit streams one, which consists of upgrading the level of the
used data then specifying the desired precision, [1].
B. Hardware Design
So we should consider a new representation for all the data.
The system design was carried out using Vivado Design In fact, the variation range of each data must be probably
Suite 2017.1 and as FPGA target the ZedBoard Development adapted, based on the encoding techniques values. A relation
Kit based on the Zynq-7000 XC7Z020 [14]. The design is between digital values and continuous ones is established.
shown in figure 5.
For fuzzification step, all the equation for membership
The design includes the Zynq processor system (PS) as a function will change, for example:
sub-module. As previously mentioned, we need to define one
Reconfigurable Partition (RP) having two Reconfigurable

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 If ((İ < í0.5) and (İ > í1)) <=> If ((İnum < í0.5*1024) and We give in the table 1 details about hardware synthesis for
(İnum > í1*1024)) the RP. Even the RM1 require less hardware resources, the RP
should be large enough to include the bigger reconfigurable
For inference part, there is no change to do. Indeed, we use module.
the method of inference Max-min, and this method only uses
the operators of max and min, so we will have no treatment to Power consumption estimations for RM1 and RM2 are
apply to manipulated values. given on figures 8 and 9.
The defuzzification consists of determining the barycenter
of the selected surface on the set of the output membership
functions, the ordinates of the center points must be digitalized.
Two version of the FLC were designed based on the number
of membership functions of the fuzzification step. We mean by
RM1 and RM2 respectively the fuzzification with 3 and 5
linguistic variables. The two versions were realized using
VHDL language under. The controllers were individually tested
and verified by flat design experimentation.
.
Step 1: Step 2: Step 3: Step 4:
Generate DCP Load Static and Define Define
for Static and one RM for Reconfigurable Reconfigurable
RM modules each RP Properties Partitions

Step 6:
Step 5:
Create and
Step 7: Step 8: Fig. 8. Power Consumption FLC with RM2
Run Design Create Other Run
Rule Checker Implement First Configurations PR_Verify
Configuration

Step 9: Step 10: Step 11:

Generate Test the Design
Generate Bit
Software
Files Application

Fig. 7. PR Flow used

As shown in figure 7, we first begin by generating the design

checkpoint for the static design then generate RM checkpoints
for each RM using out of context synthesis. Some properties for
the RM should be considered. Each RM residing in a same RP
must have same number, type, and size ports and the top-level
module (entity) name. Next, we define Reconfigurable
Partitions (RP) pblocks, especially by using Set
HD.RECONFIGURABLE.
Run Design Rule Checker (DRC) to verify violations in Fig. 9. PR Power Consumption FLC with RM1 Flow used
floorplanning, clocking regions, IOs, partial reconfiguration
specific. Next, the implementation option is run for RM1, so Now, we are done with the hardware. It is time to prepare
that the first configuration is created. RM1 is then replaced with the application software using Xilinx Software Development
a black box and the design checkpoint is saved. When done, the Kit (SDK).
second configuration is created with RM2. To ensure that the
D. Software design
static implementation, including interfaces to reconfigurable
regions, is consistent across all configurations, the PR_Verify The application software is done based on the Xilinx flow
is lunched. Full and partial bitsreams are then generated. The [15]. After following the different steps to create the SDK
reconfiguration is done using PCAP. So the PS needs to be project, a C program is developed to configure the ARM
configured to use M_GP0 interface so AXI-Lite peripheral can processor. We give in the figure 10 the program diagram. As
be connected. explained in the PR scenario, the PS interacts with user and
supervise the error value ε. It begins by doing some
TABLE 1: RP RESOURCES REQUIRED initialization and configuration such as uploading in DDR the
Physical Resource Estimates
RM bin files from the SD card. Then, it reads user parameters
(speed reference, threshold value) from UART and update PL
Site Type Available Required %Util
registers through AXI interface. The PS controls the error
LUT 352 34 10 variation over the time. If the FLC is not able to hold ε<εth then
FD_LD 704 4 1 a Timer is started. If this error persists more than a user time
SLICEL 66 10 15 limit Thold, the PS initiates a partial reconfiguration with RM2.
SLICEM 22 5 22

154
 bitstream. But, we notice that the system response is improved
and ε is now about 0.05%. After a Tinit=0.25s a new
reconfiguration is done. RM1 will continue driving the motor
while ε<εth.

Fig. 12. Zoom showing the reconfiguration orders time and effect

The illustrated tests show that the adopted approach was

successfully implemented and validated.
IV. CONCLUSION
This work introduces a self-reconfigurable FLC
implementation FPGA based. We benefit from the flexibility
that offer the PR techniques to design a system able to provide
the appropriate configuration depending on the environment
conditions changes. Furthermore, the adopted approach was
validated by experimental results on a real DC motor controlled
by Zedboard. Besides, there are more than 50% of hardware
resources not used. So we can consider a larger number of
Fig. 10. Main program diagram
environment variables and more complex system to control.
The FLC should run now with 5 linguistic variables and It has been shown that energy consumption can be reduced
improve the system performances. The flow diagram of when not required circuits are not necessary implemented. In
initiating the PR from PS is detailed on [15]. addition, that better performance may require more hardware
The RM2 needs more hardware resources than RM1 so resources. The user should take advantage of such techniques
more, there is more energy needed. To improve energy and probably have to do a compromise between energy
consumption the RM2 is maintained for a stabilization period consumption and system performances.
Tinit. After that, the PS implements through PCAP the RM1. There is a large number asset of PR that can be used to
enhance system performances particularly to respect real time
constraints.
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