H S C I: I T (I T) : Ardware Ecurity For Yber Nfrastructure Nternet of Hings O
H S C I: I T (I T) : Ardware Ecurity For Yber Nfrastructure Nternet of Hings O
IP
IP
DFT
Layout FAB
IP
IP
Feb. 11, 2016: President Obama indicated he will sign into law a customs bill passed
by the U.S. Senate that includes a provision to combat counterfeit semiconductors.
The bill, mandates that U.S. Customs share information and samples of suspected
counterfeit parts for rapid identification of counterfeits. Full transparency!!
http://www.eetimes.com/document.asp?doc_id=1328931
M ARKET P ROJECTION IS C ONSISTENT
Requirement of packaging for (in) modern era
Infected ecosystem
Infected chip
Infected package
I NTERNET OF A NIMALS , ( WEARABLE FOR PETS )
I NTERNET OF FARM ( WEARABLE FOR COW, SHEEP, …)
I NTERNET OF P LANTS
IOT SIP attached to monitor condition of growth plant that makes phone calls or tweets if it needs water
Insulin Pumps
Foot Drop
Implants
Source: entertainment.wikia.com
B ACK IN J ULY 2015
“Hackers Remotely Kill a Jeep on the Highway”
Two hackers from their basement break into a car on the highway
Vents started blasting cold air at maximum speed
Software
Assumption: Core Root of Trust (CRT) is secure
Operating
Applications Protocols
Systems
IOT SIP
MEMS Sensor
Analog/Wifi Memory
Controller
M ODES OF I NFECTION
Side Channels
Trojan • Power variation Tampering &
Cloning and
• Timing variation Reverse
overbuilding (Malicious logic) Engineering
• Test Ports
(JTAG, Scan, …)
S UMMARY OF H ARDWARE S ECURITY T HREATS
Reverse Engineering: Probe the design and build your own
Cloning: Just copy the existing products
Overbuilding: The easiest form, fab and package more than the PO
Tampering: Unauthorized access the hardware
Inadequate Security Measures: Forgot to consider system level
Back Doors: Debug, test ports can be used to break in
Design Defect: Defects in design can be used to break in
Trojan Horse: Insertion of malicious circuit to gain access later
Side-Channel: Use of timing, power data to extract keys, gain access
System Defect: Manufacturing defects that can be used to gain access
T HREAT S OURCES ( HARDWARE ASPECT )!
IP Provider
Hardware Threat
System Integrator
Sources
Manufacturing &
Assembly/Test
https://ssli.ee.washington.edu/people/duh/projects/arbiter.html
http://buyersguide.mae.pennnet.com/microsemi-pmg/p/custom-memory-multichip-package-and-system-in-a-package.html
https://stickman.butterknifeestates.com/2010/05/08/a-3-bit-alu/
P OTENTIAL A REAS OF S UPPLY C HAIN R ISKS
Manufacturing &
Design Front
Assembly
DFT
Untrusted Design
2.5D/3D P ERSPECTIVE ( MORE RISKY )
Clean
Fully Infected
Clean
Min. Infected
Source: Guin et al.: Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain
C OMMON C OUNTERFEIT T YPES
Analog ICs
Processors
Memory
FPGA
Transistors
Tantalum
Capacitors
R ECYCLING PROCESS
http://creativeelectron.com/counterfeit-components-explode/
TAXONOMY OF C OUNTERFEIT D ETECTION
Source: Guin et al.: Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain
E XAMPLE (PARAMETRIC T EST )
Power consumption
Delay test
…
Source: Guin et al.: Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain
E CONOMIC I MPACT OF C OUNTERFEIT PARTS
Hardware Trojan
http://www.ecnmag.com/article/2015/05/how-combat-counterfeit-semiconductors
H ARDWARE T ROJAN
Original Addition
Parametric
Deletion
Difficult to detect
Dormant:
• Some don’t cause failure, but instead leak information (spying).
• Others can be activated when needed.
Difficult to model:
• Manufacturing defects can be modeled by very difficult to model Trojans.
T ROJAN D ETECTION
• Costly
• Time consuming
Destructive • Use SEM to extract layers images
• Identify all the elements
Trusted
Trusted
Trusted Design Packaging
Fabrication
Assembly & Test
Trusted IP
Trusted Libraries & Models
Trusted EDA Tool
44
Summary
IOT SIP R EQUIREMENT
Footprint
Reliability/Quality
Performance
Security
S UMMARY