Unit V

Data Path Subsystems

 Acknowledgment
While preparing this material, data has been taken from various websites and
materials. In this context I am saying thanks for the authors of those who had
written them.
Contents
Page

Contents i

List of Figures ii

List of Tables iii

CHAPTER 1 Data Path Subsystems 1

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3.1 Single-Bit Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3.2 n-Bit Parallel Adder or Ripple Carry Adder . . . . . . . . . . . . . . . . 5
1.3.3 Carry lookahead adder (CLA) . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.4 Manchester carry chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.1 Array Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4.2 Wallace Tree Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5 Parity generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6 Zero/One detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.7 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.8 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.8.1 Asynchronous Up-Counter with T Flip-Flops . . . . . . . . . . . . . . . . 21
1.8.2 Asynchronous Down-Counter with T Flip-Flops . . . . . . . . . . . . . . 22
1.8.3 Synchronous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.8.4 Synchronous Up-Counter with T Flip-Flops . . . . . . . . . . . . . . . . 23

i
List of Figures

1.1 4 x 4 crossbar switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Barrel shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Full adder truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Logic gate implementation of 1-Bit adder . . . . . . . . . . . . . . . . . . . . . 4
1.5 Transistor implementation of 1-Bit adder . . . . . . . . . . . . . . . . . . . . . 4
1.6 Transistor implementation of 1-Bit adder . . . . . . . . . . . . . . . . . . . . . 5
1.7 4-bit ripple carry adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.8 Full adder stage at i with Pi and Gi shown . . . . . . . . . . . . . . . . . . . . . 6
1.9 4-Bit carry lookahead adder implementation in detail . . . . . . . . . . . . . . . 7
1.10 Carry structures of CLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.11 An adder element based on the pass/generate concept. . . . . . . . . . . . . . . 9
1.12 Manchester cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.13 Cascaded Manchester carry-chain elements with buffering . . . . . . . . . . . . . 10
1.14 4-bit multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.16 Basic cell to construct a parallel multiplier . . . . . . . . . . . . . . . . . . . . . 12
1.17 Array multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.18 Most convenient way for implementation of array multiplier . . . . . . . . . . . 14
1.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.20 Table to find product terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.21 Wallace Tree Multiplication for 4-bits . . . . . . . . . . . . . . . . . . . . . . . . 15
1.22 6 x 6 multiplication table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.23 Wallace Tree Multiplication for 6-bits . . . . . . . . . . . . . . . . . . . . . . . . 16
1.24 Even parity generator using logic gates . . . . . . . . . . . . . . . . . . . . . . . 18
1.25 Odd parity generator logic gates . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.26 One/zero detectors (a) All one detector (b) All zero detector (c) All zero detector
transistor level representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.27 1-bit Digital Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.28 A 3-bit up-counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.29 A 3-bit down-counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.30 A 4bit synchronous upcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.31 Contents of a 4bit upcounter for 16 consecutive clock cycles . . . . . . . . . . . . 23
1.32 Design of synchronous counter using adders and registers . . . . . . . . . . . . . 24

ii
List of Tables

1.1 Truth table for generating even and odd parity bit . . . . . . . . . . . . . . . . 17

iii
 Chapter 1

Data Path Subsystems

1.1 Introduction

Most digital functions can be divided into the following categories:

1. Datapath operators

2. Memory elements

3. Control structures

4. Special-purpose cells

ˆ I/O
ˆ Power distribution
ˆ Clock generation and distribution
ˆ Analog and RF

CMOS system design consists of partitioning the system into subsystems of the
types listed above. Many options exist that make trade-offs between speed, den-
sity, programmability, ease of design, and other variables. This chapter addresses
design options for common datapath operators. The next chapter addresses arrays,
especially those used for memory. Control structures are most commonly coded in
a hardware description language and synthesized.
Datapath operators benefit from the structured design principles of hierarchy,
regularity, modularity, and locality. They may use N identical circuits to process
N-bit data. Related data operators are placed physically adjacent to each other to
reduce wire length and delay. Generally, data is arranged to flow in one direction,
while control signals are introduced in a direction orthogonal to the dataflow.
Common datapath operators considered in this chapter include adders, one/zero
detectors, comparators, counters, shifters, ALUs, and multipliers.

1.2 Shifters

Consider a direct MOS switch implementation of a 4X4 crossbar switch as shown

in Fig. 4.1. The arrangement is quit general and may be readily expanded to
Chapter 1. Data Path Subsystems 1.3. Adders

Figure 1.1: 4 x 4 crossbar switch.

accommodate n-bit inputs/outputs. In fact, this arrangement is an overkill in

that any input line can be connected to any or all output lines-if all switches are
closed, then all inputs are connected to all outputs in one glorious short circuit.
Furthermore, 16 control signals (sw0 0)-sw1 5, one for each transistor switch, must be
provided to drive the crossbar switch, and such complexity is highly undesirable.
An adaption of this arrangement) Recognizes the fact that we can couple the switch
gates together in groups of four (in this case) and also form four separate groups
corresponding to shifts of zero, one, two, and three bits. The arrangement is readily
adapted so that the inlines also run horizontally (to confirm the required strategy).
The resulting arrangement is known as barrel shifter and a 4X4-bit barrel shifter
circuit diagram is given in Fig. 4.2. The interbus switches have their gate inputs
connected in staircase fashion in group of four and there are now four shift control
inputs which must be mutually exclusive in active state. CMOS transmission gates
may be used in place of the simple pass transistor switches if appropriate

1.3 Adders

Addition is one of the basic operation perform in various processing like counting,
multiplication and filtering. Adders can be implemented in various forms to suit
different speed and density requirements.
The truth table of a binary full adder is shown in Figure 4.3, along with some
functions that will be of use during the discussion of adders. Adder inputs: A, B

Prepared by R. Gangadhar Reddy 2

Chapter 1. Data Path Subsystems 1.3. Adders

Figure 1.2: Barrel shifter

Figure 1.3: Full adder truth table

Carry input: SUM

Carry output: CARRY
Generate signal: G(A • B); occurs when CARRY is internally generated within
adder
Propagate signal: P (A + B); when it is 1, C is passed to CARRY. In some adders
A ⊕ B is used as the P term because it may be reused to generate the sum term.

1.3.1 Single-Bit Adders

Probably the simplest approach to designing an adder is to implement gates to

yield the required majority logic functions.
From the truth table these are:

Prepared by R. Gangadhar Reddy 3

Chapter 1. Data Path Subsystems 1.3. Adders

SUM = A.B.C+A.B.C+A.B.C + A.B.C

= C.(A.B + A.B) + C.(A.B+A.B)

= C.(A ⊕ B) + C.(A ⊕ B)

=A⊕B⊕C

CARRY = A.B + A.C + B.C

= A.B + C.(A + B)

= A.B + C.(A + C)

The direct implementation of the above equations is shown in Fig. 4.4 using the
gate schematic and the transistors is shown in Fig. 4.5.

Figure 1.4: Logic gate implementation of 1-Bit adder

Figure 1.5: Transistor implementation of 1-Bit adder

The full adder of Fig. 4.5 employs 32 transistors (6 for the inverters, 10 for the
carry circuit, and 16 for the 3-input XOR). A more compact design is based on the
observation that S can be factored to reuse the CARRY term as follows:

SUM = A.B.C + (A + B + C).CARRY

= A.B.C + (A + B + C).A.B + C.(A + B)

Prepared by R. Gangadhar Reddy 4

Chapter 1. Data Path Subsystems 1.3. Adders

Such a design is shown at the transistor levels in Figure 4.6 and uses only 28
transistors. Note that the pMOS network is complement to the nMOS network.
Here Cin=C

Figure 1.6: Transistor implementation of 1-Bit adder

1.3.2 n-Bit Parallel Adder or Ripple Carry Adder

A ripple carry adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascaded,
with the carry output from each full adder connected to the carry input of the
next full adder in the chain. Figure 4.7 shows the interconnection of four full adder
(FA) circuits to provide a 4-bit ripple carry adder. Notice from Figure 4.7 that the
input is from the right side because the first cell traditionally represents the least
significant bit (LSB). Bits a0 and b0 in the figure represent the least significant bits
of the numbers to be added. The sum output is represented by the bits S0 -S3 .

1.3.3 Carry lookahead adder (CLA)

The carry lookahead adder (CLA) solves the carry delay problem by calculating
the carry signals in advance, based on the input signals. It is based on the fact that
a carry signal will be generated in two cases: (1) when both bits ai and bi are 1, or

Prepared by R. Gangadhar Reddy 5

Chapter 1. Data Path Subsystems 1.3. Adders

Figure 1.7: 4-bit ripple carry adder

(2) when one of the two bits is 1 and the carry-in is 1 . Thus, one can write,

ci+1 = ai .bi + (ai ⊕ bi ).ci

si = (ai ⊕ bi ) ⊕ ci

The above two equations can be written in terms of two new signals Pi and Gi ,
which are shown in Figure 4.8:

Figure 1.8: Full adder stage at i with Pi and Gi shown

ci+1 = Gi + Pi .ci

s i = Pi ⊕ ci

Where
Gi = ai .bi

Pi = (ai ⊕ bi )

Pi and Gi are called carry propagate and carry generate terms, respectively. Notice
that the generate and propagate terms only depend on the input bits and thus will
be valid after one and two gate delay, respectively. If one uses the above expression
to calculate the carry signals, one does not need to wait for the carry to ripple

Prepared by R. Gangadhar Reddy 6

Chapter 1. Data Path Subsystems 1.3. Adders

through all the previous stages to find its proper value. Let’s apply this to a 4-bit
adder to make it clear.
Putting i = 0, 1, 2, 3 in ci+1 = Gi + Pi .ci we get

c1 = G0 + P0 .c0

c2 = G1 + P1 .G0 + P1 .P0 .c0

c3 = G2 + P2 .G1 + P2 .P1 .G0 + P2 .P1 .P0 .c0

c4 = G3 + P3 .G2 + P3 .P2 .G1 + P3. .P2 .P1 .G0 + P3 .P2 .P1 .P0 .c0

Notice that the carry-out bit, ci+1 , of the last stage will be available after four delays:
two gate delays to calculate the propagate signals and two delays as a result of the
gates required to implement Equation c4 .
Figure 4.9 shows that a 4-bit CLA is built using gates to generate the Pi and
Gi and signals and a logic block to generate the carry out signals according to
Equations c1 to c4 .

Figure 1.9: 4-Bit carry lookahead adder implementation in detail

Logic gate and transistor level implementation of carry bits are shown in Figure
4.10.
The disadvantage of CLA is that the carry logic block gets very complicated for
more than 4-bits. For that reason, CLAs are usually implemented as 4-bit modules
and are used in a hierarchical structure to realize adders that have multiples of
4-bits.

Prepared by R. Gangadhar Reddy 7

Chapter 1. Data Path Subsystems 1.3. Adders

(a) Logic network for 4-bit CLA carry bits (b) Sum calculation using CLA network

(c) nFET logic arrays for the CLS terms

Figure 1.10: Carry structures of CLA

Prepared by R. Gangadhar Reddy 8

Chapter 1. Data Path Subsystems 1.3. Adders

1.3.4 Manchester carry chain

This implementation can be very performant (20 transistors) depending on the

way the XOR function is built. The carry propagation of the carry is controlled by
the output of the XOR gate. The generation of the carry is directly made by the
function at the bottom. When both input signals are 1, then the inverse output
carry is 0. In the schematic of Figure 4.11, the carry passes through a complete

Figure 1.11: An adder element based on the pass/generate concept.

transmission gate. If the carry path is precharged to VDD, the transmission gate is
then reduced to a simple NMOS transistor. In the same way the PMOS transistors
of the carry generation is removed. One gets a Manchester cell.

Figure 1.12: Manchester cell

The Manchester cell is very fast, but a large set of such cascaded cells would
be slow. This is due to the distributed RC effect and the body effect making the
propagation time grow with the square of the number of cells. Practically, an
inverter is added every four cells, like in Figure 4.12.

Prepared by R. Gangadhar Reddy 9

Chapter 1. Data Path Subsystems 1.4. Multipliers

Figure 1.13: Cascaded Manchester carry-chain elements with buffering

1.4 Multipliers

In many digital signal processing operations - such as correlations, convolution,

filtering, and frequency analysis - one needs to perform multiplication. The most
basic form of multiplication consists of forming the product of two positive binary
numbers. This may be accomplished through the traditional technique of successive
additions and shifts, in which each addition is conditional on one of the multiplier
bits. Here is an example.

Figure 1.14: 4-bit multiplication

The multiplication process may be viewed to consist of the following two steps:

ˆ Evaluation of partial products.

ˆ Accumulation of the shifted partial products.

It should be noted that binary multiplication is equivalent to a logical AND op-

eration. Thus evaluation of partial products consists of the logical ANDing of the
multiplicand and the relevant multiplier bit. Each column of partial products must
then be added and, if necessary, any carry values passed to the next column.
There are a number of techniques that may be used to perform multiplication.
In general, the choice is based on factors such as speed, throughput, numerical
accuracy, and area. As a rule, multipliers may be classified by the format in which
data words are accessed, namely:-
• Serial form

Prepared by R. Gangadhar Reddy 10

Chapter 1. Data Path Subsystems 1.4. Multipliers

• Serial/parallel form
• Parallel form

1.4.1 Array Multiplication

A parallel multiplier is based on the observation that partial products in the multi-
plication process may be independently computed in parallel. For example, consider
the unsigned binary integers X and Y.

m−1
X n−1
X
i
X= Xi · 2 and Y = Yj · 2j
i=0 j=0

The product is found by

m−1
! n−1
!
X X
P =X × Y = Xi · 2i × Yj · 2j
i=0 j=0
m−1
XX n−1
= (Xi · Yj ) · ·2i+j
i=0 j=0
m+n−1
X
= Pk · 2k
k=0

Thus Pk are the partial product terms called summands. There are mn summands,
which are produced in parallel by a set of mn AND gates.
For 4-bit numbers, the expression above may be expanded as in the table below.

Figure 1.15

An nxn multiplier requires

(n − 1)2 full adders,

n − 1 half adders, and
n2 AND gates.

Prepared by R. Gangadhar Reddy 11

Chapter 1. Data Path Subsystems 1.4. Multipliers

The worst-case delay associated with such a multiplier is (2n + l)tg , where tg is the
worst-case adder delay.
Cell shown in Figure 4.16 is a cell that may be used to construct a parallel
multiplier.

Figure 1.16: Basic cell to construct a parallel multiplier

The Xi term is propagated diagonally from top right to bottom left, while the
yj term is propagated horizontally. Incoming partial products enter at the top.
Incoming CARRY IN values enter at the top right of the cell. The bit-wise AND is
performed in the cell, and the SUM is passed to the next cell below. The CARRY
0UT is passed to the bottom left of the cell.
Figure 4.17 depicts the multiplier array with the partial products enumerated.
The Multiplier can be drawn as a square array, as shown here, Figure 4.18 is
the most convenient for implementation.
In this version the degeneration of the first two rows of the multiplier are shown.
The first row of the multiplier adders has been replaced with AND gates while the
second row employs half-adders rather than full adders.
This optimization might not be done if a completely regular multiplier were
required (i.e. one array cell). In this case the appropriate inputs to the first and
second row would be connected to ground, as shown in the previous slide. An
adder with equal carry and sum propagation times is advantageous, because the
worst-case multiply time depends on both paths.

Prepared by R. Gangadhar Reddy 12

Chapter 1. Data Path Subsystems 1.4. Multipliers

Figure 1.17: Array multiplier

1.4.2 Wallace Tree Multiplication

If the truth table for an adder, is examined, it may be seen that an adder is in
effect a “one’s counter” that counts the number of l’s on the A, B, and C inputs
and encodes them on the SUM and CARRY outputs.
A l-bit adder provides a 3:2 (3 inputs, 2 outputs)compression in the number of
bits. The addition of partial products in a column of an array multiplier may be
thought of as totaling up the number of l’s in that column, with any carry being
passed to the next column to the left.

Prepared by R. Gangadhar Reddy 13

Chapter 1. Data Path Subsystems 1.4. Multipliers

Figure 1.18: Most convenient way for implementation of array multiplier

Figure 1.19

Prepared by R. Gangadhar Reddy 14

Chapter 1. Data Path Subsystems 1.4. Multipliers

Example for implementation of 4x4 multiplier(4-bit) using Wallace Tree Multi-

plication methods

Figure 1.20: Table to find product terms

Considering the product P3, it may be seen that it requires the summation of
four partial products and a possible column carry from the summation of P2.

Figure 1.21: Wallace Tree Multiplication for 4-bits

Example for implementation of 6X6 multiplier(4-bit) using Wallace Tree Multi-

plication methods
Consider the 6 x 6 multiplication table shown below. Considering the product
P5, it may be seen that it requires the summation of six partial products and a
possible column carry from the summation of P4. Here we can see the adders
required in a multiplier based on this style of addition.
The adders have been arranged vertically into ranks that indicate the time at
which the adder output becomes available. While this small example shows the
general Wallace addition technique, it does not show the real speed advantage of
a Wallace tree. There is an identifiable “array part”, and a CPA part, which is at
the top right. While this has been shown as a ripple-carry adder, any fast CPA

Prepared by R. Gangadhar Reddy 15

Chapter 1. Data Path Subsystems 1.5. Parity generator

Figure 1.22: 6 x 6 multiplication table

Figure 1.23: Wallace Tree Multiplication for 6-bits

can be used here. The delay through the array addition (not including the CPA)
is proportional to log1.5(n), where n is the width of the Wallace tree.

1.5 Parity generator

1. Parity is a very useful tool in information processing in digital computers to

indicate any presence of error in bit information.

2. External noise and loss of signal strength cause loss of data bit information
while transporting data from one device to other device, located inside the

Prepared by R. Gangadhar Reddy 16

Chapter 1. Data Path Subsystems 1.5. Parity generator

computer or externally.

3. To indicate any occurrence of error, an extra bit is included with the message
according to the total number of 1s in a set of data, which is called parity.

4. If the extra bit is considered 0 if the total number of 1s is even and 1 for odd
quantities of 1s in a set of data, then it is called even parity.

5. On the other hand, if the extra bit is 1 for even quantities of 1s and 0 for an
odd number of 1s, then it is called odd parity

A parity generator is a combination logic system to generate the parity bit at

the transmitting side.

Table 1.1: Truth table for generating even and odd parity bit

Four bit message

Even parity Odd parity
D3 D2 D1 D0
0000 0 1
0001 1 0
0010 1 0
0011 0 1
01000 1 0
0101 0 1
0110 0 1
0111 1 0
1000 1 0
1001 0 1
1010 0 1
1011 1 0
1100 0 1
1101 1 0
1110 1 0
1111 0 1

If the message bit combination is designated as, D3 D2 D1 D0 and Pe, Po are the
even and odd parity respectively, then it is obvious from the table that the Boolean
expressions of even parity and odd parity are

Pe =D3 D2 D1 D0

Po =(D3 D2 D1 D0 )

The above illustration is given for a message with four bits of information.
However, the logic diagrams can be expanded with more XOR gates for any number
of bits.

Prepared by R. Gangadhar Reddy 17

Chapter 1. Data Path Subsystems 1.6. Zero/One detector

Figure 1.24: Even parity generator using logic gates

Figure 1.25: Odd parity generator logic gates

1.6 Zero/One detector

Detecting all ones or zeros on wide N-bit words requires large fan-in AND or NOR
gates. Recall that by DeMorgan’s law, AND, OR, NAND, and NOR are funda-
mentally the same operation except for possible inversions of the inputs and/or
outputs. You can build a tree of AND gates, as shown in Figure 4.26(b). Here,
alternate NAND and NOR gates have been used. The path has log N stages.

Figure 1.26: One/zero detectors (a) All one detector (b) All zero detector (c) All zero detector
transistor level representation

Prepared by R. Gangadhar Reddy 18

Chapter 1. Data Path Subsystems 1.7. Comparators

1.7 Comparators

Another common and very useful combinational logic circuit is that of the Digital
Comparator circuit. Digital or Binary Comparators are made up from standard
AND, NOR and NOT gates that compare the digital signals present at their input
terminals and produce an output depending upon the condition of those inputs.
For example, along with being able to add and subtract binary numbers we need
to be able to compare them and determine whether the value of input A is greater
than, smaller than or equal to the value at input B etc. The digital comparator
accomplishes this using several logic gates that operate on the principles of Boolean
Algebra. There are two main types of Digital Comparator available and these are.

1. Identity Comparator an Identity Comparator is a digital comparator that has

only one output terminal for when A = B either “HIGH” A = B = 1or “LOW”
A=B=0

2. Magnitude Comparator a Magnitude Comparator is a type of digital com-

parator that has three output terminals, one each for equality, A = B greater
than,A > B and less than A < B

The purpose of a Digital Comparator is to compare a set of variables or unknown

numbers, for example A (A1, A2, A3, . An, etc) against that of a constant or
unknown value such as B (B1, B2, B3, . Bn, etc) and produce an output condition
or flag depending upon the result of the comparison. For example, a magnitude
comparator of two 1-bits, (A and B) inputs would produce the following three
output conditions when compared to each other.

A > B, A + B, A < B

Which means: A is greater than B, A is equal to B, and A is less than B

This is useful if we want to compare two variables and want to produce an
output when any of the above three conditions are achieved. For example, produce
an output from a counter when a certain count number is reached. Consider the
simple 1-bit comparator below.
Then the operation of a 1-bit digital comparator is given in the following Truth
Table.

Prepared by R. Gangadhar Reddy 19

Chapter 1. Data Path Subsystems 1.8. Counters

Inputs Outputs
B A A>B A=B A < B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 0 0

From the above table the obtained expressions for magnitude comparator using
K-map are as follows
For A < B : C = AB
For A = B : D = AB + AB
For A > B : E = AB The logic diagram of 1-bit comparator using basic gates is
shown bellow in Figure 1.24.

Figure 1.27: 1-bit Digital Comparator

*** Draw separate diagrams for grater, equality and less than expressions.

1.8 Counters

Counters can be implemented using the adder/subtractor circuits and registers (or
equivalently, D flip- flops)
The simplest counter circuits can be built using T flip-flops because the tog-
gle feature is naturally suited for the implementation of the counting operation.
Counters are available in two categories

1. Asynchronous(Ripple counters) Asynchronous counters, also known as ripple

counters, are not clocked by a common pulse and hence every flip-flop in the
counter changes at different times. The flip-flops in an asynchronous counter
is usually clocked by the output pulse of the preceding flip-flop. The first
flip-flop is clocked by an external event.

The flip-flop output transition serves as a source for triggering other flip-flops
i.e the C input (clock input) of some or all flip-flops are triggered NOT by the
common clock pulses Eg:- Binary ripple counters, BCD ripple counters

Prepared by R. Gangadhar Reddy 20

Chapter 1. Data Path Subsystems 1.8. Counters

2. Synchronous counters A synchronous counter however, has an internal clock,

and the external event is used to produce a pulse which is synchronized with
this internal clock.

C input (clock input) of all flip-flops receive the common clock pulses

E.g.:- Binary counter, Up-down Binary counter, BCD Binary counter, Ring
counter, Johnson counter,

1.8.1 Asynchronous Up-Counter with T Flip-Flops

Figure 4.28 shows a 3-bit counter capable of counting from 0 to 7. The clock
inputs of the three flip-flops are connected in cascade. The T input of each flip-
flop is connected to a constant 1, which means that the state of the flip-flop will
be toggled at each active edge (here, it is positive edge) of its clock. We assume
that the purpose of this circuit is to count the number of pulses that occur on the
primary input called Clock. Thus the clock input of the first flip-flop is connected
to the Clock line. The other two flip-flops have their clock inputs driven by the Q
output of the preceding flip-flop. Therefore, they toggle their states whenever the
preceding flip-flop changes its state from Q = 1 to Q = 0, which results in a positive
edge of the Q signal.

Figure 1.28: A 3-bit up-counter.

Note here the value of the count is the indicated by the 3-bit binary number
Q2Q1Q0. Since the second flip-flop is clocked by Q0 , the value of Q1 changes
shortly after the change of the Q0 signal. Similarly, the value of Q2 changes shortly
after the change of the Q1 signal. This circuit is a modulo-8 counter. Because it
counts in the upward direction, we call it an up-counter. This behavior is similar
to the rippling of carries in a ripple-carry adder. The circuit is therefore called an
asynchronous counter, or a ripple counter.

Prepared by R. Gangadhar Reddy 21

Chapter 1. Data Path Subsystems 1.8. Counters

1.8.2 Asynchronous Down-Counter with T Flip-Flops

Some modifications of the circuit in Figure 4.29 lead to a down-counter which

counts in the sequence 0, 7, 6, 5, 4, 3, 2, 1, 0, 7, and so on. The modified circuit
is shown in Figure 3. Here the clock inputs of the second and third flip-flops are
driven by the Q outputs of the preceding stages, rather than by the Q outputs.

Figure 1.29: A 3-bit down-counter.

Although the asynchronous counter is easier to construct, it has some major

disadvantages over the synchronous counter.
First of all, the asynchronous counter is slow. In a synchronous counter, all
the flip-flops will change states simultaneously while for an asynchronous counter,
the propagation delays of the flip-flops add together to produce the overall delay.
Hence, the more bits or number of flip-flops in an asynchronous counter, the slower
it will be.
Secondly, there are certain ”risks” when using an asynchronous counter. In
a complex system, many state changes occur on each clock edge and some ICs
respond faster than others. If an external event is allowed to affect a system
whenever it occurs (unsynchronized), there is a small chance that it will occur near
a clock transition, after some IC’s have responded, but before others have. This
intermingling of transitions often causes erroneous operations. And the worse this
is that these problems are difficult to foresee and test for because of the random
time difference between the events.

1.8.3 Synchronous Counters

A synchronous counter usually consists of two parts: the memory element and the
combinational element. The memory element is implemented using flip-flops while
the combinational element can be implemented in a number of ways. Using logic
gates is the traditional method of implementing combinational logic and has been
applied for decades.

Prepared by R. Gangadhar Reddy 22

Chapter 1. Data Path Subsystems 1.8. Counters

1.8.4 Synchronous Up-Counter with T Flip-Flops

An example of a 4-bit synchronous up-counter is shown in Figure 5. Observing the

Figure 1.30: A 4bit synchronous upcounter

Figure 1.31: Contents of a 4bit upcounter for 16 consecutive clock cycles

pattern of bits in each row of the table, it is apparent that bit Q0 changes on each
clock cycle. Bit QQ1 changes only when Q0 = 1. Bit Q2 changes only when both Q1
and Q0 are equal to 1. Bit Q3 changes only when Q2 = Q1 = Q0 = 1. In general, for
an n-bit up-counter, a give flip-flop changes its state only when all the preceding
flip-flops are in the state Q = 1. Therefore, if we use T flip-flops to realize the 4-bit
counter, then the T inputs should be defined as

T0 = 1

T1 = Q0

T2 = Q0 Q1

T3 = Q0 Q1 Q2

In Figure 5, instead of using AND gates of increased size for each stage, we use a
factored arrangement. This arrangement does not slow down the response of the

Prepared by R. Gangadhar Reddy 23

Chapter 1. Data Path Subsystems 1.8. Counters

counter, because all flip-flops change their states after a propagation delay from
the positive edge of the clock. Note that a change in the value of Q0 may have to
propagate through several AND gates to reach the flip-flops in the higher stages of
the counter, which requires a certain amount of time. This time must not exceed
the clock period. Actually, it must be 3less than the clock period minus the setup
time of the flip-flops. It shows that the circuit behaves as a modulo-16 up-counter.
Because all changes take place with the same delay after the active edge of the
Clock signal, the circuit is called a synchronous counter.

Figure 1.32: Design of synchronous counter using adders and registers

Prepared by R. Gangadhar Reddy 24