VLSI Lab Manual

EXPERIMENT NO.1
INVERTER SIMULATION AND SYNTHESIS
Aim: To Design an inverter using Verilog and simulate the design using Verilog test bench
and observe functionality of the inverter in Linux environment.

Tools used: Model sim

Editor used:Vi
Coding: Verilog
Model: Behavioral

Logic Diagram Truth Table

input_i output_o input_i output_o

0 1
1 0
Program
module inverter( input_i, output_o);
inputinput_i;
outputoutput_o;
regoutput_o;

always@(input_i)
begin
if(input_i)
output_o=1'b0;
else
output_o=1'b1;
endendm
odule
Test Bench
moduleinverter_tb;
reginput_i;
wireoutput_o;

inverterdut (input_i, output_o);

initial
input_i=1'b0;
always #5 input_i= ~ input_i;
initial

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begin
$monitor( $time, " input_i=%b and output_o=%b ", input_i,output_o);
endend
module

Expected Waveforms:

Actual Waveforms:

Synthesis Output:

Result :

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EXPERIMENT NO.2
BUFFER SIMULATION AND SYNTHESIS
Aim:To Design a buffer using Verilog and simulate the design using Verilog test bench
and observe functionality of the buffer in Linux environment.

Logic Diagram Truth Table

input_i output_o input_i output_o

0 0
1 1
Program

module buffer( input_i, output_o);

inputinput_i;
output output_o;
reg output_o;

always @(input_i)
begin
if(input_i)
output_o=1'b1;
else
output_o=1'b0;
end
endmodule

Test Bench
module buffer_tb;
reg input_i;
wire output_o;

buffer dut (input_i, output_o);

initial
input_i=1'b;
always #5 input_i=~ input_i;
initial
begin
$monitor( $time, " input_i=%b and output_o=%b ", input_i,output_o);
end
endmodule

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Expected Waveforms:

Actual Waveforms:

Synthesis Output:

Result :

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EXPERIMENT NO.3
TRANSMISSION GATE SIMULATION AND SYNTHESIS

Aim: To Design a Transmission Gate using Verilog and simulate the design using Verilog
testbench and observe the functionality of the Transmission Gate in Linux environment.

Program

module transmission_gate (in, control, out);

input in, control;
output out;
reg out;

always @ (in)
begin
if(control)
out=in;
else
out=1'b0;
end
endmodule

Test Bench

module transmission_gate_tb;
reg in, control;
wire out;
transmission_gate dut(in, control, out);
initial in=1'b1;
always #5 in=~in;
initial
begin
#20 control=1'b1;
#20 control=1'b0;

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end
endmodule

Expected Waveforms:

Actual Waveforms:

Synthesis Output:

Result :

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EXPERIMENT NO.4
BASIC GATES SIMULATION AND SYNTHESIS

Aim: Design and simulate all basic and universal gates in one of the following modeling
styles(Behavioral, Data flow or Structural) using Verilog.

Logic Diagram

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Program

module basic_gates (a, b, c, d, e, f, g, h);

input a, b;
output c, d, e, f, g, h;

assign c=~a;
assign d=a&b;
assign e=a|b;
assign f=~(a&b);
assign g=~(a|b);
assign h=a^b;
endmodule

Test Bench
module basic_gates_tb; reg
a, b;
wire c, d, e, f, g, h;

basic_gates dut (a, b, c, d, e, f, g, h);

initial
begin
a=1'b0;b=1'b0;
#20a=1'b1; b=1'b0;
#20 a=1'b0; b=1'b1;
#20 a=1'b1; b=1'b1;
end
initial
begin

$monitor ($time, " a=%b b=%b (not_gate)c=%b (and_gate)d=%b (or_gate)e=%b

(nand_gate)f=%b (nor_gate)g=%b (xor_gate)h=%b",a,b,c,d,e,f,g,h);

end
endmodule

Expected Waveforms

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Actual Waveforms:

Synthesis Output:

Result :

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EXPERIMENT NO.5
FLIP FLOPS SIMULATION AND SYNTHESIS

(i) RS-Flip Flop

Aim: Design and simulate SR Flip Flop in one of the following modeling styles

(Behavioral,Data flow or Structural) using Verilog.

Block Diagram Truth Table

Program

modulers_ff(rs, clock, q, qb);

input [1:0] rs;
input clock;
output q, qb;
reg q, qb;

always @ (posedge clock)

begin
case (rs)
2'b00 : q = q ;
2'b01 : q = 1'b1 ;
2'b10 : q = 1'b0 ;
2'b11 : q = 1'dZ ;
endcase
qb =~ q;
end
endmodule

Test Bench

modulers_ff_tb;
reg [1:0] rs;

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reg clock;
wire q, qb;

rs_ff dut(rs, clock, q, qb);

nitial
clock=1'b1;
always #5 clock=~clock;
initial
begin
rs=2'b00; #20;
rs =2'b01; #20;
rs =2'b10;#20;
rs =2'b11;#50;
end
initial
$monitor ($time, "rs=%b q=%b qb=%b ", rs, q, qb);

endmodule

Expected Waveforms:

Actual Waveforms:

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Synthesis Output:

Result:

(ii) D Flip Flop

Aim: Design and simulate D FLIP FLOP in one of the following modelingstyles (Behavioral
Data flow or Structural) using Verilog.

Block DiagramTruth Table

Program

module dff (reset, clock, d, q, qb);

input reset, clock, d;
output q, qb;
reg q;
wireqb;
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always@ (posedge clock)

begin
if (reset)
q<=1'b0;
else
q<=d;
end

assign qb=~q;
endmodule

Test Bench

module dff_tb;
reg clock, reset, d;
wire q, qb;

dff dut (reset, clock, d, q, qb);

initial
begin
clock=1'b1;
reset=1'b0;
end
always #5 clock=~clock;
always #40 reset=~reset;
initial
begin

#20 d =1'b1;
#20 d =1'b0;
#30 d =1'b1;
#30 d =1'b0;

end

initial
begin
$monitor ($time, "reset=%b clock=%b d=%b q=%b qb=%b", reset, clock, d,
q, qb);
end
endmodule

Expected Waveforms:
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Actual Waveforms:

Synthesis Output:

Result:

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(iii) T Flip Flop

Aim: Design and simulate T FLIP FLOP in one of the following modelingstyles (Behavioral,
Data flow or Structural) using Verilog.

Block DiagramTruth Table

Clk T q qb

0 Hold

1 Toggle

Program

module T_FF (T, clock, q, qb);

inputT;
input clock;
output q, qb;
reg q, qb;

always @ (posedge clock)

begin
case (T)
1'b0 : q = q;
1'b1 : q = ~ q;

endcase
qb =~ q;
end
endmodule

Test Bench

module T_ff_tb;
reg T;
reg clock;
wire q, qb;

T_FF dut(T, clock, q, qb);

initial
clock=1'b1;
always #5 clock=~clock;
initial
begin
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T=1'b0; #20;
T=1'b1; #20;
T=1'b0; #20;
T=1'b1; #20;
end
initial
$monitor ($time, "T=%b q=%b qb=%b ", T, q, qb);

endmodule

Expected Waveforms:

Actual Waveforms:

Synthesis Output:

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VLSI Lab Manual

Result:

(iv) JK Flip Flop

Aim: Design and simulate JK Flip Flop in one of the following modelingstyles (Behavioral,
Data flow or Structural) using Verilog.

Block Diagram Truth Table

Program:

module JK_FF (JK, clock, q, qb);

input [1:0] JK;
input clock;
outputq, qb;
reg q, qb;

always @ (posedge clock)

begin
case (JK)

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2'b00 : q = q;
2'b01 : q = 1'b0;
2'b10 : q = 1'b1;
2'b11 : q =~ q;
endcase
qb =~ q;
end
endmodule

Test Bench

moduleJK_ff_tb;
reg [1:0] JK;
reg clock;
wire q, qb;

JK_FF uut(JK, clock, q, qb);

initial
clock=1'b1;
always #5 clock=~clock;
initial
begin
JK=2'b00; #20;
JK=2'b01; #20;
JK=2'b10; #20;
JK=2'b11; #50;
end
initial
$monitor ($time, "JK=%b q=%b qb=%b ", JK, q, qb);

endmodule

Expected Waveforms:

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Actual Waveforms:

Synthesis Output:

Result:

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(v) MS Flip Flop

Aim: Design and simulate MS-JK Flip Flop in one of the following modelingstyles
(Behavioral,Data flow or Structural) using Verilog.

Block Diagram

Program

(i) d_flip flop

moduled_ff (reset, clock, d, q, qb);

input reset, clock, d;
output q, qb;
reg q;
wireqb;

always @ (posedge clock)

begin
if (reset)
q<=1'b0;
else q<=d;
end

assignqb=~q;
endmodule

(ii) Master slave_flip flop

module msflipflop (reset, clock, d,q, qb);

input reset, clock, d;
output q,qb;

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wire q;
wire qb;
wire w1,w2;
d_ff master(.reset(reset), .clock(clock), .d(d), .q(w1), .qb(w2));
d_ff slave (.reset(reset), .clock(~clock),.d(w1),.q(q), .qb(qb));

endmodule

Test Bench

module ms_ff_tb;
regreset,clock,d;
wire q,qb;

msflipflop dut(reset,clock,d,q,qb);

initial
clock=1'b1;
always #5 clock=~clock;

initial
begin
reset=1'b1; d=1'b0; #40;
reset=1'b1; d=1'b1; #40;
reset=1'b0; d=1'b0; #40;
reset=1'b0; d=1'b1; #40;
reset=1'b0; d=0'b0; #40;
reset=1'b0; d=1'b1; #40;
end

initial
$monitor($time,"reset=%b d=%b q=%b qb=%b", reset, d, q, qb);

endmodule

Expected Waveforms:

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Actual Waveforms:

Synthesis Output:

Result:

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EXPERIMENT NO.6
ADDER DESIGN AND SIMULATION

i) Parallel Adder

a) Ripple Carry Adder

Aim:Design a Ripple carry adder with full adder in one of the following modeling
styles (Behavioral, Data flow or Structural) using Verilog.

Block Diagram

sum[3] sum[2] sum[1] sum[0]

sum sum sum sum

fa3 cin w3 fa2 cin w2 fa1 cin w1 fa0 cin
cin
carry carry carry carry

a b a b a b a b

a[3] b[3] a[2] b[2] a[1] b[1] a[0] b[0]

Program

(i) full_adder

module full_adder (a, b, cin, sum,carry);

input a, b, cin;
output sum, carry;
assign sum=a ^ b^ cin;
assign carry= (a & b)| (b &cin) | (cin& a);
endmodule

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(ii) 4bit_serial_full_adder
module fa_parallel_4bit (a, b, cin, sum,carry);
input [3:0] a,b;
input cin;
output [3:0] sum;
output carry;
wire [3:1] w;

full_adder fa0(.a(a[0]),.b(b[0]),.cin(cin),.sum(sum[0]),.carry(w[1]));
full_adder fa1(.a(a[1]),.b(b[1]),.cin(w[1]),.sum(sum[1]),.carry(w[2]));
full_adder fa2(.a(a[2]),.b(b[2]),.cin(w[2]),.sum(sum[2]),.carry(w[3]));
full_adder fa3(.a(a[3]),.b(b[3]),.cin(w[3]),.sum(sum[3]),.carry(carry));

endmodule

Test Bench
module fa_parallel_4bit_tb;
reg [3:0] a,b;
reg cin;
wire [3:0] sum;
wire carry;

fa_parallel_4bit uu1(a, b, cin, sum, carry);

initial
begin
a=4'b0111; b=4'b0100; cin=1'b0;#10;
a=4'b1011; b=4'b0110; cin=1'b1;
end

initial
$monitor ($time, "a=%b b=%b cin=%b sum=%b carry=%b",
a, b, cin, sum, carry);

endmodule

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Expected Waveforms:

Actual Waveforms:

Synthesis Output:

Result:

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VLSI Lab Manual

b) Carry Look Ahead Adder

Aim: Design a Carry look ahead adder in one of the following modeling style (Behavioral,
Data flow or Structural) using Verilog.

Block diagram

Carry Generator

P(2) g(2) P(1) g(1) P(0) g(0)

sum(2) sum(1) sum(0)

Cout

c(1) c(0) cin

1-Bit Adder 1-Bit Adder 1-Bit Adder

x(2) y(2) x(1) y(1) x(0) y(0)

Program

module paraller_adder (x, y,cin, sum, cout);

input [2:0] x,y;
input cin;
output [2:0] sum;
output cout;

wire c0, c1; wire [2:0] p, g;

assign g[0]= x[0] & y[0];

assign g[1]= x[1] & y[1];
assign g[2]= x[2] & y[2];

assign p[0]= x[0] | y[0];

assign p[1]= x[1] | y[1];
assign p[2]= x[2] | y[2];

assign c0= g[0] | (p[0] & cin);

assign c1= g[1] | (p[1] & g[0]) | (p[1] & p[0] &cin);

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assign cout= g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] &cin);
assign sum[0]= x[0] ^ y[0] ^ cin;
assign sum[1]= x[1] ^ y[1] ^ (g[0] | (p[0] &cin));
assign sum[2]= x[2] ^ y[2] ^ (g[1] | (p[1] & g[1]) | (p[1] & p[0] &cin));

endmodule

Test Bench

module paraller_adder_tb;
reg [2:0] x,y;
reg cin;
wire [2:0] sum;
wire cout;

paraller_adder uut (x, y,cin, sum, cout);

initial begin
x=3'b111; y=3'b100; cin=1'b0;
#10; x=3'b101; y=3'b110; cin=1'b1;
end
initial

$monitor ($time, " x=%b y=%b cin=%b sum=%b cout=%b" , x, y, cin, sum,
cout);

endmodule

Expected Waveforms:

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Actual Waveforms:

Synthesis Output:

Result :

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ii Serial Adder
Aim:Design a Serial adder in one of the following modelingstyles (Behavioral, Data flow or
Structural) using Verilog.

Block Diagram

Program for shift register

module shift_reg(data,load,E,w,clock,q);
parameter n=8;
input [n-1:0] data;
inputload,E,w,clock;
output [n-1:0] q;
reg [n-1:0] q;
integer k;

always @(posedge clock)

if (load)
q <= data;
else if (E)
begin
for (k=n-1;k>0;k=k-1)
q[k-1] <= q[k];
q[n-1] <= w;
end
endmodule

Program for Serial Adder[8 bit]

module serial_adder ( A, B, reset, clock, sum, cout);

input [7:0] A, B;
input reset, clock;
output [7:0] sum;
output cout;
reg [3:0] count;

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reg s,y,Y;
wire [7:0] qa, qb, sum;
wire run;

parameter G=0, H=1;

shift_regshift_A (.data(A), .load(reset), .E(1'b1), .w(1'b0), .clock(clock), .q( qa));
shift_regshift_B (.data(B), .load(reset), .E(1'b1), .w(1'b0), .clock(clock), .q( qb));
shift_regshift_sum (.data(8'd0), .load(reset), .E( run),.w(s), .clock)clock),.q( sum));

//adder fsm
//output and next state combinational circuit
always @(qa or qb or y)
case (y)
G: begin
s = qa[0]^qb[0];
if (qa[0] &qb[0])
Y = H;
else
Y = G;
end

H: begin
s = qa[0] ~^qb[0];
if (~qa[0] & ~qb[0])
Y =G;
else
Y = H;
end

default : Y = G;
endcase

//sequential block
always @(posedge clock) if
(reset)
y <= G;
else
y <= Y;
assign cout=y;

//control the shifting process

always @(posedge clock)
if (reset)
count = 8;
else if (run) count = count - 1;
assign run=|count;
endmodule

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Test Bench
module serial_adder_tb ;
reg [7:0] A,B;
reg reset,clock;
wire [7:0] sum ;
wire cout;

serial_adder dut (A, B, reset, clock, sum, cout);

initial
clock = 1'b1;
always #5 clock =~clock;
initial
begin
reset = 1'b0;A = 8'b10101010; B = 8'b11111111;
#20 reset = 1'b1;
#20 reset = 1'b0;
#80 $finish;
end

initial
$monitor ($time, " SUM = %d cout=%b", sum, cout);

endmodule

Expected Waveform

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Actual Waveforms:

Synthesis Output:

Result :

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EXPERIMENT NO.7
COUNTER DESIGN AND SIMULATION
i.Synchronous Counter
Aim: Design and Simulate synchronous counter in the following modelingstyles
(Behavioral) using Verilog.

Block Diagram

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Program

module counter ( clock, reset, up, down, count);

input clock, reset, up, down;
output[3:0] count;
reg [3:0] count;

always @ (posedge clock)

begin
if(reset)
count=4'b0000;

else if (up && ~down)

count= count+1'b1;

else if (down && ~up)

count= count-1'b1;

else
count=count;
endendm
odule

Test Bench

module counter_tb;
reg clock, reset, up, down;
wire [3:0]count;

counter dut (clock, reset, up, down, count);

initial
clock=1'b0;
always #5 clock=~clock;

initial
begin
reset=1'b1; up=1'b0; down=1'b1;#50;
reset=1'b0;
up=1'b1; down=1'b0; #500;
up=1'b0; down=1'b1; #500;
up=1'b1; down=1'b1; #50;
end
initial
$monitor( $time, " reset=%b up=%b down=%b count=%b" ,reset, up, down, count);
endmodule

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Expected Waveform

Actual Waveforms:

Synthesis Output:

Result:

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ii. Asynchronous Counter

Aim: Design an Asynchronous counter in the behavioral modeling stylesusing Verilog.

Block Diagram

Program

(i) T_Flip Flop

module t_ff (clock, reset, T, q);

input clock, reset, T;
output q;
reg q;
always @ (posedge clock)
begin
if(reset)
q<=1'b0;
else if (T)

q<=~q;
else
q<=q;
end
endmodule

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(ii) 4bit-counter

module asyn_counter (clock, reset, count);

input clock, reset;
output [3:0] count;

t_ffT1(.clock(clock), .reset(reset),.T(1'b1),.q( count[0]));

t_ffT2(.clock(~count[0]), .reset(reset),.T(1'b1),.q(count[1]));
t_ff T3(.clock(~count[1]), .reset(reset),.T(1'b1),.q( count[2]));
t_ff T4(.clock(~count[2]), .reset(reset),.T(1'b1),.q( count[3]));
endmodule

Test Bench

module asyn_counter_tb;
reg clock, reset;
wire [3:0] count;
asyn_counter dut(clock, reset, count);
initial clock=1'b0;
always #10 clock=~clock;
initial
begin
#20; reset=1'b1;
#20; reset=1'b0;
end
initial
$monitor( $time, " reset=%b count = %b" ,reset, count);

endmodule

Expected Waveforms

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Actual Waveforms:

Synthesis Output:

Result:

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EXPERIMENT NO.8
SUCCESSIVE APPROXIMATION REGISTER [SAR] DESIGN AND
SIMULATION
Aim: Design Successive Approximation Register in the behavioral modeling stylesusing
Verilog.

Flow chart

Shifting Operation

Program

module sar (data,load,E,w,clock,q);

parameter n=8;
input [n-1:0] data;

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input load, E, w, clock;

output [n-1:0] q;
reg [n-1:0] q;
integer k;

always @(posedge clock)

if (load)
q <= data;
else if (E)
Begin
for (k=n-1;k>0;k=k-1)
q[k-1] <= q[k];
q[n-1] <= w;
end
endmodule

Test Bench

module sar_tb;

reg [7:0] data;

reg load;
reg E;
reg w;
reg clock;
wire [7:0] q;

sar dut(.data(data),.load(load),.E(E),.w(w),.clock(clock),.q(q));

initial
clock=1'b1;
always #5 clock = ~clock;
initial
begin
load = 1'b1;
w = 1'b0;
E = 1'b0;
#5 data = 8'b11110000;
#10 load = 1'b0;
E = 1'b1;
w = 1'b0;
#10 w = 1'b0;
#10 w = 1'b0;
#10 w = 1'b0;
#10 w = 1'b1;

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#10 w = 1'b1;
#10 w = 1'b1;
#10 w = 1'b1;
end
endmodule
Expected Waveforms

Actual Waveforms:

Synthesis Output:

Result:

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VLSI Lab Manual

STEPS FOR SYNTHESIS

Step 1. Open a terminal and type the following commands:

[root@localhost ~]# csh

[root@localhost ~]# sourceams.cshrc
Welcome to mentor graphics Tool brought to you by Tridents Tech Labs Pvt
Ltd [root@localhost ~]#spectrum
Messages will be logged to file '/root/leospec.log'...
LeonardoSpectrum Level 3 - 2010a.7 (Release Production Release, compiled Jun 30
2010 at 15:05:46)
Copyright 1990-2010 Mentor Graphics. All rights reserved.
Portions copyright 1991-2010 Compuware Corporation

Checking Security...

** Welcome to Interactive Leonardo Spectrum Level 3 Version 2010a.7 ***

News :
* Enter "help" to get an overview of all commands
* Enter <command> -help to get usage of each command

Session history will be logged to file '/root/leospec.his'

This will open the Leonardo Spectrum synthesis tool.

Step 2. Loading the library:

LEONARDO {1}: load_library/root/tsmc018_typ.syn

Reading library file `/root/libraries/tsmc018_typ.syn`...
Library version = v3.1 Release : Patch (a) : (Aug 26, 2005)
Delays assume: Process=typical Temp= 0.0 C Voltage=1.80 V
Info: setting encoding to auto
Info, Command 'load_library' finished successfully

Step 3. Reading the Verilog file to be synthesized:

LEONARDO {2}: read -format verilog /root/folder_name/file_name.v

-- Reading file '/ root/folder_name/file_name.v'...
-- Loading module ''file_name'
-- Compiling root module 'file_name'
Info, Command 'read' finished successfully

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Step 4. Using elaborate and optimize commands:

LEONARDO {3}: elaborate

-- Compiling root module 'file_name'
-- Info, replacing file_name (INTERFACE)
Info, Command 'elaborate' finished successfully

LEONARDO {4}: optimize

Info: The target technology was not selected, tsmc018_typ was automatically
selected for you.
NO wire table is found
-- Optimizing netlist .work.file_name.INTERFACE
-- Automatic IO buffer insertion...
WARNING: cannot do IO mapping. Library has no plain input IO buffer
-- Matching combinational logic..
-- Matching non-combinational logic..
-- Covering..
-- CPU Time used : 00:00 Mapping
-- Final Design Rule Check..
Info, Command 'optimize' finished successfully

Step 5. Viewing the reports (area& delay):

LEONARDO {5}: report_area

*******************************************************

Cell: and_gate View: INTERFACE Library: work

*******************************************************

Number of ports : 3
Number of nets : 3
Number of instances : 1
Number of references to this view : 0

Total accumulated area :

Number of gates : 1
Number of accumulated instances : 1
Info, Command 'report_area' finished successfully

LEONARDO{6}: report_delay
NO wire table is found
Critical Path Report

Critical path #1, (unconstrained path)

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NAME GATE ARRIVAL LOAD

------------------------------------------------------------------------------
a/ 0.00 0.00 dn 0.01
ix1/Y and02 0.06 0.06 dn 0.00
c/ 0.00 0.06 dn 0.00
data arrival time 0.06

data required time not specified

------------------------------------------------------------------------------
data required time not specified
data arrival time 0.06
----------
unconstrained path
------------------------------------------------------------------------------

Critical path #2, (unconstrained path)

NAME GATE ARRIVAL LOAD
------------------------------------------------------------------------------
b/ 0.00 0.00 up 0.01
ix1/Y and02 0.05 0.05 dn 0.00
c/ 0.00 0.05 dn 0.00
data arrival time 0.05

data required time not specified

------------------------------------------------------------------------------
data required time not specified
data arrival time 0.05
----------
unconstrained path
-----------------------------------------------------------------------------

Info, Command 'report_delay' finished successfully

Step 6. Writing the synthesized file to the desired location:

LEONARDO {7}: write -format verilog /root/folder_name/file_name_syn.v

-- Writing file /root/folder_name/file_name_syn.v
Info, Command 'write' finished successfully
LEONARDO {8}: exit

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VLSI Lab
Manual

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ECE,AMCEC
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VLSI Lab Manual

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