Lecture-34

UNSPECIFIED OP CODES OF THE 8085A

If one examines the instruction set of 8085A, one finds that out of the
256 possible opcode with 8-bits, Intel had announced only 246
opcodes or 246 instructions. There are no instructions in the
instruction set corresponding to the 10 missing opcodes. Users have
since reported that Intel 8085A does have instructions corresponding
to these missing opcodes. These instructions reduce the program
length as well as execution time. The flags specified by Intel are S, Z,
AC, P, CY located in the flag register as

S Z X AC X P X CY

Users have reported that there are two more flag bits, at bit-1 and bit-
5 positions, having same useful meaning.

S Z X5 AC X P V CY
where,
V = Overflow bit. This bit is set to 1 if overflow occurs in 2‟s
complement addition/ subtraction/ DCX/ INX for 8 and 16-
arithmetic operation.
X5 = This bit has been named for its position in the flag register. It
does not resemble any normal flag but this bit is affected as per the
following expression.
X5 = S1.S2 + S1.R + S2.R
where, S1= sign of operand 1
S2= sign of operand 2
R = sign of result.
For subtraction & comparison, replace S1 by S2 where operand 2 is
the subtrahend i.e., Result = Operand 1- Operand 2.
The only use for this bit is found as an unsigned overflow indication
resulting from a data change of FFFFH to 0000H on executing the
instruction INX and as an unsigned underflow indicator from a data
change of 0000H to FFFFH on executing DCX.
The ten new instructions, include seven opcode that involve
the processing of register pairs, two that involve jump operation with
X5 flag bit and one that performs a conditional restart on the overflow
flag bit V. The various instructions are discussed below:
1. DSUB: (Double byte subtraction): This is a single byte instruction.
The meaning of the instruction is that the contents of register pair
(B,C) are subtracted foam the contents of register pair (H,L) and
result is stored back in register pair (H,L). The macro RTL
implements is
(H, L) (H, L) - (B, C)
The opcode of the instruction is (0B)H. All seven condition flag are
affected as per the result. It requires 3 machine cycles OFMC & two
BIMC and 10 states similar to DAD rp instruction. The addressing
mode is register addressing mode.
In the absence of this instruction, the operation can be
performed by writing a sequence of specified instructions as below:
MOV A, L
SUB C
MOV L, A
MOV A, H
SBB B
MOV H, A
The length of the program as well as execution time both increases.
2. ARHL: (Arithmetic Right-shift HL register pair) This is a single
byte instruction. The meaning of the instruction is that the contents of
register pair (H, L) are shifted right arithmetically by one bit. The
upper most bit is duplicated and the lower bit is shifted into the carry
bit. The result is placed back into the (H, L) register pair. The macro
RTL implemented is
(H7) (H7), (Hn-1) (Hn),
(L7) (H0), (Ln-1) (Ln), (CY) (L0)
The opcode of the instruction is (10)H. Only (CY) flag is affected. It
requires 2 machine cycles OFMC and one BIMC and 7 states. The
addressing mode is register addressing mode.
In the absence of this instruction, the operation can be
performed by writing a sequence of specified instructions as below:
MOV A, H
RAL
MOV A, H
RAR
MOV H, A
MOV A, L
RAR
MOV L, A

The length of the program as well as execution time both increases.

3. RDEL: (Rotate (D,E) register pair left through carry) This is a

single byte instruction. The operation code is 18H. The meaning of the
instruction is “Rotate the contents of register pair (D, E) left by one bit
through the carry flag”. The lower order bit is set equal to the CY flag
and the CY flag is set to the value shifted out of the higher order bit.
The result is placed book into the DE register pair. The macro RTL
implemented is
(CY) (D7), (Dn+1) (Dn),
(D0) (E7), (En+1) (En), (E0) (CY)
Only the CY flag and the V flag bits are affected. It requires three
machine cycles OFMC & 2 BIMC and a total of 10 states. The
addressing mode is register addressing mode.

4. LDHI: (Load (D, E) register pair with (H, L) plus 8-bit immediate
data). This is a 2 byte instruction. The operation code format is
28 N
<B2> N+1
The macro RTL implemented is
(D, E) (H, L) + <B2>
The meaning of the instruction is the contents of register pair (H, L)
are added to the 8-bit immediate data byte and the result is stored in
register pair (D, E). No condition flags are affected.
It requires three machine cycles OFMC, one MRMC & one
BIMC and a total of 10 states. The addressing mode is immediate &
register addressing mode the second byte is called offset.
5. LDSI: (Load (D, E) register pair with (SP) plus 8-bit immediate
data byte). This is two byte instruction. The opcode format is

38 N
<B2> N+1

The macro RTL implemented is

 (D,E) (SP) + <B2>

The meaning of the instruction is “Add the contents of register pair

(SP) to the 8-bit data byte immediately available as a2ndbyte of the
instruction & store the result in register pair (D,E)”. No condition flag
are affected.
It requires 3 machine cycles OFMC,1 MRMC and 1 BIMC and a
total of 10 states. The addressing mode is immediate register
addressing mode.

6. RST V (Restart on overflow). This is a single byte instruction. The

opcode is (CS)H. the meaning is the overflow flag V is set, the actions
specified above are performed, otherwise control continues
sequentially. The macro RTL implemented is shown below:
If overflow flag V=1
M[(SP) – 1] (PCH)
M[(SP) – 2] (PCL)
(SP) (SP) – 2
(PC) 0040H
Otherwise
(PC) (PC) + 1
where (PC) on right hand side is having the address of the opcode.
It requires 1 or 3 machine cycles and 6 or 12 states. The addressing
mode is register indirect addressing mode. None of the flags are
affected.
7. SHLX: (Store (H,L) register pair indirect through (D,E) register
pair). This is a single byte instruction. The opcode is (D9)H. The
meaning of the instruction is “Move the content of register (L) to the
memory location whose address is in (D,E) register pair and move
the content of register (H) to the memory location whose address is
one more than the (D,E) register pair. The macro RTL implemented is
M [(D,E)] (L)
M [(DE) + 1] (H)
It requires 3 machine cycles OFMC & two MWRMC and a total
of 10 states. The addressing mode is register indirect addressing
mode. None of the flags are affected.

8. JNX5: (Jump on not X5) This is a 3-byte conditional jump

instruction. The operation code format is

DD N
<B2> N+1
<B3> N+2

This instruction tests the X5 bit. If the X5 bit is „0‟, the control is
transferred to the instruction whose address is specified in 2nd byte &
3rd byte of the instruction, otherwise control continues sequentially.
The macro RTL implemented is shown below:
If X5 flag = 0
(PCL) <B2>
(PCH) <B3>
otherwise
(PC) (PC) + 3
where (PC) on right hand side is having the address of the opcode.
It requires 2 or 3 machine cycle of 7 or 10 states depending on
whether the condition is TRUE or not. The addressing mode is
immediate mode. No flag is affected.

9. JX5: (Jump on X5) This is also a 3-byte conditional jump

instruction. The operation code format is

FD N
<B2> N+1
<B3> N+2

This instruction tests the X5 bit. If the X5 bit is „1‟, the control is
transferred to the instruction whose address is specified in 2nd byte &
3rd byte of the instruction, otherwise control continues sequentially.
The macro RTL implemented is shown below:
If X5 flag = 1
(PCL) <B2>
(PCH) <B3>
otherwise
(PC) (PC) + 3
where (PC) on right hand side is having the address of the opcode.
It requires 2 or 3 machine cycle of 7 or 10 states depending on
whether the condition is TRUE or not. The addressing mode is
immediate mode. No flag is affected.

10. LHLX: (Load (H,L) register pair indirect through (D,E) register
pair) This is a single byte instruction. The operation code is EDH. The
meaning of the instruction is “Load (L) register with the content of the
memory location whose address is in (D,E) register pair and load (H)
register with the content of the memory location whose address is
one more the contents of (D,E) register”. The macro RTL
implemented is
(L) M [(D, E)]
(H) M [(D, E) +1]
The instruction requires 3 machine cycles OFMC & two MRMC and
10 states. The addressing mode is register indirect addressing mode.
None of the flags are affected in this instruction.