l Applications

l Why Two Fault Simulators Never Agree

l General Techniques
l Parallel Pattern Simulation
l Inactive Fault Removal
l Critical Path Tracing
l Fault Sampling
l Statistical Fault Analysis

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 l Fault grading a test set
l An aid to an ATPG
l Generates knowledge used in some ATPG
systems
l Used to compute coverage loss due to
signature analysis
l Generates fault dictionaries for use in fault
diagnosis and location

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 l Since ATPG is much slower than fault simulation,
the fault list is trimmed with use of a fault simulator
after each vector is generated
Select Fault
List Remove all
Next
Detected
Fault
Faults

Test Fault
Generator Simulator

Add Fault
Vectors Simulate
Test
to Test Set Vectors
Set

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 l It has been shown that the quality of a shipped part
heavily depends on the quality of a test.
¨ Defect Level = Reject Rate = shipped defective parts
total parts shipped as good
¨ c = single stuck-at fault coverage
¨ d = defect coverage
¨ Assumption: c » d
¨ Y = inherent yield of a process = % of chips that are good
¨ defect level = 1 - Y1-c
¨ Current defect levels are 100 to 200 per million.
1 decreasing
yield
defect
level
80 100
c
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50
University of Toronto
 l They simulate different sets of faults.
l Some report coverage on the collapsed fault list
rather than the complete (uncollapsed) list.
l Fault collapsing algorithms may differ.
¨ Some count ALL gate input and output faults as
different, even if a gate output without any fanout is
identical to the input of the next gate.
l Coverage reported on different classes of faults
(e.g., exclude untestable faults from the fault list).
l Generate less accurate fault lists (e.g., do not
distinguish between fanout and stem faults).
ECE 1767 University of Toronto
 l Some include potential detects in the regular fault
coverage.

l Some will find a fault definitely detected while

others may find it undetected due to inaccuracy
in logic simulation involving unknown values

l Some start all flip-flops in a known state, since

they do not handle unknowns

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 Detected Faults
Fault Coverage =
Total Faults

Detected Faults
Testable Coverage =
Total Faults - Untestable

Detected + Untestable Faults

ATG Efficiency =
Total Faults
NOTE: ‘Untestable’ definition may be tool dependent!

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 l Serial
l Bit-Parallel
l Deductive
l Concurrent
l Parallel concurrent
l Parallel Pattern
l Inactive Fault Removal:
¨ Star Algorithm
¨ Critical Path Tracing

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 l Advantages
¨ Easiest to implement if you have a logic simulator.
¨ Works with any logic or timing simulator.
¨ Fault insertion/injection is done by modifying the
circuit. X s/0

¨ Any type of fault can be handled.

l Disadvantage
¨ Consumes too much CPU time.
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 l A number of faults can be simulated in parallel by using the
separate bits of a binary word to represent different logic
values.
l Thus, the four faults that a 2-input AND gate can have can
be associated with four bits as shown:

B/1 A/0
B A
C/1 C A/1

0 1 2 3 4
l Effectively, there are five different logic circuits being
simulated,Fault-Free A/0 A/1
but the bitwise B/1 C/1
operation A = B.C is performed in
one step.

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 l If the word size W is smaller than the number of
faults NF, then a parallel fault simulator has to do
multiple passes.
l 31 faults and the fault-free circuit are typically
simulated in parallel using the bitwise parallelism of
the computer word:
g f1 f2 ... f31 32-bit-word
v1
v2 g f1 f2 ... f31
v3 g f1 f2 ... f31
...

¨ Actually need two words to encode 3 values: 0, 1, x

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 l Fault injection done using masks.
¨ If fault needs to be injected on line then override
the line value by fault value.
i/0
X

i
v v’ = v.m + m.c
m 00001000000
c x xxx 0xxx x x x

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 l Simulate faults for inputs ABCDEF = 000001

Fault-Free H/1 J/0

A I G/1 J/1
B
K
C G G
D X X
X H
J
E H J
F
I
K

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 l Based on the concept of fault-list propagation.
l We associate with each node a list of faults that are
detectable at that node.
l When we simulate a gate, we propagate the fault
lists at its inputs to its output.
l The output fault list is deduced from those at
inputs.
l Key attributes:
¨ one pass, carry all faults at the same time
¨ carry only active faults
¨ symbolic representation of faults
ECE 1767 ¨ basic operations used: set Ç, U, and differenceUniversity of Toronto
 LA: {a,c,f} 1
LZ = {a,c,d,f,g}
LB: {d,f,g} 1
LZ = LA U LB

LA: {a,c,f} 0
LZ = {a,c}
LB: {d,f,g} 1
LZ = LA - LB = LA Ç LB
{all faults in A which are not in B}

LA: {a,c,f} 0
LZ = { f }
LB: {d,f,g} 0
LZ = LA Ç LB
ECE 1767 University of Toronto
 LA: {a,c,f} 0
LZ = {a,c,d,f,g}
LB: {d,f,g} 0
LZ = LA U LB

LA: {a,c,f} 1
LZ = {a,c}
LB: {d,f,g} 0 LI LZ = LI
LZ = LA - LB = LA Ç LB
{all faults in A which are not in B}

LA: {a,c,f} 1
LZ = { f }
LB: {d,f,g} 1
LZ = LA Ç LB
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 A
LA LA A
LZ LZ
LB Z LB Z
B B

LZ = {LA Ç LB} U {Z/1} LZ = LA U LB U {Z/1} A=0, B=0

LZ = LA - LB U {Z/1} LZ = LB - LA U {Z/0} A=0, B=1

LZ = LB - LA U {Z/1} LZ = LA - LB U {Z/0} A=1, B=0

LZ = LA U LB U {Z/0} LZ = {LA Ç LB} U {Z/0} A=1, B=1

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 i
a e m
1 h 1
1 b 1
1 k p
1 c f 1
0 d j 1
l 1
1
n
g
Excited faults:
a0 = {a0 } h0 = {e0,b0,f0,h0 }
c0 = {c0 } m0 = {i0,k0,m0 } collapsed fault list with
equivalence classes
j0 = {j0 } n0 = {l0,g0,n0 }
p0 = {p0 }
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 i
m m0
1 a a0 e h0 1
h 1
1 b k p0
c0 1 1
1 c j0 p
f
0 d j 1

1
l 1

n
g n0

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 l Less pessimistic (two lists per node)
{ }0 { }U 1 0 0
LZ = LA U LB
0
A 1
Z
{ }0 { }U B U U 0 U 0
1 LZ = {LA - LB } U {LB - LA }

0 U
LA LA A 1 0 0
LZ = LA U LB
0
U
Z
1 B
L0B LB U 1 1
LZ = LB - LA0 - LUA

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 l More pessimistic (single list per node)
¨ If good value is unknown, then no fault propagates
on that line.
LA0 LUA A 1 U
Z
1 B
L0B LB U forces the list to Æ
¨ If faulty value is unknown, mark fault with * and
follow propagation rules below.
f Ç f* = f* f U f* = f f - f* = f* f* - f = Æ
g Ç f* = Æ g U f* = {g,f*} g - f* = g f* - g = f*
1->0 1->0 1->U use same rules
f A 1->0 f A as for 2-value
Z Z
f* B f f* B f* deductive
1->U 1->U fault simulation
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 l A fault list L containing fault a/0 may
propagate back to line a which now has a
good value of 0. Then fault a/0 must be
removed from the list.

1 a/0
X D Q
1 time t
L 1 0 1/0 0/1
1/0 0/1 1/1 0/1 time t+1

remove fault effect

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 l In theory, deductive fault simulation can be very
efficient.
¨ One pass simulates all faults.
¨ Only active faults that will cause events are
present in the list.
l However, lists can be very large.
¨ Must implement efficient set union, intersection.
¨ Keep lists sorted so that operations are linear.
l Very hard to extend to non-logical fault behavior,
e.g., multi-valued levels, hard to incorporate
timing (essentially 0-delay simulator).

ECE 1767 University of Toronto

 l Like deductive fault simulation, this is also a
one-pass approach, given enough memory,
but several passes are often required in
practice.
l Only those gates in the faulty circuit whose
inputs/outputs are different from the fault-free
circuit are (explicitly) simulated.
¨ Input and output values are stored for these
gates.
¨ The simulation algorithm is similar to event-
driven logic simulation, but events are for the
fault-free and faulty circuits.

ECE 1767 University of Toronto

 0 fault-free gate
1 1

0
0
1 9
fault list
ordered by
fault index 0
0 1 12

1
1
0 45

l Concurrent fault simulation is faster, but more

memory intensive than deductive fault simulation.
l Various timing models can be incorporated, so
asynchronous circuits can be simulated accurately.
ECE 1767 University of Toronto
 l Faults are evaluated in parallel in groups of size
w, where w is the size of the computer word.
l Fault effects are propagated using concurrent
fault simulation algorithm.
l Faster and less memory than concurrent fault
simulation.

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 l For combinational circuits only
l Evaluate 32 patterns (test vectors) in parallel
for each fault
¨ vectors can be applied in any order
s evaluate good circuit

s inject fault and evaluate

l Used in random testing

¨ keep vector that detects fault
l Used in commercial fault simulator available
from Mentor Graphics
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 l Temporarily removing faults known to be inactive
in a given time frame will speed up the fault
simulation.
l Any faults having different states from the fault-
free circuit must be simulated.

ECE 1767 University of Toronto

 l Local Analysis:
zero-level inactive
stuck-at-0 two-level inactive
0 X 0
stuck-at-0
Fault not excited 1X
1
one-level inactive
stuck-at-0 1
1X
0 Fault excited but not
Fault excited but not propagated two levels
propagated one level

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 l Global Analysis: Star Algorithm
[Akers, Krishnamurthy, Park, Swaminathan, ITC,
1990]
¨ Evaluate good circuit
¨ Place Star (*) on subset of nodes which
adequately justify primary output values
¨ Nodes not marked * are inactive, and faults on
these nodes cannot be detected

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 0 * *1 *1 *1
1
* *1 0 *
d 1
1 0 0
0 d 1 *
d *
1 *
0
d 0

d = don’t care

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 l Mark all outputs * (essential to justify the value)
l Back propagate *’s to primary inputs using
the following rules:
* 0
1 1
1 *
0 * * *
choose one arbitrarily *0
1
*0 1 * 0 if at least one
branch has *, mark
1 * *1 * stem with *

l All lines not marked * are not required to

determine the outputs; hence, no faults on
unstarred lines can be detected.
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 1 0
* 1 1 *0 0
* 1 * *0
* * *
d1 1
*
0 0 d* 0 1
du * du *
u 0
* 1 u *u u
* *u
* u * * *
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 1

1
0

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 l Theorem: All single and multiple stuck-at faults marked
with “d” during a single execution of the algorithm are not
detected by the vector and they need not be simulated

l Theorem: All single stuck-at faults marked with “d” in the

union of many executions of the algorithm for different
runs are also not detected

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 [Abramovici, Menon, Miller, IEEE D&T, 1984]

l Identify critical lines in circuit to implicitly determine

detected faults for each test vector.
l Perform logic simulation, identify sensitive inputs of
each gate, then backtrace from the primary outputs,
connecting the dots.
l Exact algorithm for fanout-free circuits, but requires
stem analysis for circuits with reconvergent fanout
l It can act as a “sandwich” with Star Algorithm to speed
fault simulation
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 l Gate input is sensitive if complementing its value it changes the
value of the gate output. A line l has critical value v for test
vector t iff t detects the fault l stuck-at-v’

l Lemma: If the output of a gate is critical then all sensitive inputs

for this gate are also critical

ALGORITHM
Simulate a vector and from every primary output, mark it as critical and
Trace backwards towards primary inputs marking sensitive lines as
Critical according to the lemma

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 0
0 1

1 1
0
Sensitive
lines
0
0 1
1 1
0
0 1
0
1

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l CPT needs extra care for circuits with reconvergent fanouts

1 1
? 1 1 ? 1 1
1 0 1 0
0 0
1 0

Line is not critical for vector 111 Line is critical for vector 110
(s-a-0 not detected) (s-a-0 detected)

l Needs stem analysis, simulate s-a-0 on the line under

consideration until next capture line and mark it if it is critical

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 l Let
¨ T = test set
¨ M = total number of faults in collapsed fault list
¨ K = number of faults detected in collapsed fault list
l Then fault coverage F = K/M.
l Select a random sample of m faults from M faults,
and let k be the number of faults detected in the
sample. Then the sample fault coverage f = k/m.
l How big should the sample be to get F = f ± e for a
given error?

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 l Probability that test T will detect k faults in a
random sample of size m is: K M-K
k m-k
max m=1000 M
error 0.05 m
e
m=2000

M >> m
0 0.5 1
Fault Coverage F

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 l No fault simulation is performed
¨ Only a good circuit simulation is performed.
¨ Based on signal probabilities.
l Let T = test set of n independent random vectors
l df = probability that a random vector from T detects
the fault f
l Probability that none of the n vectors detects f =
(1-df)n
l Then the probability dfn of detecting f by n vectors
= 1 - (1-df)n
not power, just a notation
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 l The the expected number of faults detected (Dn)
from a set F of faults is: Dn = å(1- (1-df)n)
fÎF
l Expected fault coverage = Dn
|F|
l How to compute df?
Pa = probability of signal a being 1
a c s/0 e h
X
b
d f g
df = Pc Pd (1-Pf) Ph assuming independent events
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 l 1-Controllability of line l = C1(l) = probability that a
randomly selected vector from T produces logic 1 on
line l.
l C0(l) = 1 - C1(l) if no unknowns.
l O(l) = observability of line l = probability that a
randomly selected vector from T propagates the fault
effect from l to a primary output (PO).
l During good circuit simulation, keep 0-count, 1-count
C0(l) = 0-count C1(l) = 1-count
n n
(signal probabilities)

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 l We also keep a sensitization count on each gate
input
¨ S(l) = probability that line l is sensitized to next gate
l m
1 line l is sensitized
1
l Observability of l = S(l) O(m) O(PO) = 1
¨ Traverse backwards from PO’s to compute
l1 O(l1) lower bound: O(l) = max O(lk)
l
l2 O(l2) upper bound:
?O(l) l3 O(l3) O(l) = O(l1) + O(l2) - O(l1)(l2)
(assuming independent lines)
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 l Detection probabilities for line/fault l/0, l/1
¨ dl/0 = C1(l) O(l)
¨ dl/1 = C0(l) O(l)
l Group faults in 3 ranges:
¨ high range: df > 0.9 --> considered detected
¨ low range: df < 0.1 --> considered not detected
¨ middle range: 0.1 < df < 0.9 --> undecided
l Experimental results [Jain and Singer, 1986]
¨ 91% to 98% of high range indeed detected
¨ 78% to 98% of low range not detected
¨ middle range contained 10% of faults on average
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