Scribd
Upload
72 views

CMOS Fundamentals - Test 1 - Shastra Micro Systems: (Subjective Type)

This document contains 25 questions about CMOS fundamentals for a test. It covers topics such as latchup, noise margin, sizing transistors, delay, power consumption, charge sharing, body effect, differences between MOSFETs and BJTs, metastability, and optimizing NAND gate delay. The student is asked to answer all questions briefly and provide diagrams where necessary.

Uploaded by

veeru
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
72 views

CMOS Fundamentals - Test 1 - Shastra Micro Systems: (Subjective Type)

This document contains 25 questions about CMOS fundamentals for a test. It covers topics such as latchup, noise margin, sizing transistors, delay, power consumption, charge sharing, body effect, differences between MOSFETs and BJTs, metastability, and optimizing NAND gate delay. The student is asked to answer all questions briefly and provide diagrams where necessary.

Uploaded by

veeru
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

CMOS Fundamentals - Test 1 - Shastra Micro Systems

(Subjective Type)
Answer all questions in brief. Explain with diagram (attach diagrams ) wherever necessary:--

<1> What is Latch up...?

<2> Why is NAND Gate preferred over NOR gate for fabrication..?

<3> What is noise margin.? Explain the procedure to join noise margin.

<4> Explain sizing of the inverter.

<5> How do you size the NMOS & PMOS transistor to increase the threshold voltage..?

<6> What is noise margin. Explain the procedure to determine noise margin.

<7> What happens to delay if you increase the load capacitance..?

<8> What happens to delay if we include the resistance at the output of a CMOS circuit.

<9> What are the limitations in increasing the power supply to reduce delay...?

<10> How does resistance of the metal lines vary with increasing thickness and increasing
length..?

<11> For CMOS logic, give the various techniques you know to minimize the power
consumption.

<12> What is charge sharing.? Explain the charge sharing with an example.

<13> Why do we gradually increase the size of inverters in buffer design.?

<14> What is Latch-up..? Explain latch up with cross section of CMOS inverter. How do you
avoid latch-up.?

<15> What is the expression for CMOS switching power dissipation.

<16> What is body effect..?

<17> Why is the substrate of NMOS connected to ground and in PMOS to VDD..?

WWW.shastramicro.com | email: [email protected] | Cont: 040-66666883


<18> What is the fundamental difference between MOSFET & BJT..?

<19> Which transistor has higher gain..? BJT or MOSFET. Explain why..?

<20> Why do we gradually increase the size of inverters in buffer design when trying to drive a
high load capacitance..? Why dont we give the output of a circuit to one large inverter..?

<21> In CMOS technology, (especially in digital design) why do we design the PMOS to be
higher than the NMOS. What determines the size of PMOS with respect to NMOS.

<22>. Why PMOS & NMOS are sized equally in a transmission Gate..?

<23> What happens when the PMOS & NMOS are interchanged with one another in an
inverter..?

<24>. What is metastabilty.? When/why it will occur.? Explain how we can avoid this.?

<25> Let A and B be two inputs of a NAND gate. Say signal A arrives at the NAND gate later
than signal B. To optimize delay of the two series NMOS inputs A and B which one would you
place near to the output..?

WWW.shastramicro.com | email: [email protected] | Cont: 040-66666883

You might also like