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Vlsi Assignment 1 Solved

1. The document summarizes the results of a lab assignment on analyzing characteristics of an NMOS transistor. Threshold voltage decreases with increasing drain-source voltage due to drain-induced barrier lowering. Threshold voltage also increases with more negative source-body voltage. Channel length modulation causes drain current to increase slightly in saturation. 2. Analysis of a symmetric CMOS inverter where threshold voltage is half the supply voltage is presented. Noise margins and threshold voltage are calculated for different PMOS to NMOS width ratios and load types. Threshold voltage increases with higher PMOS to NMOS width ratio. A CMOS inverter provides better noise margins and full output voltage swing compared to an inverter with a resistive load.

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Nilesh Chauhan
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33 views

Vlsi Assignment 1 Solved

1. The document summarizes the results of a lab assignment on analyzing characteristics of an NMOS transistor. Threshold voltage decreases with increasing drain-source voltage due to drain-induced barrier lowering. Threshold voltage also increases with more negative source-body voltage. Channel length modulation causes drain current to increase slightly in saturation. 2. Analysis of a symmetric CMOS inverter where threshold voltage is half the supply voltage is presented. Noise margins and threshold voltage are calculated for different PMOS to NMOS width ratios and load types. Threshold voltage increases with higher PMOS to NMOS width ratio. A CMOS inverter provides better noise margins and full output voltage swing compared to an inverter with a resistive load.

Uploaded by

Nilesh Chauhan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI LAB ASSIGNMENT 1

NILESH CHAUHAN
2018H1230149G
1) Schematic for determining characteristics of NMOS :

VDS = 50mV
VDS = 1.8 V
a) Plot of ID vs VGS for Vbs = 0V ,Vds = 50mV
VT = 526.679 mV

b) Plot of ID vs VGS for VBS = 0V ,VDS = 1.8 V


VT = 436.694 mV
Observation:
As VDS is increased from 50mV to 1.8mV , VT is decreases from 526mV to 436mV.
In small-geometry MOSFETs, because
the potential barrier is controlled by both the gate-to-source voltage VGS and the
drain-to-source voltage VDS. If the drain voltage is increased, the potential barrier
in the channel decreases, leading to drain-induced barrier lowering (DIBL). The
reduction of the potential barrier eventually allows electron flow between the
source and the drain, even if the gate-to-source voltage is lower than the
threshold voltage or we can say that the threshold voltage decreases .

c) Plot of ID vs VGS for VBS = -0.9V and VBS =0 at Vds = 50mV


Observation:
For VGS of 1.3 V ID decreases from 7mA to 6mA as VSB is increased .
VT is a function of VSB as seen in the relation
VT (VSB) = VTO + (|2 ɸF| + VSB)0.5 - (|2 ɸF|)0.5

Therefore as VSB increases , VT increases due to which current decreases following


the relation given given below for both linear and saturation region .

ID (lin) = Kn/2 [2 (VGS - VT) VDS - VDS2 ]


ID (sat) = Kn/2 (VGS - VT)2 (1 + ʎ VDS )

d) Plot of ID vs VDS for Vgs = 1.8 V and VSB=0


Observation:
Positive slope when the device is in saturation is due to channel length
modulation. Due to this drain current increases slightly after saturation .

e) Simulation setup for measuring channel length modulation :


The drain-to-source voltage is chosen sufficiently large (VDS > VGS - Vt)such that the transistor
operates in the saturation mode(VDS > 1.8-0.436=1.364V). The saturation drain current is
then measured for two different drain voltage values, VDSI and VDS2.The drain current in the
saturation mode is given by
ID (sat) =. (VGS -VTO)2 (I+ λ VDs)
For fixed VGS , the ratio of the measured drain current values ID1, and ID2 is

Id1/Id2 = 1+ʎVds1/1+ʎVds2
which is used to calculate the channel length modulation coefficient λ. This is
equivalent to calculating the slope of the drain current versus drain voltage curve in the
saturation region

12.6516/12.3527 = 1+ʎ(1.6)/1+ʎ(1.4)
Therefore, ʎ = 0.15 V-1
2)
a) Symmetric Inverter :
A CMOS Inverter for which threshold voltage is half of supply
voltage (VDD) i.e. VTH = VDD/2
VTH = 1.8/2 = 0.9 V
 Wp for the CMOS inverter to become symmetric is
6.26 X 4 = 25 um (approx.) using parametric analysis.

 Voltage transfer characteristic


 Calculation of Noise Margin and Vth using derivative graph :
 Noise Margin:
NML=VIL-VOL = 0.746 – 0=0.746 V Op Voltage swing: 1.8 V
NMH=VOH-VIH = 1.8 – 1.05228=0.74772 V VT = 0.9 V

b)
Case 1 : For Wp/Wn = 0.5
Vt = 0.794 V
Case 2 : For Wp/Wn = 1
Vt = 0.837 V

Case 3 : Wp/Wn=2
Vt = 0.97 V
Observation: Vth is proportional to Wp/Wn ratio. So as this ratio increases in
the order 0.5,1,2 from case 1 to case 3 , Vth also increases .

c) Resistive load (1k)


 NMH=VOH-VIH =1.8-0.854= 0.94 V
 NML=VIL-VOL = 0.448-0.1 =0.348 V
 Vt = 0.71 V
 Output Voltage swing: 1.7 V
 Enhancement Load
 WP/WN is set to 1/20

 NML=VIL-VOL = 0.20-0.05 =0.15 V


 NMH=VOH-VIH =1.45-0.688= 0.762 V
 VTH = 0.55 V
 Output Voltage swing: 1.25 V

CMOS inverter :

 Noise Margin:
NML=VIL-VOL = 0.746 – 0=0.746 V
NMH=VOH-VIH = 1.8 – 1.05228=0.74772 V
VT = 0.9 V
Output Voltage swing: 1.8 V

Observation :
From the VTC , we conclude that CMOS inverter has better noise margins,the
transition region is very sharp due to which it resembles an ideal inverter and it
also provides full output voltage swing from 0 to VDD.

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