Unit-1

BASIC MOS Device Physics

Chapter 2: MOS Device Physics

2.1 General Considerations
2.2 MOS I/V Characteristics
2.3 Second-Order Effects
2.4 MOS Device Models
2.5 Appendix A: FinFETs
2.6 Appendix B: Behavior of MOS
Device as a Capacitor
MOSFET as a Switch

• When gate voltage is high, device is on.

• Source and drain are interchangeable.
• But,
- At what gate voltage does the device turn on?
- How much is the resistance between S and D?
- What limits the speed of the device?
MOSFET Structure

• n-type MOS (NMOS) has n-doped source (S) and drain (D) on p-type substrate (“bulk” or “body”).
• S/D junctions “side-diffuse” during fabrication so that effective length Leff = Ldrawn − 2LD .
• Typical values are Leff ≈ 10 nm and tox ≈ 15 A.
• The S terminal provides charge carriers and the D terminal collects them.
• As voltages at the three terminals changes, the source and drain may exchange roles.
MOSFET Structure

• MOSFETs actually have four terminals.

• Substrate potential greatly influences device characteristics.
• Typically S/D junction diodes are reversed-biased and the NMOS substrate is connected to the most negative supply in the system.
In complementary MOS (CMOS) technologies both NMOS (NFET) and PMOS (PFET) are needed and fabricated on the same wafer.
• In today’s CMOS, the PMOS is fabricated in an nwell, where the n-well is tied to the most positive supply voltage.
MOS Symbols

• Substrate is denoted by “B” (bulk).

• PMOS source is positioned on top since it has a higher potential than the gate.
• Most circuits have NMOS and PMOS bulk tied to ground and VDD, respectively, so we tend to omit the connections (b,c).
• Digital circuits tend to incorporate “switch” symbols (c).
Threshold Voltage

As VG increases from zero, holes in p-substrate are repelled leaving negative ions behind to form a depletion region.
• There are no charge carriers, so no current flow. Increasing VG further increases the width of the depletion region and the potential at
the oxide silicon interface.
• Structure resembles voltage divider consisting of gate-oxide capacitor and depletion region capacitor in series.
Increasing VG further increases the width of the depletion region and the potential at the oxide silicon interface.
• Structure resembles voltage divider consisting of gate-oxide capacitor and depletion region capacitor in series.
When interface potential reaches sufficiently positive value, electrons flow from the source to the interface and eventually to the drain.
• This creates a channel of charge carriers (inversion layer) beneath the gate oxide.
• The value of VG at which the inversion layer occurs is the threshold voltage (VTH).

Where
- ΦMS is the difference between the work functions of the poly silicon gate and the silicon substrate.
- k is Boltzmann’s constant. - q is the electron charge. - Nsub is the doping density of the substrate.
- ni is the density of electrons in undoped silicon. - Qdep is the charge in the depletion region.
- Cox is the gate oxide capacitance per unit area. - єsi is the dielectric constant of silicon.
 In practice, threshold voltage is adjusted by implanting dopants into the channel area during device fabrication.
• For NMOS, adding a thin sheet of p+ increases the gate voltage necessary to deplete the region.

 Turn-on phenomena in PMOS are similar to that of NMOS but with all polarities reversed.
• If the gate-source voltage becomes sufficiently negative, an inversion layer consisting of holes is formed at the oxide-silicon interface,
providing a conduction path between source and drain.
• PMOS threshold voltage is negative.
Derivation of I/V Characteristics

• Where
- Qd is the mobile charge density along the direction of current I.
- v is the charge velocity.

Onset of inversion occurs at VGS = VTH.

• Inversion charge density produced by gate oxide capacitance is proportional to VGS − VTH since for VGS ≥ VTH, charge placed on
the gate must be mirrored by charge in the channel, yielding a uniform channel charge density:

• Where WCox is the total capacitance per unit length .

Channel potential varies from zero at the source to VD at the drain.
• Local voltage difference between the gate and the channel varies from VG to VG − VD.
• Charge density now varies with respect to x :

where V(x) is the channel potential at x.

Since

• A negative sign is added because the charge carriers are negative for NMOS.

VGS−VTH is known as the “overdrive voltage.”

• W/L is known as the “aspect ratio.”
• If VDS ≤ VGS−VTH, we say the device is operating in the “triode region.”
If VDS << 2(VGS−VTH), then

• In this case, the drain current is a linear function of VDS so the path from source to drain can be represented by a linear
resistor:

If VDS << 2(VGS−VTH), the device is operating in “deep triode region.”

• In this region, a MOSFET can operate as a resistor whose value is controlled by the overdrive voltage.
• Unlike bipolar transistors, a MOS device may be on even if it carries no current.
For example, given the topology on the left and that

In reality, if VDS > VGS−VTH, ID becomes relatively constant and we say that the device operates in “saturation region.”
• VD,sat = VGS−VTH denotes the minimum VDS necessary for operation in saturation.
 If VDS is slightly larger than VGS−VTH, the inversion layer stops at x ≤ L, and the channel becomes “pinched off.”
• As VDS increases, the point at which QD equals zero gradually moves towards the source.
• At some point along the channel, the local potential difference between the gate and the oxide-silicon interface is not sufficient to
support an inversion layer.
Electron velocity ( ) rises tremendously as they approach the pinch-off point (where ) and shoot through
the depletion region near the drain junction and arrive at the drain terminal.

Since the integral becomes

ID is relatively independent of VDS if L’ remains close to L.

• The device exhibits a “square-law” behavior.
For PMOS devices, the equations become

The negative sign shows up due to the assumption that drain current flows from drain to source, whereas holes in a PMOS flow in the
reverse direction.
• VGS, VDS, VTH, and VGS−VTH are negative for a PMOS transistor that is turned on.
• Since the mobility of holes is ½ about the mobility of electrons, PMOS devices suffer from lower “current drive” capability.

A saturated MOSFET can be used as a current source connected between the drain and the source.
• NMOS current sources inject current into ground while PMOS current sources draws current from VDD.
VDS = VGS−VTH = VD,sat is the line between saturation and triode region.
• For a given VDS, the device eventually leaves saturation as VGS increases.
• The drain is defined as the terminal with a higher (lower) voltage than the source for an NMOS (PMOS).

MOS Transconductance

Transconductance (usually defined in the saturation region) is defined as the change in drain current divided by the change in the gate
source voltage.
• gm represents the sensitivity of the device since a high value implies a small change in VGS will result in a large change in ID.
• Transconductance in saturation region is equal to the inverse of Ron in the deep triode region.

Each expression for transconductance is useful in studying its behavior.

• Drain current and overdrive voltage are bias values.
• If a small signal is applied to a device with defined bias values, we assume the signal amplitude is small enough that the variation in
transconductance is negligible.

To find the transconductance for the topology on the left with respect to VDS, - So long as VDS ≥ Vb − VTH, M1 is in saturation, so ID is
relatively constant, and therefore so is gm.
- When M1 enters triode region (VDS < Vb − VTH),

For PMOS,

Second-Order Effects

Originally, with the bulk of an NMOS tied to ground, the threshold voltage was defined as

Decreasing the bulk voltage (VB) increases the number of holes attracted to the substrate connection, which leaves a larger negative
charge behind and makes the depletion region wider, increasing Q d and thus increasing VTH. • This is known as the “body effect” or
“back-gate effect.”
With body effect, the expression which characterizes the dependence of threshold voltage on the bulk voltage is

• Where,

- denotes the body effect coefficient.

For example, let's find the drain current as bulk voltage varies from negative infinity to 0 given the topology on the left and that
 Body effect manifests itself whenever the source voltage varies with respect to the bulk potential.
• Given the topology on the left and first ignoring body effect, as Vin varies, Vout follows the input because the drain current remains
equal to I1, where

With body effect, as Vin,out become more positive, VSB increases, which increases VTH and thus Vin – Vout must increase to maintain a
constant ID.

Originally, when the device was in saturation region, drain current was characterized by

• The actual length of the channel (L’ = L − ΔL) is a function of VDS, which is an effect called “channel length modulation.”
• 1/L’ ≈ (1 + ΔL/L)/L, and ΔL/L = λVDS, where λ is the channel-length modulation coefficient” gives us

With the effect of channel length modulation, the expressions derived for transconductance of the device that need modification are

Knowing that
and keeping all other parameters constant, we can see that if the length L is doubled, the slope of I D vs. VDS is divided by four.
This is due to

MOSFETs do not turn off abruptly when VGS < VTH, but actually there is a “weak” inversion layer that exists and finite current flows
from drain to source with an exponential dependence on VGS.• This effect is called “sub threshold conduction.”
• When VGS < VTH,

where I0 W/L, ξ > 1 is a no ideality factor, and

VT = kT/q. • Here the device operates in “weak inversion.”

To examine MOSFET behavior as the drain “current density,” ID/W varies, we must consider the equations for both strong and weak
inversion:

For a given current and W/L, we must obtain VGS from both expressions and select the lower value.
• If ID remains constant and W increases, VGS falls and the device goes from strong to weak inversion.
MOSFETs experience undesirable effects if terminal voltage differences exceed certain limits,
e.g.- If VGS is too high, the gate oxide breaks down irreversibly, damaging the transistor.
- In short channel devices, excessively large VDS widens depletion region around the drain so that it touches the depletion region around
the source, creating a very large drain current (an effect called “punchthrough”).

MOS Device Layout

 The gate polysilicon and the source and drain terminals must be tied to metal (aluminum) wires that serve as
interconnects with low resistance and capacitance.
 This is accomplished with contact windows”which are filled with metal and connected to the upper metal wires.
 To minimize the capacitance of the source and drain, the total area of each junction must be minimized.
  Since M1 and M2 share the same S/D junctions at node C and M2 and M3 do the same at node N, we can lay them out as
shown above.
 Since the gate polysilicon of M3 cannot be directly tied to the source material of M1, a metal interconnect is necessary.
MOS Device Capacitances

 To better predict high-frequency behavior, it is necessary to consider device capacitances.

 Capacitance exists between every two of the four terminals, and their values depend on the bias conditions of the transistor .

Capacitances include
- The oxide capacitance between the gate and the channel C1.
- The depletion capacitance between the channel and the substrate C2.
- The capacitance due to the overlap of the gate poly with the source and drain areas C3 and C4.
- The junction capacitance between the source/drain areas and the substrate C5 and C6.

Due to fringing electric fields, C3 and C4 cannot be written as WLDCox; rather we must find the overlap capacitance per unit width
(Cov) and multiply that value with W.C5 and C6 are decomposed into two components:
- The bottom-plate capacitance associated with the bottom of the junction, Cj:

where VR is the reverse voltage across the junction, ΦB is the junction built-in potential and m is a power typically in the range of 0.3
and 0.4. - The sidewall capacitance due to the perimeter of the junction, Cjsw.
For example calculating the source and drain junction capacitance of the topology on the left,

Calculating the source and drain junction capacitance of the second topology on the left,

We assumed the total source/drain perimeter 2(W+E) is multiplied by Cjsw.

Considering capacitance values in different

operating regions, if the device is off,

- where L is the effective length, and єsi = єr,si x є0 = 11.8 x (8.85 x 10-14) F/cm.
- The values of CSB and CDB are a function of the source and drain voltages with respect to the substrate.
In deep triode region, the source/drain have approximately equal voltages, so the gate channel capacitance WLCox is divided equally
between the gate-source terminals and the gate drain terminals, which results in

CGB is usually neglected in triode and saturation regions because the inversion layer acts as a “shield” between the gate and the bulk, so
if VG varies, the charge is supplied by the source/drain rather than the bulk.
If the device is in saturation region, CGD will be
roughly equal to WCov.
• The varying potential difference between gate and channel cause nonuniform vertical electric field in the gate oxide while going from
source to drain, which results in CGS being

MOS Small-Signal Model

If perturbation in bias conditions are small, a “small-signal” model can be used to simplify calculations (derived for
saturation region).
• In order to derive the small-signal model, we - Apply certain bias voltages to the terminals of the device.
- Increment the potential difference between two of the terminals while the other terminal voltages remain constant.
- Measure the resulting change in all terminal currents.
By changing the voltage between two terminals by ΔV = VGS and then measuring a current change ΔI = gmVGS, we can model the
effect by a voltage dependent current source.
• Above is the small-signal model of an ideal MOSFET.

Due to channel-length modulation, drain current also varies with VDS , but a current source whose value linearly depends on the
voltage across it is equivalent to a linear resistor:

It is assumed that λVDS << 1.

• ro limits the maximum voltage gain of most amplifiers.

Due to body effect, bulk potential influences VTH and hence gate-source overdrive.
• With all other terminals held at a constant voltage, the bulk behaves as a second gate since the drain current is a function of the bulk
voltage given by gmbVBS, where
The small-signal model above is adequate for most low-frequency small-signal analyses.
• In reality, each terminal exhibits a finite ohmic resistance due to resistivity of the material (and contacts), but proper layout can
minimize these resistances.
- Folding reduces the gate resistance by a factor of four.

The complete MOS small-signal model not only includes channel-length modulation and body effect, but also the capacitances between
each terminal.

To sketch gm and gmb of M1 on the left as a function of bias current I1,

gmb dependence on I1 is less straight forward, but as I1 increases, VX decreases and so does VSB.
The derivation of the small-signal model for PMOS yields the exact same model as for NMOS.
• The model shows the voltage-dependent current source pointing upward, giving the (wrong) impression that the direction of the
current in the PMOS is opposite of that in NMOS.