FPGA
FPGA
The Emergence of
FPGA-Based Prototyping
for SoC Design
Includes All-New
DANIEL NENNI
& DON DINGEE
Field Guide A SEMIWIKI PROJECT
PROTOTYPICAL
The Emergence of
FPGA-based Prototyping
for SoC Design
Foreword by Mon-Ren Chene, CTO of S2C Inc.
Daniel Nenni
Don Dingee
@2016 by Daniel Nenni and Don Dingee
All rights reserved. No part of this work covered by the copyright herein
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as permitted under Section 107 or 108 of the 1976 US Copyright Act, without
the prior written permission of the publisher.
Although the authors and publisher have made every effort to ensure the
accuracy and completeness of information contained in this book, we
assume no responsibility for errors, inaccuracies, omissions, or any
inconsistency herein.
Contents
Foreword ......................................................................................................... v
The Future of FPGA Prototyping .............................................................. v
Design for FPGA Prototyping .................................................................... v
Moving to the Cloud ................................................................................. ix
Introduction: The Art of the “Start” ................................................................ 1
A Few Thousand Transistors ..................................................................... 2
Microprocessors, ASICs, and FPGAs ......................................................... 5
Pre-Silicon Becomes a Thing ..................................................................... 7
Enabling Exploration and Integration .................................................... 10
Chapter 1: SoC Prototyping Becomes Imperative ......................................... 15
Programmable Logic in Labs .................................................................... 15
First Productization of Prototyping ........................................................ 18
Fabless and Design Enablement ............................................................ 20
Chapter 2: How S2C Stacked Up Success .................................................... 25
Making ESL Mean Something ................................................................. 25
TAI IP and “Prototype Ready” ................................................................. 26
Taking on the Cloud ................................................................................ 30
Chapter 3: Big EDA Moves In ....................................................................... 35
A Laurel and HARDI Handshake ............................................................ 35
Verification is Very Valuable ................................................................... 37
An Either-Or Response............................................................................ 39
A Bright Future Ahead............................................................................. 41
Chapter 4: Strategies for Today and Tomorrow .......................................... 45
The State of FPGA-Based Prototyping .................................................... 45
Developing for ARM Architecture ..........................................................48
Adoption Among Major System Houses .................................................. 51
Application Segments in Need ................................................................ 52
iii
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
iv
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Foreword
The Future of FPGA Prototyping
Nearly two decades ago during our time at Aptix, my S2C co-founder,
Toshio Nakama and I recognized the power of prototyping. At that time,
prototyping was only accessible by large design houses with the budget
and means to employ a prototyping architecture. We also recognized
that FPGAs had become a popular alternative to the much more
expensive and rigid ASICs. It was then that we both decided to team up
to develop a prototyping board around an FPGA, and S2C was born. Our
commitment to our customers has been to push the limits of what FPGA
prototyping can do to make designing easy, faster, and more efficient.
Our goal has always been to close the gap between design and
verification which meant that we needed to provide a complete
prototyping platform to include not only the prototyping hardware but
also the sophisticated software technology to deal with all aspects of
FPGA prototyping.
Fast forward to today and you’ll find that FPGAs and FPGA prototyping
technology has advanced so much that designers and verification
engineers can no longer ignore the value that they bring, especially
when dealing with the very large and complex designs that we see today.
These advances have made FPGA prototyping poised to become a
dominant part of the design and verification flow. This book will
hopefully give you a sense of how this is achieved.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
2) Block-based Prototyping
And very often, designers don’t even have the RTL source code
for the IP blocks from 3rd parties (for example, ARM processors)
and therefore cannot map the IP to the FPGAs themselves. This
can be solved by requesting the IP provider to supply the
encrypted netlist so that you can synthesize and partition the
vi
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
4) Memory Modeling
viii
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Mon-Ren Chene
CTO of S2C, Inc.
May 2016
ix
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
x
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
With the stakes so high for large, sophisticated chips, no prudent leader
would dare avoid investments in semiconductor process quality.
Foundries such as GlobalFoundries, Intel, Powerchip, Samsung, SMIC,
TSMC, UMC, and others have designed entire businesses around
producing quality in volume at competitive costs for their customers.
1
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Yet, chip design teams often struggle with justifying verification costs,
settling for doing only part of the job. A prevailing assumption is the
composite best efforts of skilled designers using powerful EDA tools
should result in a good design. Reusing blocks from known-good
sources, a long-standing engineering best practice in reducing risk and
speeding up the design cycle, helps.
Any team that has experienced a chip design “stop” knows better. Many
stories exist of a small error creeping through and putting a chip
design, and sometimes a reputation, at risk. The price of non-
verification of both hardware and software of a design can dwarf all
other investments, and instantly thwart any prior success a firm may
have enjoyed.
2
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
3
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Image I-1: Texas Instruments SN74S181N 4-bit ALU with 63 logic gates
Using LSI chips changed as well. The good news was more functions
were integrated. The bad news was board-level test visibility declined,
with designers having to trust the data sheet because the inner
workings of a chip were mostly impenetrable. Chip errata become
commonplace; instead of fixing the chip layout immediately, vendors
spent energy on diagnosing issues and determining workarounds,
waiting to gather enough fixes to justify a chip respin.
4
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Intel moved to the lead in LSI with offerings in DRAM, EPROM, and a
new type of chip in November 1971: the microprocessor. Its first part
sprang from a custom product for a Japanese calculator vendor. The
4004 4-bit microprocessor debuted under the MCS-4 banner,
including RAM and ROM and a shift register tuned for the 4-bit
multiplexed bus. With 2300 transistors fabbed in 10 micron and
running up to 740 MHz, the 4004 had 16 internal registers and offered
46 instructions. 6
5
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
The first usage of ASICs was as glue logic for improved integration, or
as companion chipsets to microprocessors, often customized to a
specific board design. A growing roster of ASIC vendors eventually
including AT&T, Fujitsu, IBM, LSI Logic, Plessey, Toshiba, TI, and VLSI
Technology were working to abstract the design flow with tools, IP
libraries, and fab qualification. For the first time, design teams at a
customer could create parts using “standard cells” and get them
produced at moderate risk and reasonable lead times of a few months.
Another breakthrough was near. Altera took an idea from the research
halls of GE, combining the elements of EPROM memory with CMOS
floating logic gates, and added synthesis software in 1984. A logic
design for the Altera EP300 could be created on a PC in a week or so
using schematic capture, state machine, or logic table entries. Parts
could be “burned”, and easily erased with an ultraviolet light and
reprogrammed as needed, in a matter of hours. Customers with
6
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
EDA tools from pioneers Daisy, Mentor, and Valid were being adapted
from circuit board design to ASIC tasks. Rather than capturing a design
7
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
and tossing it into silicon and hoping for good results, more emphasis
was being placed on logic simulation. EDA workstations were relatively
fast, but simulation of a VLSI design was still a tedious and slow
process, requiring skill to create a testbench providing the right stimuli.
Still, ASIC simulation was cheaper than a failed piece of silicon and
more dollars and several more months waiting for a fix. 9
Just as ASIC vendors discovered, Intel found simulation too slow and
falling further behind. RTL simulations were chewing up more than
80% of Intel’s EDA computing resources, and verification was growing
non-linearly with processor size. A solution would come from an
unexpected source: the FPGA community.
8
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
9
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Hardware emulators are automatic, meant for big projects and broader
application on more than one design. A user need not know details of
the logic implementation, or how interconnects are organized. An
arbitrary netlist for an ASIC is loaded, chopped into many smaller
pieces, and spread out across many partitions – in the beginning,
implemented with tens or hundreds of FPGAs.
Prototypes are more specific, often configured and tuned for one
project. Assuming adequate logic capacity and interconnect pins, a
design can be synthesized for a single FPGA target, or perhaps
partitioned across a handful of FPGAs with optimized interconnect.
Rent’s Rule becomes less applicable for a design of manageable size.
This is the basic premise of FPGA-based prototyping, which becomes
more and more attractive as FPGA logic capacities improve. 14
10
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
What really makes the case for FPGA-based prototyping is not a change
in FPGAs, however, but changes in system design practices and
objectives. The type of design starts typical in the industry evolved
dramatically, looking less often like an enormous Intel microprocessor.
System-on-chips, microcontrollers, application-specific standard
product (ASSPs), and other designs take advantage of a growing field of
IP for customized implementations.
11
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
12
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
NOTES
1
“1947 – Invention of the Point-Contact Transistor”, Computer History
Museum,
http://www.computerhistory.org/semiconductor/timeline/1947-
invention.html
2
“1958 – All semiconductor ‘Solid Circuit’ is demonstrated”, Computer
History Museum,
http://www.computerhistory.org/semiconductor/timeline/1958-
Miniaturized.html
3
“1960 – First Planar Integrated Circuit is Fabricated”, Computer
History Museum,
http://www.computerhistory.org/semiconductor/timeline/1960-
FirstIC.html
4
“1963 – Standard Logic IC Families Introduced”, Computer History
Museum,
http://www.computerhistory.org/semiconductor/timeline/1963-
TTL.html
5
“Viterbi Decoding for Satellite and Space Communication”, Jerry
Heller and Irwin Jacobs, Linkabit Corporation, IEEE Transactions on
Communication Technology, October 1971, pp. 835-848,
http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1090711
6
“The Story of the Intel 4004”, Intel,
http://www.intel.com/content/www/us/en/history/museum-story-of-
intel-4004.html
7
“In the Beginning”, Ron Wilson, Altera,
https://www.altera.com/solutions/technology/system-
design/articles/_2013/in-the-beginning.html
8
“’XILINX DEVELOPS NEW CLASS OF ASIC.’ Blast from the Past: A
press release from 30 Years ago, yesterday”, Steve Leibson, Xilinx,
November 3, 2015, https://forums.xilinx.com/t5/Xcell-Daily-
Blog/XILINX-DEVELOPS-NEW-CLASS-OF-ASIC-Blast-from-the-Past-
A-press/ba-p/663224
9
“A Brief History of ASIC, part I”, Paul McLellan, SemiWiki, August 21,
2012, https://www.semiwiki.com/forum/content/1587-brief-history-
asic-part-i.html
10
“Coping with the Complexity of Microprocessor Design at Intel – A
CAD History”, Gelsinger et al, Intel, IEEE Solid-State Circuits Magazine,
June 2010,
13
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
http://webee.technion.ac.il/people/kolodny/ftp/IntelCADPaperFinal2.
pdf
11
“A Reprogrammable Gate Array and Applications”, Stephen
Trimberger, Xilinx, Proceedings of the IEEE, Vol. 81 No. 7, July 1993,
http://arantxa.ii.uam.es/~die/[Lectura%20FPGA%20Architecture]%20
A%20reprogrammable%20gate%20array%20-Trimberger.pdf
12
“Inside Intel”, Robert Hof, BusinessWeek, June 1, 1992,
http://www.businessweek.com/1989-94/pre88/b326855.htm
13
“Pre-Silicon Validation of Pentium CPU”, Koe et al, Intel, Hot Chips 5,
August 10, 1993, http://www.hotchips.org/archives/1990s/hc05/
14
“Logic Emulation and Prototyping: It’s the Interconnect (Rent
Rules)”, Mike Butts, NVIDIA, RAMP at Stanford, August 2010,
http://ramp.eecs.berkeley.edu/Publications/RAMP2010_MButts20Aug
%20(Slides,%208-25-2010).pptx
14
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
processing FPGAs (with a 17th part controlling the crossbar), and added
an SBus adapter for easy connection to a Sun Microsystems
SPARCstation. 15
16
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
The first of these rapid prototyping boards appearing in 1990 was the
AnyBoard from North Carolina State University. It returned to a simple
linear array of five Xilinx XC3090s and soon added automated circuit
partitioning built on Xilinx place & route software. The partitioning
software understood interconnect pins, clock rates, and logic and I/O
constraints. Researchers compared gradient descent algorithms with a
multi-bin version of Kernighan and Lin graph partitioning, testing
designs of varying complexity. 17
From the University of California, Santa Cruz came the aptly named
BORG in 1992. Two Xilinx FPGAs contained logic, two more held
reconfigurable routing, and a fifth performed configuration and
interfacing to a PC host. Much of the research focused on the problem
of pin assignment using bipartite graphs and new algorithms for a two-
commodity flow solution. (In a bit of irony, the first BORG prototype
itself was wire wrapped.) BORG illustrated the complexity of
programmable interconnect between parts even with relatively small
FPGA packages. 19
17
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
The growing popularity of the Aptix FPIC influenced the design of the
Transmogrifier-1 at the University of Toronto in 1994. It indirectly
scaled up the BORG concept, with four more powerful Xilinx XC4010
FPGAs interconnected by two FPICs, and a fifth FPGA providing the
interface to a SPARCstation. Researchers used the platform to speed
designs of three example projects: a Viterbi decoder, a memory
organizer that emulated various configurations, and a logarithmic
number system processor. Using SRAM blocks in the FPGAs allowed
algorithm optimization compared to full-custom chip designs (multi-
chip modules using FPGA dies), resulting in higher clock speeds and
other implementation insights that were fed back to future modules. 21
Aptix CEO Amr Mohsen reflected on the early business challenges with
the FPIC parts, saying they were “probably two to three years ahead”
and being asked by customers to move into complete, turnkey
hardware emulation. At the Design Automation Conference in June
1994, Aptix launched two products. Explorer ASIC targeted single-chip
emulation at 10 MHz using 21 Xilinx XC4000-class FPGAs and FPICs
for interconnect, with automatic partitioning software provided by
third party Software & Technologies. System Explorer MP3 provided
general-purpose 50 MHz system-level emulation with configurable
FPGA payloads and I/O, but lacking automatic partitioning tools.
Automation would be added later with the System Explorer MP4 family
in May 1996. 22, 23
IKOS Systems bought its way into the hardware emulation market by
acquiring Virtual Machine Works in May 1996. The VirtuaLogic SLI
hardware emulator was productized and released by late 1996 with a
basic 200K gate capacity upgradable to over 1M gates. VirtualWires
technology created at MIT provided synthesis for FPGAs, avoiding a
need to move toward ASICs as other vendors were doing. 24
Major EDA players then moved in and competition got a bit ugly.
19
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
ASIC complexity in both gate and pin counts had overwhelmed most
FPGA implementations, even attempts with programmable
interconnect. HARDI Electronics AB, a small Swedish firm,
reinvestigated the problem and decided to route FPGA I/O to high
speed connectors leading off board. By insuring impedance and trace
length matching, external cabling could be used to complete
connections in the desired configuration. The result was the first
HARDI ASIC Prototyping System (HAPS) created in 2000, based on
the Xilinx Virtex FPGA. To get larger configurations, HARDI began
work on a board stacking scheme and bus interconnect – HapsTrak.
20
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Then, ARM cores became fully synthesizable. The impetus was an effort
at ASIC vendor LSI Logic who launched a CoreWare synthesizable
version of ARM7TDMI in late 1997. ARM soon responded with
standard synthesizable versions of its ARM7TDMI-S core and
ARM946E-S and ARM966E-S macrocells, opening choices for using
industry-standard EDA tools. By 2000, both TSMC and UMC had
joined the new ARM Foundry Program and taken “per use” licenses.
22
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
NOTES
15
“Reconfigurable Computing”, Jeffrey M. Arnold, IDA Supercomputing
Research Center, published in New Horizons of Computational
Science: Proceedings of the International Symposium on
Supercomputing, Tokyo, Japan, September 1997, edited by Toshikazu
Ebisuzaki and Junichiro Makino, pp. 95-106.
16
“The Roles of FPGAs in Reprogrammable Systems”, Scott Hauck,
Northwestern University, published in Proceedings of the IEEE,
Volume 86 Issue 4, April 1998, pp. 615-638.
17
“Automatic circuit partitioning in the AnyBoard rapid prototyping
system”, Douglas A. Thomae and David E. Van den Bout, North
Carolina State University, Microprocessors and Microsystems, Volume
16 Issue 6, 1992, pp. 283-290.
18
“Chips on the Net: An FPGA prototyping platform”, M. J. Smith and
H. Fallside, University of Hawaii and Xilinx, published in Proceedings
of the 3rd European Workshop on Microelectronics Education, May
2000, pp. 151-154.
19
“BORG: A Reconfigurable Prototyping Board Using Field-
Programmable Gate Arrays”, Pak K. Chan, Martine D. F. Schlag, and
Marcelo Martin, University of California, Santa Cruz, published in
Proceedings of the 1st International ACM/SIGDA Workshop on Field-
Programmable Gate Arrays, 1992, pp. 47-51.
20
“FPGA Based Low Cost Generic Reusable Module for the Rapid
Prototyping of Subsystems”, Apostolos Dollas, Brent Ward, John D. S.
Babcock, Duke University, published in Lecture Notes in Computer
Science, Volume 849, 1994, pp. 259-270.
21
“The Transmogrifier: The University of Toronto Field-Programmable
System”, Galloway et al, University of Toronto, June 1994,
http://www.eecg.toronto.edu/~jayar/research/Transmogrifier1.pdf
22
“Aptix aims to be ‘system-emulation’ pioneer”, Richard Goering,
Techweb, CMP Publications, June 27, 1994, p. 33,
http://www.xsim.com/bib/papers.d/aptix.html
23
“Aptix expands System Explorer family of emulation tools”, Aptix
press release, May 20, 1996,
http://www.thefreelibrary.com/APTIX+EXPANDS+SYSTEM+EXPLORE
R+FAMILY+OF+SYSTEM+EMULATION+TOOLS-a018303369
24
“Logic Emulation for the Masses Arrives; IKOS prepares to roll out
production versions of its innovative VirtuaLogic SLI emulation
23
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
24
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
25
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
S2C was essentially in stealth mode for nearly two years. One of the key
problems in making the leap from reconfigurable computing to FPGA-
based prototyping was the tools used with FPGAs and the IP that went
inside.
The buzzword making the rounds in EDA circles at the time was ESL:
electronic system-level design. The idea of ESL sounded great on paper,
bringing together approaches using high-level hardware descriptions
with hardware and software co-design strategies and adding virtual
prototyping and co-verification. (It was a lot of buzzwords inside
buzzwords.) EDA vendors were scrambling to unify their tool suites
and create a cohesive flow that shared design data and results.
FPGA tools were different, even foreign to most ASIC designers. For
many, although the benefits of prototyping were increasing, the extra
steps in becoming familiar with FPGA synthesis and debug were
troubling. Worse yet, FPGA IP blocks were usually tuned for FPGA
constructs. Steps to obtain logic and timing closure in FPGAs were
different from those in ASICs. Concerns over the fidelity of an FPGA-
based prototype were valid; if too much effort was required to resolve
differences when moving a design back into an ASIC flow, the time-to-
success gains from prototyping and exploration would be undone.
26
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Beta customers working with the product estimated their design time
was cut by 3 to 6 months. Productivity gains came not so much from
the initial setup of a prototype, but from a significant reduction in
iteration time as debug and analysis uncovered changes and
improvements. TAI IP enabled reconfiguring only the part of the design
where changes were made, speeding up the synthesis.
27
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
28
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
2013 saw the addition of more logic modules based on the Xilinx Zynq-
7000 All Programmable SoC with its integrated dual ARM Cortex-A9
cores. With up to four Zynq-7000 parts on one board, plus a high-
frequency LVDS pin multiplexing scheme, a single board could handle
up to 80M gates. New Prototype Ready modules added HDMI, GTX
transceiver interfacing, and other support around the Zynq-7000.
29
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
In April 2015, S2C announced a new brand: Prodigy. In many ways, the
story remains the same under a new name. Prodigy unifies the offering
of FPGA logic modules, Player Pro partitioning and configuration
software, ProtoBridge system-level simulation link tool, and the library
of Prototype Ready modules now numbering over 80 designs. In other
ways, Prodigy marks a new beginning. 40
30
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
For DAC 2015 in June, ten years after introducing its first product to
the public, S2C unveiled a new concept in scalability. Prodigy Cloud
Cube introduces a capacity breakthrough providing up to 1.4B gates in
a single chassis with up to 32 FPGAs. Simultaneous access for up to 16
engineers is supported, with remote access via Ethernet. Configuration
of the platform itself is automatic, with detection of installed logic
modules, cabling, and daughter cards, along with self-tests to isolate
issues. 41
31
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
32
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
NOTES
29
“Scalable reconfigurable prototyping system and method”, US Patent
7353162, April 1, 2008, http://www.google.com/patents/US7353162
30
“S2C delivers breakthrough FPGA-based ESL Design with TAI IP”,
Design & Reuse, May 31, 2005, http://www.design-
reuse.com/news/10519/s2c-breakthrough-fpga-esl-design-tai-ip.html
31
“A New Era for SoC Prototyping Flow: From System Architecture Plan
to Verification”, S2C presentation by Mon-Ren Chene, January 15,
2009,
http://www.digitimes.com.tw/tw/B2B/Seminar/Service/download/0519
801150/DTF_980115_Track1_04.pdf
32
“S2C Announces 4th Generation Rapid SoC Prototyping Solution”,
S2C press release, June 14, 2010,
http://www.s2cinc.com/company/press-releases/2010/s2c-announces-
4th-generation-rapid-soc-prototyping-solution
33
“S2C Announces Virtex-6 Based 4th Generation Rapid SoC
Prototyping Solution”, S2C press release, August 30, 2010,
http://www.s2cinc.com/company/press-releases/2010/s2c-announces-
virtex-6-based-4th-generation-rapid-soc-prototyping-solution
34
“S2C Releases 32.8 Million Gate SoC/ASIC Prototyping System”, S2C
press release, April 21, 2011, http://www.s2cinc.com/company/press-
releases/2011/s2c-releases-32.8-million-gate-socasic-prototyping-
system
35
“S2C Announces a Breakthrough Verification Module”, S2C press
release, June 6, 2011, http://www.s2cinc.com/company/press-
releases/2011/s2c-announces-a-breakthrough-verification-module
36
“S2C Releases Dual Virtex-7 2000T FPGA Rapid SoC Prototyping
Hardware”, S2C press release, May 31, 2012,
http://www.s2cinc.com/company/press-releases/2012/s2c-releases-
dual-virtex-7-2000t-fpga-rapid-soc-prototyping-hardware
37
“S2C Releases New Prototype Ready ARM11 and ARM9 Modules for
FPGA-Based Prototypes”, S2C press release, June 1, 2012,
http://www.s2cinc.com/company/press-releases/2012/s2c-releases-
new-prototype-ready%E2%84%A2-arm11-and-arm9-modules-for-fpga-
based-prototypes
38
“New Quad Virtex-7 2000T 3D IC Rapid ASIC Prototyping Platform
from S2C Optimized for Design Partitioning”, S2C press release,
January 21, 2013, http://www.s2cinc.com/company/press-
33
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
releases/2013/new-quad-virtex-7-2000t-3d-ic-rapid-asic-prototyping-
platform-from-s2c-optimized-for-design-partitioning
39
“S2C ProtoBridge AXI Expands FPGA-Based Prototype Usage”, S2C
press release, June 30, 2014, http://www.s2cinc.com/company/press-
releases/2014/s2c-protobridge%E2%84%A2-axi-expands-fpga-based-
prototype-usage
40
“S2C Sets New Standards for FPGA-Based Prototyping with Prodigy
Complete Prototyping Platform”, S2C press release, April 21, 2015,
http://www.s2cinc.com/company/press-releases/2015/s2c-sets-new-
standards-for-fpga-based-prototyping-with-prodigy-complete-
prototyping-platform
41
“S2C Prodigy Cloud Cube Enables FPGA Prototyping of 1 Billion Gate
Designs”, S2C press release, May 26, 2015,
http://www.s2cinc.com/company/press-releases/2015/s2c-
prodigy%E2%84%A2-cloud-cube%E2%84%A2-enables-fpga-
prototyping-of-1-billion-gates-designs
42
“S2C Expands Kintex UltraScale Prototyping Solutions for Consumer-
based IoT and Other Small to Medium Sized Designs”, S2C press
release, January 11, 2016, http://www.s2cinc.com/company/press-
releases/20161/s2c-expands-kintex-ultrascale-prototyping-solutions-
for-consumer-based-iot-and-other-small-to-medium-sized-designs
34
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
As VHDL usage grew, so did the size of ASIC designs performed using
it. Simulation, though effective, was falling behind in terms of
providing enough speed to run the necessary verification tests on a
larger ASIC. Moving the verification tasks into hardware became the
path forward.
35
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
In 2000, HARDI took the next logical step, creating the HARDI ASIC
Prototyping System. For several years, the system then just known as
HAPS was used in consulting activity for ASIC customer engagements.
HARDI coordinated closely with both Xilinx and a relatively new firm
formed in 1994, Synplicity, for FPGA synthesis and debug technology
including Synplicity’s Certify and Identify.
Demand for the HAPS platform rose over the next several years to the
point where HARDI began more aggressive external marketing,
launching version 2.1 of HAPS (soon to be rebranded as HAPS-10) at
the Design Automation and Test in Europe show in March 2003. HAPS
2.1 held up to four Xilinx Virtex-II 8000 FPGAs providing a total of up
to 8M gate capacity running at up to 200 MHz. 45
36
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Almost two months to the day later came a much more surprising
announcement. The HAPS-50 news included a quote on the growing
partnership between HARDI and Synplicity, including the addition of
the new Total Recall debugging technology. The partnership cemented
on June 1, 2007 with the news that Synplicity was acquiring HARDI for
$24.2M in cash. 52
37
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
In turn, the new and improved Synplicity was suddenly on radar of one
of the big three EDA firms: Synopsys. In a slightly more complicated
transaction since Synplicity was publicly traded, Synopsys paid around
$227M to acquire Synplicity on March 20, 2008. HAPS was now a
Synopsys brand. 53
Capacity had long been an objective of HAPS, keeping pace with each
successive Xilinx FPGA release. The efforts with DesignWare IP and
customers showed how valuable smaller FPGA-prototyping platforms
could be, easy to set up for a software developer to work on code or for
an IP block developer to work on a single piece of IP prior to
integration. Streamlining the larger HAPS-70 platform resulted in the
HAPS Developer eXpress, or HAPS-DX, in December 2013. HAPS-DX
added an FMC interface for industry-standard daughterboards to add
I/O, and ProtoCompiler (formally released in April 2014, replacing the
short-lived Confirma tools) extending the flow and hardware awareness
in software tools. 56, 57
An Either-Or Response
In March 2011 after working in conjunction with Xilinx, Synopsys
released the FPGA-Based Prototyping Methodology Manual. Mentor
Graphics was (and is) still focused on hardware emulation technology.
The third member of the big three, Cadence, was also in hardware
emulation but needed some kind of response to the growing FPGA-
based prototyping movement.
39
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
40
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Synopsys has stayed its course as one of the leaders in the field. Moving
into the Xilinx UltraScale generation, HAPS-80 launched in September
2015. Synopsys says this gets them to 1.6B ASIC gates with stacked
HAPS-80 modules, supported with an improved ProtoCompiler
handling the high-speed time-division multiplexing awareness. HAPS-
80 runs at 300 MHz for a single FPGA, 100 MHz with non-pin-
multiplexed multi-FPGAs, and 30 MHz with pin multiplexing.
41
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Combined with the efforts of S2C and others including Aldec, The Dini
Group, HyperSilicon, Pro Design Electronic GmbH, ReFLEX, and even
small prototyping systems from ARM, these developments have moved
the art of FPGA-based prototyping systems forward. Next, we’ll take a
look at where the technology is headed and how designers in segments
enjoying a renaissance of design starts can benefit from the ideas.
42
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
NOTES
43
“1076-2008 – IEEE Standard VHDL Language Reference Manual”,
IEEE Standards Association,
https://standards.ieee.org/findstds/standard/1076-2008.html
44
“VHDL Handbook”, HARDI Electronics AB, 1997,
http://www.csee.umbc.edu/portal/help/VHDL/VHDL-Handbook.pdf
45
“HARDI Electronics Releases a Real-Time ASIC Prototyping Platform
at DATE”, HARDI Electronics AB press release, March 3, 2003,
http://www.businesswire.com/news/home/20030303005294/en/HAR
DI-Electronics-Releases-Real-Time-ASIC-Prototyping-Platform
46
“HARDI Electronics Releases a New Single-FPGA Module in the
HAPS Prototyping Family”, HARDI Electronics AB press release,
December 2, 2003,
http://www.businesswire.com/news/home/20031202005773/en/HAR
DI-Electronics-Releases-Single-FPGA-Module-HAPS-Prototyping
47
“HARDI Electronics Unveils Second Generation ASIC Prototyping
Platform”, HARDI Electronics AB press release, December 13, 2004,
http://www.businesswire.com/news/home/20041213005828/en/HARD
I-Electronics-Unveils-Generation-ASIC-Prototyping-Platform
48
“HARDI Electronics Unveils Industry's Most Advanced ASIC
Prototyping Platform at the ARM Developers Conference”, HARDI
Electronics AB press release, October 4, 2005,
http://www.businesswire.com/news/home/20051004005734/en/HAR
DI-Electronics-Unveils-Industrys-Advanced-ASIC-Prototyping
49
“How to Make an ASIC Prototype”, Lars-Eric Lundgren, HARDI
Electronics AB, Electronic Engineering Journal October 18, 2005,
http://www.eejournal.com/archives/articles/20051018_hardi/
50
“HARDI Electronics Announces Two New Motherboards in The
HAPS ASIC Prototyping Family at DATE 2006 (Booth A1)”, HARDI
Electronics AB press release, March 6, 2006,
http://www.businesswire.com/news/home/20060306005867/en/HAR
DI-Electronics-Announces-Motherboards-HAPS-ASIC-Prototyping
51
“HARDI announces FPGA-based HAPS-50 prototyping system”, Max
Maxfield, EETimes, April 4, 2007,
http://www.eetimes.com/document.asp?doc_id=1304157
52
“Synplicity Announces Agreement to Acquire HARDI Electronics
AB”, Synplicity press release, June 1, 2007,
43
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
http://www.sec.gov/Archives/edgar/data/1027362/000119312507129831
/dex991.htm
53
“Synopsys to Acquire Synplicity, Inc.”, Synopsys press release, March
20, 2008, http://news.synopsys.com/index.php?item=122910
54
“Synopsys Introduces the HAPS-60 Series of Rapid Prototyping
Systems”, Synopsys press release, April 19, 2010,
http://news.synopsys.com/index.php?s=20295&item=123150
55
“New FPGA-Based Prototyping Solution Delivers Up to 3x System
Performance Improvement”, Synopsys press release, November 12,
2012, http://news.synopsys.com/index.php?s=20295&item=123433
56
“Synopsys Extends HAPS-70 Prototyping Family with New Solution
Optimized for IP and Subsystems”, Synopsys press release, December
16, 2013, http://news.synopsys.com/2013-12-16-Synopsys-Extends-
HAPS-70-Prototyping-Family-with-New-Solution-Optimized-for-IP-
and-Subsystems
57
“Synopsys' New ProtoCompiler Software Speeds Time to First
Prototype by Up to 3X”, Synopsys press release, April 23, 2014,
http://news.synopsys.com/2014-04-23-Synopsys-New-ProtoCompiler-
Software-Speeds-Time-to-First-Prototype-by-Up-to-3X
58
“Cadence Strengthens Leadership in FPGA Design-In Solutions with
Acquisition of Taray”, Cadence Design Systems press release, March 22,
2010,
http://www.cadence.com/cadence/newsroom/features/pages/feature.a
spx?xml=taray
59
“ASIC Prototyping Simplified”, Cadence Design Systems white paper,
April 2011,
http://www.cadence.com/rl/Resources/technical_papers/asic_prototyp
ing_tp.pdf
60
“Cadence Announces Breakthrough in System Development to Meet
Demands of ‘App-driven’ Electronics”, Cadence Design Systems press
release, May 3, 2011,
http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.
aspx?xml=050311_sys_dev
61
“Cadence Announces Protium Rapid Prototyping Platform and
Expands System Development Suite Low-Power Verification”, Cadence
Design Systems press release, July 17, 2014,
http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.
aspx?xml=071714_Protium
44
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
As the cost of an SoC has escalated, the need for pre-silicon exploration
has increased. Tradeoffs in performance and power consumption are
part of nearly every design, especially mobile devices where recharging
factors heavily into user experience. Expanding software content must
be co-verified, with testing beginning long before production silicon is
available. Complex workloads present an opportunity for optimization
at the system level, if understood.
Diverse I/O interfaces and greater numbers of I/O pins motivate FPGA-
based prototyping board designers. High-speed connectors provide
flexibility with signal integrity. Common physical interfaces are now
45
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
46
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
The biggest changes may be in the design workflow. Design teams are
often geographically distributed, and access to a lab-based system is
impractical. Teams are also working together; a software developer may
use a small FPGA-based prototyping system to exercise an IP block,
then pass those results on to another team working on the fully
integrated design on a larger FPGA-based prototype. Enterprise-class
solutions are emerging, leveraging network connectivity and cloud
resources to connect and manage multiple FPGA-based platforms. This
reduces handoffs, improves scalability and reuse, and opens up access
across the globe 24/7 in a flexible, yet secure environment.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Some teams elect to use ARM’s hard macro IP offering, with optimized
implementations of cores. ARM has a mixed prototyping solution with
their CoreTile Express and LogicTile Express products. CoreTile
Express versions are available for the Cortex-A5, Cortex-A7, Cortex-A9,
and Cortex-A15 MPCore processors, based on a dedicated chip with the
hardened core and test features. The LogicTile Express comes in
versions with a single Xilinx Vertex-5, dual Virtex-6, or single Virtex-7
FPGAs, allowing loose coupling of peripheral IP. 64
48
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
However, as we have seen SoC design is rarely about just the processor
core; other IP must be integrated and verified. Without a complete pass
at the full chip design with the actual software, too much is left to
chance in committing to silicon. While useful, these other platforms do
not provide a cost-effective end-to-end solution for development and
debug with distributed teams. Exploration capability in a prototyping
environment is also extremely valuable, changing out design elements
in a search for better performance, power consumption, third-party IP
evaluation, or other tradeoffs.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Creating that trust is challenging. IoT design falls into three tiers: edge,
gateway, and infrastructure. Edge devices interface with sensors and
actuators, taking readings and interfacing with the physical world, and
most often connect wirelessly to a gateway. Incoming data is
aggregated and analyzed in gateways, then passed to an infrastructure
(often referred to as “the cloud”, but implementation can vary with use
cases) for further processing, storage, and presentation. Any weak link
in performance, power consumption, wireless signal integrity, security,
or other issues can cause a system-wide problem.
IoT applications will test the mettle of design teams. Rushing hardware
and software to market in order to declare “first” versus competition
may be counterproductive when flaws are uncovered. Business
customers in particular are proceeding very cautiously, asking for pilot
installations on a small scale before rolling out full-scale deployments.
SoC designers will need to customize, explore, test, and perhaps adapt
rapidly but carefully.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
NOTES
62
“Methodology of Multi-FPGA Prototyping Platform Generation”,
Qingshan Tang, Universit´e Pierre et Marie Curie - Paris, January 13,
2015, https://hal.inria.fr/tel-01256510/document
63
“Part 9: The 2014 Wilson Research Group Functional Verification
Study”, Harry Foster, July 19, 2015,
https://blogs.mentor.com/verificationhorizons/blog/2015/07/19/part-
9-the-2014-wilson-research-group-functional-verification-study/
64
“CoreTile Express”, ARM website,
https://www.arm.com/products/tools/development-boards/versatile-
express/coretile-express.php
65
“All Programmable Heterogeneous MPSoC”, Xilinx web site,
http://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-
mpsoc.html
56
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
58
Implementing an
FPGA Prototyping Methodology
FIELD GUIDE
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
61
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
earlier, simulation can only get you so far when dealing with
complex device behavior. Deep and accurate assessment can’t
be achieved simply through simulation no matter how many
regressions are done. Confidence in a design can often times
only be achieved through the ability to test it in real-time
scenarios especially for designs heavily dependent on timing
accuracy.
2) How many tests will you need to run and what is the
time window that needs to be achieved between testing
and implementation?
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Design Specifications
For the size of your design, think in terms of capacity. Without enough
gate-level capacity to accommodate your design, you can’t build a
prototype. Most systems need adequate memory too, so having
sufficient memory available is critical.
You also need to think about the type of application you are building. Is
it IoT, Automotive, Super Computing, Data Storage, Cloud Computing,
Image Processing, a Communication Network, or is it something else?
Is it a design that contains a large number of DSPs or does it require a
lot of logic resources or memory resources? Is it based on a specific
protocol like PCIe or a particular bus standard like AXI? There are
many different types of prototyping hardware and software solutions
that cater to these different application types. Some hardware boards
are flexible enough to scale with your design and allow you to adapt to
different design types through extensions and daughter cards while
others do not.
The design stage refers to when within your design methodology flow
you’ll implement FPGA prototyping. We talked earlier about the FPGA
prototyping sweet spot being used during software testing and
validation and that it is well suited for designs that are fully rendered in
RTL that can be mapped to an FPGA. However, recent advances in
FPGA prototyping technology have extended its value into other areas.
For example, many designs may not be completely mapped to an FPGA
and may be only partially available as behavioral models in descriptions
such as C++ or SystemC.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
range of capacities to fit your design size requirements. The larger your
design, the most likely you’ll need an FPGA or FPGAs with the capacity
to follow suit. Today’s FPGAs can handle designs of up to 44 million
gates. Even with these high-capacity FPGAs you must keep in mind
that the usable capacity of an FPGA is roughly 50-70% when
incorporated into an FPGA prototyping environment regardless of the
FPGA prototyping solution that is chosen. Given this fact and that most
designs scale beyond the limits of a single FPGA, a multiple FPGA
prototyping solution is the norm.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
limited memory size using FPGA internal memory, and long place-and-
route times to change probes. Debugging a design partitioned across
multiple FPGAs is all but impossible without a tool that helps set up
probes and makes signals easy to track based on their RTL-level names.
Debugging should use FPGA I/O efficiently and maintain a useful
debug trace.
Given the points made above, there are three options for the type of
FPGA prototyping platform you can implement. All of these options
utilize FPGAs from such vendors as Xilinx and Altera. Specifications
for each of these vendors’ latest FPGAs are shown below.
Whether you need scalability for your current design as you move
through the design and verification process or whether you need your
FPGA platform to be reusable and able to scale for future designs that
may be larger than your current one, it all starts with identifying and
selecting the ideal building blocks. The foundational prototyping board
you choose must have flexibility to expand so a custom platform is
usually out of the question as a custom board requires even greater
customization to grow. When crafting your platform, there are three
initial FPGA building blocks to evaluate: Single FPGA boards, Dual
FPGA boards, and Quad FPGA boards.
These comparisons don’t tell the whole story though. You must take a
closer look at the architecture for each of these solutions. Besides the
number of physical interconnections between FPGAs, the type (DDR3
or DDR4) and capacity (4GB, 8GB, or more) of on-board memory is
equally important to your design. Of additional interest should be the
number of high-speed gigabit transceivers and their performance level.
The following diagrams provide in-depth comparisons of each of the
architectures for single, dual, and quad FPGA prototyping boards.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
The type of I/O connectors used in the FPGA module may have a big
impact on your design mapping and performance. First, they must be
optimized for FPGA I/O banks, and even the FPGA die, in case some
FPGAs have multiple internal die. In addition, having I/Os from
different die will decrease performance. All traces from the FPGA to the
same I/O connector should have the same trace length to increase bus
performance. Connector performance itself may also play an important
role especially if the connectors are optimized for running high
performance LVDS (low voltage differential signaling), especially at
rates over 1 GHz.
Even with this flexibility, there are some implications to the number of
interconnects and I/Os when stitching together these systems. Careful
consideration must be given to which system you initially choose. You
will notice in the following diagrams that building these multi-FPGA
systems require the ability for the boards to be connected via cables or
interconnection modules. These systems will also need some sort of
external module to manage global clocking and reset mechanisms.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Space – How big of a desk or lab area do you need to work with a large
number of FPGAs? Although you can continue to stitch together
multiple prototyping boards to expand beyond a quad system, your
physical lab space may be limited making the connections of these
boards much more complicated. Not only will you be dealing with
space issues, but also the cabling of these systems will become very
unwieldy.
Scalability & Flexibility– What if you require more logic and memory
capacity or the system interfaces or memory types change? Can you
configure the large number of FPGA resources for multiple designs?
Because of the investment into large multiple board systems, these
reusability type questions become important. It is much easier to invest
in single board systems if the expectation is that the board will have
limited use beyond the initial design. However, when the initial design
requires the use of a larger prototyping system, your investment must
consider possible changes in the prototyping environments and future
project uses.
Image FG-7: S2C’s Cloud Cube supports any combination of FPGA boards,
and up to 8 Quad boards can fit into the chassis.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
A chassis system should easily support both single and multiple module
clock & reset requirements including available global clock resources
and types, internally generated clock, and clock skew. The diagrams
below illustrate how this is done.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
chassis system makes performing the following tasks much easier with
some having built-in automation:
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
77
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Setting Up a Prototype
A typical implementation flow for a prototype with multiple FPGAs
contains three general parts: Partitioning, Routing / Multiplexing, and
Place and Route.
After the design RTL is created and goes through the synthesis process,
it is then ready for the partitioning stage. As mentioned earlier, many
designs are larger than a single FPGA so the design must be
compartmentalized or partitioned into several FPGAs. Partitioning is
tricky as the design can’t simply be cut into equal parts based on the
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Place and Route is the last step, where the bitstream of each FPGA is
generated and downloaded into the platform to model the design.
Manual techniques only allow for debugging one FPGA at a time, and
traditional tools such as an external logic analyzer or FPGA internal
logic analyzer have limitations when it comes to multi-FPGA debug.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
With manual processes, only gaining insight into the behavior of one
FPGA at a time may result in missed design errors or misleading design
behavior as it becomes difficult to test the functionality of the design as
a whole. The part of a design that resides on a particular FPGA may be
bug-free in its compartmentalized form, but when operated within the
totality of the design may contain critical errors. External logic
analyzers have a limited number of probes and require designers to pull
their probes to the top level so they come out from the FPGA I/O pins.
Because of these issues, debug has been largely inadequate within the
FPGA prototyping process thus leaving debug to be done only through
simulation and/or emulation. But, hold on a minute. There have been
significant advances in FPGA prototyping to deal with the very complex
issue of multi-FPGA debug that augment the FPGA Prototyping Flow.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Because most designs today are IP-based (with functional blocks such
as CPU, GPU, and peripherals) the individual blocks are often smaller
than a single FPGA and can therefore be grouped at the IP level rather
than having to go through more fine-grained gate-level partitioning. As
an example one of the biggest ARM processor cores today, the ARM
Cortex-A57, can fit into one Xilinx Virtex UltraScale FPGA. Most IP
blocks have a manageable number of I/Os and partitioning algorithms
should be able to find the best grouping to minimize the number of
interconnects among FPGAs. The result is a much easier and smoother
partitioning experience.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
cycles. Utilizing commercial partitioning tools can save both time and
help improve the performance of your design.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
This solution is still widely employed and serves as the foundation for
today’s pin multiplexing. However, with advances in I/O technologies,
the need to serve multiple clock domains, and the increasing reliability
of pin multiplexing, many flavors of TDM have emerged to address
different design requirements.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Flavors of TDM
There are many flavors of TDM methods. TDM can be either
synchronous or asynchronous. TDM can be single-cycle or multiple-
cycles. Finally, TDM can use different I/O standards such as using
single-ended vs LVDS I/O.
Synchronous TDM
In addition, the difference between the fast clock and the design clock
can introduce issues. The timing diagram below shows an example of
this where event A is the sampling time for the fast clock, and event B
is the sampling time for the design clock – the setup time for both
needs to be the same as a single period of the fast clock.
And the interface between the two clock domains could contain a
critical path, especially when the TDM ratio is quite large. (This is true
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
even where all inter-FPGA nets are registered input/output.) This path
is often routed poorly inside the FPGA and usually suffers from timing
violations due to limited FPGA routing resources. This in turn
significantly decreases the speed of the fast clock which decreases the
speed of the design.
Finally, synchronous TDM typically supports only one clock per one set
of pins. Usually this requires stricter timing constraints that can be
hard to meet with a lot of pins, making it difficult to automate.
Asynchronous TDM
As for designs that use multiple clock cycles, they can run at full
transmission speed. However, since the data doesn’t get to the
destination in 1 design clock cycle, the designer must manually insure
this is okay for their design. This issue is design dependent, and as
result, can’t be automated.
With a TDM ratio of 4:1, the system clock speed will be around 17.8
MHz. If the TDM ratio is increased to 16:1, the system clock speed will
drop to less than 10 MHz. From this we can see that as the TDM ratio
increases the performance drops linearly.
However, using the LVDS I/O standard supported by Xilinx FPGAs, the
physical transmission data rate between FPGAs can achieve up to 1.6
Gbps. This offers tremendous advantages over single-ended
transmission, even when considering that a single LVDS signal requires
a pair of single-ended pins.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
88
PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
However, if your design can afford data to get from one FPGA to
another FPGA in multiple cycles, you can run at near full LVDS speed
divided by the pin-multiplexing ratio. Of course, this is limited to just
one clock domain and cannot accommodate mixing multiple clock
domains without modifying the design.
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PROTOTYPICAL: The Emergence of FPGA-based Prototyping for SoC Design
Let’s first take a look at the use of external logic analyzers that have
been in use for years. Popular external logic analyzers today are from
Agilent and Tektronix and can sample at GHz frequency and store GBs
of waveforms. External logic analyzers have the ability to store large
amounts of trace data but for the data to be useable, the data needs to
be taken off the chip, which can be a difficult task. The signals, or
probes, designers want to observe need to be sent to FPGA I/O pins to
connect to a logic analyzer. Since some probes may be buried deep
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Physically, you also need some kind of adapter card that connects the
FPGA I/O pins to the logic analyzer header. For example, Agilent logic
analyzers use a 38-pin Mictor connector. Most off-the-shelf FPGA
boards do provide optional daughter cards that can connect the FPGA
I/O pins to the 38-pin Mictor connector. If you are building your own
(RYO) board, then you should reserve a set of pins to connect to the
Mictor connectors if you choose to have the ability to observe through
a logic analyzer.
The biggest drawback for the use of external logic analyzers is actually
the limited number of probes you can observe at a time since there are
only a limited number of FPGA I/O pins you can use for debug. In most
designs, the majority of FPGA I/O pins are used for external target
interfaces or used as interconnects to other FPGAs if more than one
FPGA is used. Therefore, reserving a large amount of pins for
debugging through an external logic analyzer may not be feasible.
Multiplexing the probes to I/O pins can solve the limited pin issue but
is almost never used since external logic analyzers need to capture data
at real speed and also need to support de-multiplexing on the logic
analyzer side.
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the DDR3 memory content is sent to the host computer for analysis via
a high speed PC port such as Gigabit Ethernet. The waveforms in VCD
or FSDB format can then be debugged using popular waveform debug
tools such as Synopsys Verdi. Signals from multiple FPGAs can be
viewed in a single waveform window.
The use of a separate debug module of this nature allows for deep trace
with a large number of RTL-level probes, the use of minimal FPGA
resources to avoid design impact, and system-level debugging across
the entire SoC design. An example of this device is the Prodigy Multi-
Debug Module from S2C. The Prodigy Multi-Debug Module supports
up to 32 FPGAs at a time with 16GB of DDR3 trace buffer and can
utilize up to four 5GHz transceivers to capture waveforms from each
FPGA to the debug module. The use of Gigabit Transceivers allows
large amounts of data to be transmitted at high frequency. General
purpose I/O pins are not occupied by debugging so they can be used
for interconnecting between FPGAs and external interfaces. Deep trace
is achieved with 16GB or trace memory with actual trace depth
dependent on the number of signals that are probed. S2C also provides
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an easy-to-use GUI (as shown below) that allows you to mark probes in
RTL before synthesis, quickly locate probes after design partitioning,
and select probes before FPGA place-and-route.
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Finally, some newer FPGA families now support register and memory
readbacks and even allow you to set the register and memory content.
The readback feature enables you to access all nodes inside an FPGA at
a given time. However, to access that information you would need to
stop the design clock to shift out the register data. Therefore, this
feature can only be used when the design is run in a controlled clock
environment and not really useful when running FPGA prototypes in or
close to real time speed. In addition, just by taking a snapshot of what’s
inside an FPGA cannot solve the issue/bug you are looking for. Are you
taking the right snapshot and how many snap shots do you need to
take? Readback data is often shifted out through a JTAG port which is
also very slow when dataset is large. FPGA vendors do have plans to
improve this feature by allowing shifting out the readback data without
stopping the clock as well as using a faster protocol to shift out the
data. We hope to see better support of this feature from Xilinx and
Altera and also a complete environment that allows designers to
quickly see what they are looking for.
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can move on to the final topic of exercising the design and the methods
that are used to perform actual testing.
In-Circuit Testing
The common definition of In-Circuit testing is to connect your design
to real targets intended by your final chip for real world tests before
you have the silicon. FPGA prototyping, which can operate at or near
final chip speed. allows you to simply build those system target
interfaces either directly on the FPGA boards or through the use of
daughter cards.
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• What type of connectors are being used on the FPGA board and
how many daughter cards are available for that connector?
• Does the type of connector support high speed I/Os such as LVDS
and multi-GHz transceivers?
• How many connectors are available on the FPGA board so you
can connect to different targets at the same time?
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• How many I/O pins are on the connector and how are the I/O
pins/banks optimized on the connector?
• How will the daughter cards get power?
• What are the I/O voltages that are supported on the connector so
you can pass power from the FPGA board to the daughter cards?
• Are there physical limitations on the size of the daughter card
and how reliable is the daughter cards physically?
• Are the daughter cards testable?
• For an off-the-shelf daughter card, does the vendor provide tests?
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Hybrid Prototyping
In-circuit testing is probably the most important reason for doing
prototyping today. But in-circuit tests are usually based on un-
constrained random tests, which don't always ensure complete test
coverage. Using a transactor interface allows test cases developed in
simulation to be run directly on the prototype making these tests
instantly available and insuring compliance. Moreover, these tests can
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What about taking FPGA-based prototyping to the next level? How can
you maximize your FPGA prototyping experience? The next step in the
process is to code your design with FPGA prototyping in mind. This
topic was explored briefly by Mon-Ren Chene in his foreword to
“Prototypical” and will become a key launching point for the future of
FPGA-based prototyping. We look forward to providing you with the
knowledge you need to further your FPGA prototyping goals.
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About the Authors