Assignment-3 the work function of metal is 4.6 e V and electron ig level of 10'* cm”. Draw the equilibrium band ff the Fermi level, the band edges, and the vacuum level. Is this a net, and why? By how much should the metal work function be "reontact? Explain with reference to the band diagram. k function is given by = 4 +0.55eV + 0.0259In 2 = 5.02eV metal work function { @s > Orn] the contact cer is deposited over Si layer. T ‘Si is 4 eV, and acceptor dopin; QL. A metal lay‘ affinity of diagram and mark o! Schottky or ohmic cont altered to change the type o} Sol. For the p-type silicon material, the wor ty aw Os =x + 0.55eV + kTIn Bt Hence @s Since the semiconductor work function jis more than is schottky barrier contact, tion { 05 $ Om} is more or equal Jhmie contact when metal work fur i= = __ the junction becomes an ol eo fo semiconductor work function. The metal work function in this case must be raised to 5.02eV to make it an ohmic contact. mt V4. = 4X +E-O 2 Fa yrecnrety ea aA bad Tbe Te Q2 Find the maximum depletion wid ideal MOS capacitor with a 10-rim gs calculate after including the effects o1 and fixed oxide charge of 5 X 10" q (Clem’), Sol. The Fermi level of p-type Semiconductor is: -~ . 16 10’ 0.0259V x nexa0 = 0.347V =4,x+Eetareee |_| ox ayes’ depleting Schottky sad Obmic contact minimum capacitance Cj, and threshold voltage for an > odide (8:02) on p-type Si with N, = 10'°cm®. Also flat band voltage, assuming an n+ polysilicon gate Wy = ae ‘maximum depletion width Wom occurs at @s = 20 , 20387 — 3.01 x 10-Scm Therefore Wom is 0.3011m 5 5 ‘a9sx10-*(£) Mininzam Capacitance is Cy = sree Ga = 3.45 x 10°7F /em? Charge Qa = ~@NaWn = —1.6 x 10°19C x 101®em-#0,301 x 10cm, Hence, Qy = —4.82 x 107°C/cm? ‘Threshold voltage Vr = oh + 20p = RS + 2x 0.347 = 0.834V mae a _ Hexeesx10"(E ; ‘At maximum depletion, Ca got = nee = 3.47 x 10-8F /em? Minimum Capacitance is Cin, EAE = 3.15 x 10°F fom?‘Subjects VLSI Donign (ECA) Faculty: Dr. RAK. Chauhan 3 G2 Phoulel Ee ploen Bing SOAS. QB An Al-gate p-channel MOS transistor is made on an n-type Si substrate with Np = 5x 10"7 em”. The Sis thickness is 100 A in the gate region, and the effective interface charge Oy is 5X 10! qC/em’, Find maximum depletion width(Wp,), fat-band voltage (Voy), and é threshold voltage (Vr). Sketch the approximate C-V curve for this device, Sol. In this we have to determine Wm, Vin, and Vr and finally draw the C-V curve Np 5x10!” Oy = sKTin=? = ~0.0259V x Inorg = —0.449V OXO95XI0- 70.449 «9 49.194 em Wom = [S28 = DO cep) Sx!" Charge Qa = qNpWry = 1.6 x 10729. 5 x 10°7em="0.049 x 10-4em, Hence, Qq = 3:92 x'10-7¢/em? : wie . Minimum Capacitance is G; = & = 2220610 md Flatband voltage Vpp = Os ~ 2 = ~0.15 — MAO Masnt0" = _g.a79y s tag Threshold voltage Vp = Vzp + 20y ~ 24 = -0.173 - 0,898 — 1.136 = —2.27 = 3.45 x 10°7F Jem? yay Hy Atmaximum depletion, Cy = cS = “OOO NG «2.13 x 10-7 /em? Minimum Capacitance is Cin = ae = 1.32 x 10°7F fem? Q4 Calculate the Vr of -channel MOS transistor for an n+-polysilicon gate with silicon oxide thickness = 50 A, Np = 1 x 10" cm® and a fixed ace io gclont ein -mode device? What B dose is required to change the Vr to 0 V? : ‘Assume work function for an n+-polysilicon gate asQ5 Calculate the VT of an MOS capacitor wl Vist Design (@EC-41) Dr RK. Chauhan : Fesion _ » /HDRUuRKAOT NOG _ . Wom = [SBE = 2 pawxnasaerenste? =3.49x10%em = 16 x 10719C x 10!%cm=3 x 3,49 x 10-Sem, _ uexn07 P92. 029 6oxa0-? Hence, Threshold voltage Vr = Veg + 20 — 7 85V For Enhancement Mode P-Channel Device, to achieve Vr= OW a AVr = 1.85V is required Hence Qyoron = AVr X Ci = 1.85 x 6.9 x 1077 = 1.28 x 1076C/cm? Qvoren _ 1:28. 105° Boron Dost =o = Te a0- Charge Qa = IND Win Flat-band voltage Vw a 7.98 x 10*em™* here we deposit a high-k gate dielectric, HfO2, ‘whose relative dielectric constant is 25, on a novel p-type semiconductor whose electron affinity is 4 eV, band gap is 1.5 eV, relative dielectric constant is 10, and intrinsic carrier concentration is 10'2 cm”, The gate is made of a metal whose work function is 5 eV, gate ‘oxide thickness is 100 A, and Na is 10"* cr? and that has a fixed oxide charge of 5X 10" qC/cm*. At Vz, what are the cl centrations at the oxide-semiconductor stron and hole concer xide-s interface and deep in the subsirate?, Sketch a labeled band diagram normal to the surface at Vz, and mark off the relevant values on the bi asis of the numbers given. Sketch the low- and high-frequency C-V characteristics of this capacitor, and explain their differences How would the characteristics change at large negative gate bias if we doubled the oxide thickness? How about if we doubled the substrate Sol. In this we have to sketch the band diagram and CV characteristics and calculate the appropriate values. Ene Fig3. Energy-band diagram for large negative bias Work function=Ons = Om — 05 = 5- (4+ + .0259In 4) = only eae‘sunject: VLSI Design (BEC-41) Facufty: Dr. RIK. Chauhan ‘At Vr, at interface, n=10"cm? and p = 2 = 19"em? Deep in the substrate, n=10* and p=10""cm? ‘Athigh frequency, inversion electrons do not respond while at low frequency, they do ‘At large negative bias, doubling the oxide thickness reduces Q by 1/2 ‘At large negative bias, doubling the substrate doping does not change C, but would affect the depletion capacitances Saree ic Tas Frececy Tair v Fig: C-V plot for high frequency and low frequency Q6. Threshold voltage shift is observed in the fig.6(a), and (b) for varying channel length of n- and p-MOSFET. Give suitable reasons in support of your explanation for the cause in sift ee. | Tesh sobs (Y) be} Pk. oe a st + gba) (a) “5 $01.6. Fig. 6(a) and 6(b) shows that there is threshold voltage shift when the channel Iength is below 2um and it shift is high for channel length less than lym. This is due to short-channel effect (SCE), in which threshold voltage decreases as the channel length is reduced drstically. ‘The short-channel effect is therefore an important consideration in device design; one must ensure that the threshold voltage does not become too low for the device on the chip. In long-channel device, the source-drain distance is large enough and it's separation with their depletion regions have no effect on the potential or field pattern in most parts of the device. Whereas in a short-channel device, the source-drain distance is comparable to the MOS depletion width in the vertical direction, and the source-drain potential has a strong effect on the band bending over a significant portion of the device. QU-Threshold voltage sbift for varyit reverse substrate bias is shown in the fig.7(a), for two tgon‘The threshold voltage of a MOSFET, when its substrate is bias, is give here as: {2esaNa20a — Vos) Vz = Vey + 20¢ + G Vy f2esiqN,/2(205 — Vas) aes G It-can be seen from above Eq. that the effect of a reverse substrate bias (Vas < 0) is to widen the ean iar oe pee tees votre The substrate sensitivity is clearly described by the slope of the curve obtained as ~*~. a Te enreie) ca gurizestinty higher for higher bulk doping Nx and it decreases as the substrate increases and. same can be inferred from above eq. also. Q8. Three regions of operation of MOS is shown in the fig.8(a). and the drift and diffusion - Semponent is shown in the fig.8(0). Which region of operation involve drift and diffusion component of current and why?supjects VLSI Design (BEC-A1) Faculty! Dr. RAK. Chauhan In Fig. 8(b), the drain current is almost zero. ice in the subthreshold region where Vyy < Vo ‘ear scale appears 10 approach zero immediately below the threshold devi in current remains at non-negligible the drain current on a lin voltage. On a logarithmic scale, however, the descending drai Ievels for several tenths of a volt below Vj. This is because the inversion charge density does not drop to zero abruptly. The Subthreshold behavior is of particular importance in low-voltage, low. power applications, such as in digital logic ‘and memory circuits, because it describes how a MOSFET device switches off, ‘The subthreshold region immediately below Vx, where Oy < * Os $ 20g, is also called the weak inversion region. Drift current dominates in strong inversion region, i.e. when the gate potential is large enough to ‘cause inversion in the substrate region in the channel and transistor operates in saturation region, whereas the diffusion current dominates in subthreshold region when the gate potential ints arc included in is such that inversion region is about to take place: Both current compone! current computation, not to its individual components. In other words, the fractional ratio between the drift and the diffusion components may vary from one point of the channel to another, At low drain bias voltages, however, it is possible to separate the drift and diffusion components using the implicit function, It is clear that in weak inversion where Pp < Ps < 28» the numerator is much less than unity and the diffusion component dominates. Conversely, beyond strong inversion, “2! = 1 the drift current dominates over diffusion component. These kinds of behavior are further illustrated in Fig. 8b. : Q9. Calculate the Vy of a Si n-channel MOSFET for a gate-to-substrate work function difference Oms = —1.5 eV, gate oxide thickness = 100 A, Na = 10'8 cm®, and fixed oxide charge of 5 X'10"® gC/om?, for a substrate bias of -2.5 V. At Vr, what are the electron and hole concentrations at the oxide-Si interface and deep in the substrate? Sketch a labeled band diagram normal to the surface at Vr, showing the Fermi potential. Sol.9 The threshold voltage and flat-band voltage is given : 1,6x10779x5x108° = -1533V = 94 ttc ee Vp = Von + 207 ~ 24 and Vep = Oms — $f = ~1.5 — STS 8.85x10-'4F/om _ 2 ag 3.45 x 107F fom? Na x 10% Op = — In = 0.02590 x In = p= int = 0.02590 x Inge aig = 0467 With Van=-2.5V, depletion charge increases. Instead of band-bending of 20, itis (20 +Va), ° Ba DOTS G 345K 107 Vr=-1,533 V+0.934V+3.103V = 2.514V_ ‘Near the interface, (when bulk concentration is Nq=10'8 cm} under strong inversion region, the : x mobile charges are n=Nq and p = Zi = SSP" — 2.25 x 10%em? Vice-versa will be observed for bulk region where the mobile charges are n= 2.25 x 10%cm? and p=Navist Design (BEC41) sect Srna onaunan (Q10, For a MOSFET with Vr= 1V and Z = 50 wm, L = 2 wm, calculate the drain current at Vo = 5 V, Wp = 0.1 V. Repeat for Vo = 3 V, Vo = 5 V. Assume an electron channel mobility Ha = 200 cm2/V-s, and the substrate is connected to the source. Sol.10 For the MOSFET, we have to calculate the drain current (@)at Voz 5 V, when Vp=0.1V and (b)Repeat for Vox 3°V, when Vp = 5V (@ For Vo = 5V, Vo= 0. IV, since Vr= 1V, Hence Vo <(VorV1) —> linear region Zul 1 ZAG, —Vy Vp - 38 )= 682% 10-*4 = 5V, Since Vp >(Vo-V1) —» Saturation region Vp(sat) =V¢ + Vr =3-1=2 Zuc, seat, J thor (We =Vr)¥p(sat) — 1 VB) = 3,45 x 103A ID (b) for Vo= 3 V, when Voa 7: Fie Tond 2 thew 440 Mos Capasittoys TD ean ie Copertter by Fig 1 Had trmrulaite gnalouiol c > Co Hheckrerss 4,2 Imm Amel clelecbuic onstat €=4) owt 1 Cof Hacer te =3mm and dalubu'c wmstark €, =20). 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