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Unit3!1!8086 Pin Functions

The 8086/8088 microprocessor has various pins that serve different functions. It has a 16-bit data bus and address bus. Pins like AD0-AD15, A16-A19 serve to multiplex the address and data. Other pins like ALE, RD, WR control memory/I/O access. Status pins S0-S7 provide mode and segment information. Interrupt and bus control pins include INTR, NMI, HOLD, and HLDA. The 8086/8088 can operate in minimum or maximum mode based on the MN/MX pin state.

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Venkatesh Macha
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0% found this document useful (0 votes)
64 views

Unit3!1!8086 Pin Functions

The 8086/8088 microprocessor has various pins that serve different functions. It has a 16-bit data bus and address bus. Pins like AD0-AD15, A16-A19 serve to multiplex the address and data. Other pins like ALE, RD, WR control memory/I/O access. Status pins S0-S7 provide mode and segment information. Interrupt and bus control pins include INTR, NMI, HOLD, and HLDA. The 8086/8088 can operate in minimum or maximum mode based on the MN/MX pin state.

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Venkatesh Macha
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8086 Microprocessor

T.RANGA BABU,Dept.of ECE 1


T.RANGA BABU,Dept.of ECE 2
8086 / 8088 Pin Functions
Ø8086 16 bit mp with 16bit data bus / 8088 16 bit mp with 8 bit data bus
ØBoth are packaged in DIP (Dual In Line Packages)
ØVCC: +5v DC
ØGND: 0v
ØAD15 – AD0 : Multiplexed Bus
ØIf ALE = 1, Address Bus ; If ALE = 0, Data Bus
ØA19/S6 – A16/S3 : Multiplexed Bus
ØHigh order 4 bits of the 20bit address OR
ØStatus bits S6-S3

ØBHE / S7 : Bus High Enable. Enables the most significant data bus bits
(D 15 – D 8 ) during a read or write operation.
ØM / IO : Indicates Memory or I/O . when ‘1’ Memory, when ‘0’ I/O
ØRD : When 0, Data bus is driven by Memory or an I/O devices
ØWR : Microprocessor is driving Data Bus to Memory or I/O devices.
When 0, Data Bus contains valid DATA
T.RANGA BABU,Dept.of ECE 3
8086 / 8088 Pin Functions
ØALE (Address Latch Enable) : When 1, Address/Data bus contains a
Memory or I/O address
ØDEN (Data Bus Enable) : Activates external data bus buffers

ØDT/R (Data Transmit / Receiver): Data bus is Transmitting / Receiving data

ØMN / MX : Differentiate Modes of 8086 MP.

When 0, MP is operated in Maximum mode


When 1, MP is operated in Minimum mode

ØS7, S6, S5, S4, S3 : Status Signals in Minimum Mode

ØS2,S1,S0 : Status Signals in Maximum Mode

ØS7: Logic 1, S6: Logic 0.

ØS5: Indicates condition of IF flag bits.

ØS4-S3: Indicate which segment is accessed during current bus cycle

T.RANGA BABU,Dept.of ECE 4


8086 / 8088 Pin Functions
ØINTR : Interrupt, When 1 and IF=1, microprocessor prepares to service
Interrupt. INTA becomes active after current instruction completes.

Ø INTA: Interrupt Acknowledge generated by the microprocessor in


response to INTR. Causes the interrupt vector to be put onto the
data bus.
ØNMI : Non- maskable interrupt. Similar to INTR except IF flag bit is not
consulted and interrupt is vector 2.
ØCLK: Clock input must have a duty cycle of 33%
(high for 1/3 and low for 2/3s)
ØREADY:Used to insert wait states (controlled by memory and IO for
reads/writes) into the microprocessor.

ØRESET: Microprocessor resets if this pin is held high for 4 clock periods.
Instruction execution begins at FFFF0H and IF flag is cleared.

ØTEST : An input that is tested by the WAIT instruction. Commonly


connected to the 8087 coprocessor.

T.RANGA BABU,Dept.of ECE 5


8086 / 8088 Pin Functions
ØHOLD: Requests a direct memory access (DMA). When 1, microprocessor
stops and places address, data and control bus in high-impedance
state.
ØHLDA(Hold Acknowledge) : Indicates that the microprocessor has entered
the hold state.
ØRO/GT1 and RO/GT0 :Request/grant pins request/grant direct memory
accesses (DMA) during maximum mode operation.

ØLOCK : Lock output is used to lock peripherals off the system. Activated
by using the LOCK: prefix on any instruction.
ØQS1 and QS0 :The queue status bits show status of internal instruction
queue. Provided for access by the numeric coprocessor (8087).

T.RANGA BABU,Dept.of ECE 6


8086 / 8088 Pin Functions
ØS2,S1,S0: Indicates function of current bus cycle

S4 S3 Function S2 S1 S0 Function
0 0 0 Interrupt
0 0 Extra Segment Acknowledge
0 0 1 I /O Read
0 1 Stack Segment 0 1 0 I /O Write
0 1 1 HALT
1 0 Code or No 1 0 0 Opcode Fetch
Segment
1 0 1 Memory Read
1 1 Data Segment
1 1 0 Memory Write
1 1 1 Passive

T.RANGA BABU,Dept.of ECE 7


Simplified CPU Design

Data Bus

Data Registers
Control Arithmetic Status Memory
Unit Logic Unit Flags
Address Registers

Address Bus

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