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Proposed syllabus for 6 Semester M.TECH (VLSI
design and Microelectronics Technology) Course
Under Department of Electronics and
Telecommunication Engineering, Jadavpur University
PG Engineering Course (M.E. TEL.E)
(Theoretical Papers)

, Semester Paper Code

" 1 VLSI fabrication Technology MECE614 ~S.
Advanced Analog IC Design MECE 616 .~ pr
Semiconductor and Photonic MECE 520
-?~
Devices and Modeling
2 Advanced Digital IC Design MECE 617
Low Power VLSI Design MECE 634
Embedded and Real Time MECE 518
System
3 MEMS and NEMS MECE 615 '14 ~Cl!~.

Algorithm for VLSI Physical MECE 635

Design
ry' ~01
Quantum and Nanoelectronic MECE 618 ~pr06'
Devices (j)r>

4 VLSI Architecture and System MECE 619

Design ,
Advanced DSP MECE 516'
EMCIEMI and System Testing MECE 512
and Testable Design
5 Seminar MECE 600
5&6 Thesis Viva

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 Jadavpur University

Sessional Papers: (Two labs in each of four semesters)

Total Sessional Papers: 2x4=8

Lab Code Semester

Embedded System Lab MECE 533 2
Device Fabrication and Testing Lab MECE535 1 ~
Analysis and Design Using MATLAB, VHDL and SPICE -I MECE 536/1 2
Analysis and Design Using MA TLAB, VHDL and SPICE -II MECE 536/11 3
DSP Lab MECE 540 4
VLSI Design Lab MECE 543 4
MEMS and Sensor Lab MECE 544 3.
Circuit & System Lab MECE 545 1

Marks Distribution

Semester Total Full Sessional Full Total

Papers Marks (Lab Marks
Assignment)
1st 3 300 2 200 500
2nd 3 300 2 200 500
3rd 3 300 2 200 500
4th 3 300 2 200 500
5th 1 (Seminar) 100 -- -- 100
s" & 6th Thesis Thesis Viva 300+100 400
Total 2500
 SEMESTER 1:

PAPER 1: VLSI Fabrication Technology

Clean room concept, Growth of Single crystal silicon - Czochralski and Float zone method, wafer
processing, cleaning and etching.
Physical vapour deposition ; Vacuum evaporation sputtering. Chemical vapour deposition -
APCVD, Plasma CVD, MOCVD.
Epitaxial gro~h : Liquid phase epitaxy, vapour phase epitaxy, Molecular beam epitaxy;
Heteroepitaxy.
Oxidation: Growth mechanism and Kinetics of oxidation, oxidation techniques and systems,
oxide properties, oxide-induced defects.
Diffusion : Fick's equations; Atomic Diffusion mechanisms, Measurement techniques, Diffusion
in Polysilicon and Si02, Diffusion Systems.
Ion Implantation : Range Theory, Equipments, Annealing, Shallow junction, High energy
implantation.
lithography: Optical lithography; optical mask printing and making techniques, electron
lithography, X-ray lithography. '
Plasma Deposition and Etching: Plasma properties, plasma assisted depositions of Polysilicon,
silicon dioxide and silicon nitrides; Reactive plasma Etching techniques and equipment; specific
etch processes.
Metallisation : Metallisation Application, Patterning Interconnects, Multilayer metallisation,
Measurement.
VLSI Process Integration : Microcircuit technologies; Thick/thin filrT; technology and
formulations; design of components, substrate and properties; deposition techniques; applications
- MICs; thermal analysis; design rules for hybrid circuits; Bonding techniques; Passivation; Die
bonding testing; Quality control; Packaging - types and usages.Fundamental considerations of IC
technology, NMOS and CMOS IC processing; MaS Memory IC processing, Bi CMOS
processing.

PAPER 2: Advanced Analog IC Design

Basic MaS device and model. CMOS inverter, characteristics, transient response and delay analysis,
power considerations.
MaS resister, MaS current source, current mirror circuits: design and performance enhancement
issues, MaS voltage source, design and improvement considerations. linear voltage and current
converters.

CMOS operational' amplifier (OP AMP) design techniques and performance characteristics ,
differential amplifier, level shifter, source follower, output stage voltage and power amplifiers.
Compensation techniques, opamp instrumentation in low and high power circuits; Phase lock
techniques; PLL design parameters and systems; Analog multipliers and modulators, NO and D/A
conversion: sampling and quantization. '

BieMOS circuit techniques: BiCMOS device and technology, basic analog subcircuits, low-
voltage SiCMOS, operational amplifier design.

Analog Filters: Switched capacitor (SC) fundamentals" first order and higher, second-order SC
circuits and cascade design, analytical techniques for SC circuits; SC ladder filters, switched current
filters.

'Analog VLSI Interconnects: Physics of interconnects in VLSI, scaling of interconnects, distributed

RC model, transmission line model. Improvements in interconnect performance, future interconnect
technologies.

RFIC Design: Introduction to MOSFET Devices, MOSFET modeling, Spice model, Device parasitics,
RF modeling, Parasitics sensitive to RF. Issue in RF IC a brief review, Impedance matChing, use and
design of passive circuits, LNA Design, Matching Techniques using algebra techniques, Basic Bond
circuits, UHF Mixer design. Cross talk, Cross connect architecture, Cross Connect characteristics,
classification, Cross connect mechanism, Cross connect mitigation, Cross connect reduction,
multiple Cross connect sources.

PAPER 3: Semiconductor and Photonic Devices and Modeling:

MaS structures and their characteristics; surface space charge regious and either characteristics;
properties of silicon-silicon dioxide systems, MIS diodes and CCDS.

MOSFETs; analysis of MOSFET parameters; short channel and narrow width effects; hot electron
effects; MOSFET models; JFET and MESFETs; Modulation doped FETs; Heterojunctions and
HBTs; microwave and optonic devices; outline of numerical approach to 20 and 3D device
models; Introduction to device simulation programs.

Photonic Devices: Optical processes in semiconductors; Light-emitting diodes; Laser operating

principles; Semiconductor laser structures; Solid-state and gas lasers, Photodetectors, Receiver
noise considerations; Special detection systems; Solar cells; Optoelectronic modulation and
switching devices; Liquid crystal devices; porous silicon optical devices; Optical integrated circuits
and its processing and applications. Integrated optics, optical waveguide components,
acoustoopical and electrooptical devices, optical radar.

Microwave and Millimeter wave Devices: Amplifiers - Microwave semiconductor devices and
models; Power gain equations, stability, impedance matching, constant gain and noise
figure circles; Small signal, low noise, high-power and broadband amplifier designs.

Oscillators - One port, two port, YIG dielectric and Gunn-diode oscillators.Two terminal
microwave devices and circuits:PIN diodes and uses as switches, phase shifters and limiters;
Varactor diodes, IMPATT and TRAPATI devices, transferred electron devices. Microwave
BJTs. GaAs FETs, low noise and power GaAs FETs and their applications. Microwave
Mixers.

Device Modeling: MOSFET Structure and Operation, SPICE Model of the MaS Transistor: The
Simple MaS DC Model, Semi Empirical Short Channel MaS (LEVEL 3), BSIM Model (LEVEL 4),
MaS Capacitance, CMOS Low Vottaqe Analytical Model, Threshold Voltage Definition,
Subthreshold Current, Low Voltage Drain Current, CMOS Power Supply Scaling, Modeling of
Bipolar Transistor: BJT Structure and Operation, Ebers-Moll Model, Bipolar Model in SPICE.

SEMESTER 2

PAPER 4: Advanced DigitallC Design

MOSFET capacitances. MaS inverters, CMOS inverter, static characteristics, switching

characteristics, power dissipation issues. Combinational MaS Logic Circuits: MaS logic circuits
with depletion loads, CMOS logic gates, complex logic gates, CMOS transmission gates.

Pseudo-nMOS, domino logic gates. Multilevel gate circuits and design. Sequential MaS Logic
Circuits: The SR latch circuit, clocked latch and flip-flop, CMOS D-Iatch and edge triggered
circuits, Schmitt trigger circuit CMOS Logic Families Including Static, Dynamic and Dual Rail
logic.
 Dynamic Logic Circuits: Pass transistor logic, synchronous dynamic circuit techniques, high-
performance dynamic CMOS circuits.

Semiconductor Memories: ROM circuits, SRAM circuits, DRAM circuits, drivers and buffers,
design issues in memory and array structures, Memory Testing and Reliability Issues, Memory
Cards, High Density Memory Packaging, Future Directions, Introduction to digital tablet PC, LCD,
DVD player etc.

Introduction to hardware description languages (VHDL, VERILOG), logic, circuit and layout
verification, Design examples.

BiCMOS Logic Circuits: Basic BiCMOS circuits, static behavior, switchinq characteristics in
BiCMOS logic circuits, BiCMOS applications.

Input-Output Circuits: ESD protection, input and output buffer design, on-chip clock generation
and distribution, latch- up and its prevention.

PAPER 5: Low Power VLSI Design

Why low power? Low Power Application, Low Power Design Methodologies: Power reduction
Through Process Technology, Power reduction Through CircuiULogic Design, Power Reduction
through Architectural Design, Power Reduction through Algorithm Selection, Power Reduction in
System Integration, Low Voltage Process Technology, Low Voltage Device Modeling, Low
Voltage Low Power VLSI CMOS Circuit Design, Low Voltage BiCMOS VLSI Circuit Design, Low
Power CMOS RAM, VLSI CMOS Subsystem Design, Low Power VLSI Design Methodology,
Multi-threshold CMOS, SOI-MOSFET design issues.

Overview of Power Consumption: Dynamic, Short Circuit and Leakage Power Consumption,
Controlling Factors for Power Dissipation, Delay and Power Optimization. Power Saving:
Minimizing Activity, Minimizing Glitches, Minimize Capacitance and Wire Length of Nodes with
High Activity, No limit to Power Consumption-Adiabatic and Semi-adiabatic Logic, Supply
Voltage, Lost Performance Compensation by Parallelism, Voltage in Sleep and Active Mode,
Reduction of Voltage Swing over Long Wires, Continuous Voltage Adoption as p-Lead, Threshold
Voltage Reduction, Need of Two Threshold Voltages in the Same Circuit, Most Probable Future
Supply Voltage.

Low Voltage Process Technology: CMOS Process Technology: N-well Process Technology, Twin
Tub CMOS Process, Low Voltage CMOS Technoloqy. Bipolar Process Technology, Isolation in
CMOS and Bipolar Technologies: CMOS Devices Isolation Technique, Bipolar Devices Isolation
Technique, CMOS and Bipolar Process Convergence, BiCMOS Technology: Low Cost BiCMOS
Process, Medium Performance BiCMOS Process, High Performance BiCMOS Process,
Complementry BiCMOS Technology, SiCMaS Design Rules, Silicon on Insulator.

Low Voltage Low Power VLSI CMOS Circuit Design: MaS Inverter: DC Characteristics, Transfer
Characteristics, Effect of p, Noise Margin, Minimum Power Supply, Example of Noise Margin,
switching Characteristics: Analytic Delay Model, Delay Characterization with SPICE, Power
Dissipation: Static Power, Dynamic Power of the Output l.oad, Short Circuit Power Dissipation,
Other Power Issues, Capacitance Estimation: Estimation of Cin , Parasitic Capacitance, Wiring
Capacitance, CMOS Static Logic Design: NAND/NOR Gates, Complex CMOS Logic Gates,
Switching activity Concept, Switching Activity of Static CMOS Gates, Glitching Power, Basic
Physical Design, Physical Design Methodologies, Static Latch, CMOS Logic Styles: Pseudo
NMOS Logic, Clock Skew in Dynamic Logic, Clocking: Storage Elements, Single Phase Clocking,
 Two Phase Clocking, Pass Transistor Logic Families: CPL. DPL, Modified CPL, Logic
Comparison, I/O Circuits: Input Circuits, Schmitt Trigger, CMOS Buffer Sizing, Clock Drivers and
Clock Distribution, Output Circuit, Ground Bounce, Low Switching Output Circuit, Low Power
Circuit Technique: Low Static Power Technlque, Low Dynamic Power Technique, Adiabatic
Computing.

PAPER 6: EMBEDDED AND REAL TIME SYSTEM:

The concept of embedded systems design, Design methodologies, Design metrics, Specialties,
Concepts and types of memories, Cache memory, Cache mapping technique, Replacement
policies, Cache wire techniques, Cache impact on system performance, Examples of Embedded
Systems, Technological aspects of embedded systems: interfacing between analog and digital
blocks, signal conditioning, digital signal processing. sub-system interfacing, interfacing with
external systems, user interfacing. Design trade offs due to process compatibility, thermal
considerations, etc.

Embedded microcontroller cores, Embedded memories, Embedded Computer Organization,

Embedded RISC processors, Memory controllers, Communication processor module and serial
interface, Serial management controller and serial communication controller, UART, HDLC and
Ethernet protocol, SOMA channels and IDMA emulation. ~

ARM 7/ARM 9 architecture, ARM microcontroller and processor cores, Instructions and Data
handling, Interfacing with memories, Interrupts, Timers, ARM Bus, I/O Devices, Controllers,
Simple and autonomous I/O controllers, Parallel, Multiplexed, Tristate and Open drained buses,
Bus protocols, Serial transmission techniques and standards, CAN and advanced buses, Design
optimization, Area optimization, Timing optimization and Power optimization.

Software aspects of embedded systems: Real-Time system concepts, Kernel structure, Task
management, Inter task communication & synchronization, Real time programming languages and
operating systems for. embedded systems; Methodologies and technologies for behavioral
synthesis, system synthesis and real-time issues in embedded systems, hardware/software co-
design, interface synthesis, scheduling, real-time constraints, real-time specification and
modeling, transformation and estimations during synthesis and design optimization.

SEMESTER 3

PAPER7:MEMSandNEMS

Micro and Nanoelectromechanical Systems: Fundamentals of microelectromechanical systems

(MEMS) microsensors and microinstruments. Advanced discussion of micromachining processes
used to construct MEMS. Coverage of many lithographic, deposition and etching processes, as
well as their combination in process integration. Materials issues such as chemical resistance,
corrosion, mechanical properties and residual/intrinsic stress. Introduction to MEMS design.
Design methods, design rules, sensing and actuation mechanisms, microsensors and
microactuators. Measurement principles for MEMS transducers. Design methods and design
constraints for sensitivity and stability. Implementation of control methods for improving
measurement sensitivity, linearity and reproducibility.

Mechanical, Inertial, Bioloqlcal, Chemical, Acoustic, Microsystems Technology, Integrated Smart

Sensors and MEMS, Interface Electronics for MEMS, MEMS Simulators, MEMS for RF
Applications, Bonding & Packaging of MEMS, Conclusions & Future Trends.
 Nano Electromechanical systems; nanofabrication and measurement techniques, Applications
with special attention to biomedical application.

PAPER 8: Algorithms for VLSI Physical Design

VLSI Physical Design Automation: VLSI design cycle, physical design cycle, design styles,
system packaging, Logic Synthesis and Verification: Logic synthesis, Binary decision diagram,
Hardware model for high level synthesis.

Data Structure and Basic Algorithm: Algorithms for NP hard problems: exponential algorithm,
special case algorithm, approximation algorithm, heuristic algorithm, basic algorithm: graph
search algorithm, spanning tree algorithm, shortest path algorithm, matching algorithm, max cut
and min cut algorithm, Steiner tree algorithm, line sweep method, extended line sweep method.
Data structure: atomic operations for layout edition, linked list of blocks, bin-based method,
neighbor pointer, corner stitching, multi layer operation, limitation of existing data structure, layout
specification language, graph algorithm for physical design: graph related to a set of lines, graph
related to set of rectangles, relationship between graph classes, graph problem in physical
design, algorithm for interval graph, algorithm for permutation graph, algorithm for circle graph.

Partitioning: Design style specific partitioning problem, classification of partitioning algorithm,

group migration algorithm, kernighan-lin algorithm, simulated annealing and evolution, other
partitioning algorithm, performance driven partitioning.

Floorplanning and Pin Assignment: Floorplanning: design style specific tloorplanning problem,
classification of tloorplanning algorithm, constraint based tloorplanning, integer programming
based tloorplanning, rectangular dualizaiton, hierarchical tree based methods, tloorplanning
algorithm for mixed block and cell design, simulated evolution algorithm, timing driven
tloorplanning, theritical advancement in tloorplanning, , chip planning, pin assignment,
classification of pin assignment algOrithm)general and channel pin assignment.

Placement: Design style specific placement problem, classification of placement algorithm,

simulation based placement algorithm: simulated annealing, simulated evolution, force directed
placement, sequence pair technique, comparison, partitioning based placement algorithm:
breuer's algorithm, terminal propagation algorithm, cluster growth, quadratic assignment, resistive
network optimization, branch and bound technique, performance driven placement.

Global Routing: Classification of 'global routing algorithm, maze routing algorithm: lee's algorithm,
Soukup's algorithm, Hadlock's algorithm, comparison of maze routing algorithm, line probe
algorithm, shortest path based algorithm, Steiner tree based algorithm: separability based
algorithm, non-rectilinear Steiner tree based algorithm, Steiner min-rnax tree based algorithm,
weighted Steiner tree based algorithm, integer programming based approach, performance
driven routing.

Detailed Routing: Routing consideration, routing model, channel routing model, switchbox routing
problem, design style specific detailed routing problem, classification of routing algorithm,
general river routing algorithm, single row routing problem, two layer routing algorithm:
'classification, LEA based algorithm, constrained graph based routing algorithm, greedy channel
router, hierarchical channel router, comparison of two layer channel router, three layer channel
routing algorithm: classification, extended net merge channel router, HVH routing from HV
solution, hybrid HVH-VHV router, multi layer channel routing algorithm, switchbox routing
algorithm: classification, greedy router, rip up and re route based router, computational geometry
based router, comparison of switch box router.
 Over the Cell Routing and Via Minimization: Cell models, two layer over the cell routers, three
layer over the cell routers, multilayer over the cell routers, via minimization: graph representation
of two layer constrained via minimization problem, unconstrained via minimization: optimal
algorithm for crossing channel TVM problem, approximation result for general k-TVM problem,
routing based on topological solution.

Clock and Power Routing: Clocking scheme, design consideration for the clocking system, delay
calculation for clock trees, design style specific problem, clock routing algorithm: H-tree based
algorithm, the MMM algorithm, geometric matching based algorithm, weighted center algorithm,
exact zero skew algorithm, DME algorithm, skew and delay reduction by pin assignment, multiple
clock routing, power and ground routing.

Compaction: Classification of compaction algorithm, one dimensional compaction: constraint

graph based compaction; virtual grid based compaction, one and half dimensional compaction,
two dimensional compaction, hierarchical compaction, resent trends.

PAPER 9: Quantum and Nanoelectronic Devices

Quantum and Nanoelectronic Devices and Systems: Foundation: Wave mechanics and
the Schrodinger Eq., Free particles, Bound particles: Quantum Mechanics ofNanometric
structures, Concept of Quantum well, quantum wires, Fundamentals of carrier transport
in quantum structures, Charge and current densities, Operators and Measurements, Math
properties of Eigenstatics, Counting states, Occupation of states Electrons and Phonons in
crystal : Band structures in ID, Motion of electrons in Band, Density of states, Band
structures in two and three dimensions, Phonons. Heterostructures (HS): General
properties of Heterostructures, Bandgap Engineering, Layered structures: Quantum well
and barriers, Doped Heterostructures, Strained layers, Si-Ge Heterostructures, Effective
mass in HS. Quantum wells and Low dimensional systems: Infinite deep square well,
finite deep well, parabolic well, Low dimensional systems, Quantum well in HS,
Superlattice and Miniband, Tunnelling in HS, The Quantum Hall effect: Longitudinal and
Hall Conductivities and Resistivities, Filling Factor, Integer Quantum Hall Effect,
Cllasical theories and quantum mechanical treatment, Transition between quantum' hall
states, Low field quantum hall effect, International standards of resistance and structure
constant. Optical absorption in QW, Band diagram, Modulation doped FET, Scattering
mechanisms in QW. Optical properties in Low dimensions: Optoelectronic Interaction in
Quantum structure, Valence band structure, Bands in QW, Inter sub band transistions in
QW, Optical laser, Exitons, Quantum effect nanoelectronic devices: Resonant tunneling
diode, QW Laser, QW detector, Modulator and Switch.

Emerging nanoelectronics: Basic concepts on molecular electronics, spintronics and

carbon nanotubes (CNT), Single Electron Devices: Introduction, Fabrication, Tunnel
junction, Coulomb blockade, coulomb island, double tunnel junction, Single Electron
Transistor (SET) characteristics, Spintronic devices, Quantum Dot Structure, Spintronic
devices including Magnetoresistence sensors in hard disks, Magnetic RAM, Magnetic
Tunneling Transistors, Spin FET, Spin dependent transport and Diluted magnetic
Semiconductor, Application of SET and Spintronic devices for the realization of some
sequential and combinational circuits.
 SEMESTER 4

PAPER 10: VlSI Architecture and System Design

The Impact of VlSI on Computer Architecture, VLSI Technology Overview and Trends,
Dedicated and programmable VLSI architecture, Instruction set and through enhancement
techniques (parallelism, pipelining, cache etc), VLSI design methodologies: Custom, semi-
custom, synthesis, simulation and verification at the system, behavior, logic, circuit and layout
levels. (Data path synthesis, bit slice approach, structured logic-control: ad hoc, finite state
machines, use of PLAs.), Advanced Microprocessor Architecture and Memory Systems in VLSI,
Multi-Processor Arrays and Interconnect Topologies: Architectures and algorithms, systolic arrays
methods, Timing Design of VLSI systems: Asynchronous' schemes, Timing and clocking-
asynchronous versus synchronous, single and two-phase clocking schemes, clock generation,
buffering and clock distribution, CPLD Structure, Programming Techniques, Device
Dependent/Independent, Technologies, Tips & Tricks Rules.

CISC Architecture Concepts: Typical CIC instruction set and its VLSI implementation, RT-Ievel
optimization through hardware Charting, Design of the execution unit, Design of the control part
(micro programmed and hardwared) Handling exceptions: Instruction Boundary Interrupts,
Immediate Interrupts and Traps.

RISC Architecture Concepts: Typical RISC instruction set and its VLSI implementation,
Execution pipeline, Benefits and problems of pipelined execution, Hazards of various types of
pipelined stalling, concepts of scheduling (static and dynamic) and forwarding to reduce/minimize
pipeline stalls exceptions in pipelined processors.

Introduction to ASIC: Full custom ASIC, standard cell based ASIC, gate array ASIC, channeled
gate array, channel less gate array, structured gate array, programmable logic device, design
flow, Modeling combinational and sequential circuits, ASIC construction, Simulation ,Verification
of complex logic design model, verification issues like verification plan, verification methodology,
timing verification, Hardware design verification, Software design verification ,verification strategy
for ASIC bus functional models, verification Automation, physical verification, Layout planning and
verifications, ASIC design flow and HDL based ASIC design flow, EDA tools for ASIC design,
Mixed signal design.

FPGA Design and Architecture: Introduction and fundamental concepts, The origin of FPGA,
FPGA Architecture and Design Flows, Technology Mapping, Physical Synthesis, Design and
Synthesis with High Level of Abstraction, Power Optimization.

System Design: Introduction, Variable Resistor Delay, Interconnection Network, Non-numeric

Processor, Arithmetic processor, Serial-parallel multiplier, Parallel multiplier, multiply-accumulate
. circuit, neural networks, genetic Algorithm based optimization, Signed and Unsigned
Comparators, Fixed point division.

PAPER 11: Advanced DSP

Advanced Digital Signal Processing: Brief recapitulation of linear & circular convolutions, linear
filtering, OFT, Goertzel and chirp-z transform algorithms, Radix-4 FFT algorithms, Quantization
errors in FET algotithms, Linear Phase FIR filters, realizations, design using Rectangular window,
Bartlett window, Hanning window, Hamming window, Kaiser window, FIR filter design using
MATLAB. Multirate signal processing, decimation, interpolations, ~nmpling rate conversion,
Filters in sampling rate alternation systems, MATLAB examples, Polyphase decomposition. Filter
banks, decimation & inverse decimation, M-band filter banks, reconstruction, transmultiplexers,
QMF & CQF filter banks, Cosine-modulated filter banks, Lapped Orthogonal Transforms, wavelet
transforms. Programmable Digital Signal Processors, Multiplier Accumulator, Modified bus
structures, VLlW architecture, pipelining, Addressing Modes, On-chip peripherals. MAC, Barrel
Shifter, ALU, Multipliers, dividers, VLSI Architecture for DSP and DSP programming, Instruction
pipelining, analog interfacing circuits & applications, introduction to FPGA based DSP system
design. TMS320C5X DSP, Architecture, Assembly" Language instructions & programming,
Blackfin processor.

PAPER 12: EMC/EMI and System Testing and Testable Design

EMC/EMI:
Concepts of EMI and EMC: The wave equation, Waves in dielectric and lossy media, Planner
and quasi planner transmission structure-analysis and design, The applications of MICs and
MMlcs, Common EMC units, EMC requirements for electronic systems, radiated emission,
conducted emission, ESD, application of EMC design, prevention of ESD events, system design
for EMC.

System testing and Testable Design:

Introduction to VLSI testing and Verification, Issues in test and verification of complex chips,
embedded cores and SOCs, Fundamentals of VLSI testing, Fault models, Automatic test pattern
generation, Design for testability, Scan design, Test interface and boundary scan, System testing
and test for SOCs, Iddq testing, Delay fault testing, BIST for testing of logic and memories, Test
automation, Design verification techniques based on simulation, analytical and formal
approaches. Functional verification, Timing verification, Formal verification, Basics of equivalence
checking and model checking, Hardware emulation, Basics of test generation, test evaluation and
test application, Methods and algorithms, Practical test issues. Fault models for logic .and
memories, Design for testability (DFT, Scan test methodologies. Comparative tradeoffs,
Embedded core test, System test, Test interfaces, JTAG and boundary scan, Test integration,
Memory and memory interface logic testing, Delay fault testing.