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1101.2 BlkDiag ClockLock

The document shows a block diagram of an Optimod-PC ClockLock device. It receives multiple digital audio inputs and word clock references and uses an FPGA and PLL to generate locked digital audio and word clock outputs at various sample rates including 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz.

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48 views1 page

1101.2 BlkDiag ClockLock

The document shows a block diagram of an Optimod-PC ClockLock device. It receives multiple digital audio inputs and word clock references and uses an FPGA and PLL to generate locked digital audio and word clock outputs at various sample rates including 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz.

Uploaded by

Anonymous j5apk2Aum
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital 1 IN Digital 1 OUT

32 kHz 32 kHz
44.1 kHz 44.1 kHz
48 kHz SRC SRC 48 kHz
88.2 kHz AES/EBU AES/EBU 88.2 kHz
96 kHz 96 kHz

Digital 2 IN Digital 1 OUT


DSP
32 kHz 32 kHz
44.1 kHz 44.1 kHz
48 kHz SRC Mixers SRC 48 kHz
88.2 kHz AES/EBU Processing AES/EBU 88.2 kHz
96 kHz Routing 96 kHz

Digital Audio Outputs Locked to Clock


Word Clock

32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
10 MHz ×/÷

Digital Clock References

Digital ClockLock™ Reference


FPGA
INT Clock
EXT Sync Digital IN 1
EXT Sync Digital IN 2
EXT Sync Word Clock/10MHz IN

INT Clock INT Clock Disables PLL


VCXO PLL

48 kHz

Wave 1 IN Wave 1 OUT

32 kHz 32 kHz
44.1 kHz SRC SRC 44.1 kHz
48 kHz Windows Windows 48 kHz
88.2 kHz Kernel Kernel 88.2 kHz
96 kHz Audio Audio 96 kHz

Audio Plays/Decodes Locked to Clock Audio Records/Encodes Locked to Clock


Wave 2 IN Wave 2 OUT

32 kHz 32 kHz
44.1 kHz SRC SRC 44.1 kHz
48 kHz Windows Windows 48 kHz
88.2 kHz Kernel Kernel 88.2 kHz
96 kHz Audio Audio 96 kHz

orban
1101 Optimod-PC ClockLock™ Block Diagram
Digital Audio Clock Signals
GOGONOWSKI 2009/09

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