2 Microprocessor 8085
2 Microprocessor 8085
Instructions
Binary Codes Microprocessor Processed
Hexadecimal Programs
(Data Processor) Data
Codes
Mneumonics
Low Level
Language/Machine
Language
Hexadecimal Code
language
Assembly Language Input Data
High Level Language • Memory
• IO Device
Assembler
Assembly Language
Machine Language
program ASSEMBLER
Program (memory)
Instructions
LABEL: OPERANDS (If ; Comments
MNEUMONIC
required) (Optional)
Examples:
MVI C, 05H
LXI D, 2005H
Continue: LDAX D
ADD B; Adds eight bit data of accumulator A and register B and stores result in register A
JC BypInstr
INR B
BypInstr: INX D
DCR C
JNZ Continue
OUT 80H (STA 8000H)
MOV A, B
OUT 81H (STA 8001H)
RST1/HLT
PROGRAM MEMORY
Instruction codes CONTENTS
Address Codes
8000 21
PROGRAM
ASSEMBLED 8001 00
MEMORY MENUMONICS
CODES 8002 40
ADDRESS
8003 0E
8000 LXI H 4000h 21,00,40 8004 04
8003 MVI C 04 0E, 04 8005 06
8005 MVI B 00 06, 00 8006 00
8007 3E
8007 MVI A 00 3E, 00 8008 00
8009 VERTADD: ADD M 86 8009 86
800A JNC SKIPCARRYACCUM D2, 0E, 80
ASSEMBLY 800A D2
800B 0E
800B INR B 04
800C 80
SKIPCARRYACCUM: INX 800D 04
800E 23
H 800E 23
800F DCR C 0D 800F 0D
8010 JNZ VERTADD C2, 09, 80 8010 C2
8011 09
8013 MOV M A 77
8012 80
8014 INX H 23 8013 77
8015 MOV M B 70 8014 23
8016 RST 1 CF 8015 70
8016 CF
Instructions
MOV C D MOV A C
LDA 1000h
LXI H 1000h
MOV M C
MOV D A MOV C E MOV C A
MOV E A
RST 1 LDA 1001h
LXI H 1001h
MOV A B MOV M B
MOV B A
MOV B D
MOV D A SOLUTION 2:
RST 1 //USE HL PAIR INTERFACE
1. READ MEMLOCATION DATA IN HL.
2. EXCHANGE HL AND DE
SOLUTION 2: 3. COPY BC RP TO HL
4. COPY DE RP TO BC
5. COPY HL PAIR DATA TO MEMLOC
LXI B 0050h LXI B 1234h
LXI D 5000h
XCHG LXI H 1000h
MVI A 50h
MOV M A
MOV A C
MOV C L INX H
MOV L A MVI A 05h
MOV M A
LHLD 1000
MOV A B XCHG
MOV B H MOV L C
MOV H B
MOV H A
MOV C D
MOV B E
XCHG
SHLD 1000
RST 1
RST 1
Data Exchange Programs
4. Exchange memory contents of 1000H and 1001H 5. INTERCHANGE 16 BIT MEMORY
SOLUTION 1: LOCATIONS AT 1000H AND 2000H
//USE Accumulator to read individual bytes from memory and //USE HL PAIR INTERFACE
write in reverse manner
LXI H 1000h
MVI A 50h //Init values in MLocs
MOV M A LXI H 1000h
INX H MVI A 50h
MVI A 05h MOV M A
MOV M A
MOV A M INX H
MOV C A MVI A 05h
DCX H
MOV A M MOV M A
STA 1001h
MOV A C LXI H 2000h
STA 1000h
RST 1 MVI A 20h
MOV M A
Solution 2:
1. Read 1000H and 1001H in HL Pair INX H
2. Interchange HL pair data MVI A 02h
3. Store the data back
MOV M A
LXI H 1000h
MVI A 50h
MOV M A
LHLD 2000h
INX H XCHG
MVI A 05h LHLD 1000h
MOV M A
SHLD 2000h
LHLD 1000h XCHG
MOV A L SHLD 1000h
MOV L H
MOV H A RST 1
SHLD 1000h
RST 1
Arithmetic Instructions
Addition (with/without carry), Subtraction (with/without Borrow) (AFAC)
A=A±S (addition or subtraction without carry/borrow), where S=R8/M8
A=A±S±CY (addition or subtraction with carry/borrow), where S=R8/M8
ADD S, ADC S, ADI data8, ACI data8
SUB S, SBB S, SUI data8, SBI data8
Double addition (16 bit addition): DAD RP (HL=HL+RP) Only CY is changed
Increment (8/16 bit), decrement (8/16 bit)
S=S±1, where S=R8/M8
INR S, DCR S (AFAC except CY)
INX RP, DCX RP [NFAC]
Decimal adjust after addition (only 8 bits): DAA (AFAC)
Comparison (only 8 bits): CMP S, CPI data8
Logical Instructions
For logical operations like AND, OR, XOR: CY=0 and ZF, PF, SF will vary according
to result
AND OPERATION (AC=1)
ANA S (A=A.S)
ANI data8 (A=A.data8)
OR OPERATION (AC=0)
ORA S
ORI data8
XOR OPERATION (AC=0)
XRA S
XRI data8
Other Logical Operations
CMA, CMC, STC
RLC, RRC, (Rotate left/right accumulator without carry)
RAL, RAR (Rotate left/right accumulator with carry)
Stack Instructions FFFB
Stack is a memory area of 8085 memory model where data is arranged in FFFC
the form of Stack data structure for frequent access.
Only one entry/exit point FFFD CFH TOS
LIFO FFFE 84H TOS+1
TOS: Top of the stack
FFFF 55H TOS+2
STACK POINTER (SP) Holds the address of the TOP of the Stack (TOS)
Instructions:
PUSH RP (SP=SP-1, RPH->[SP], SP=SP-1, RPL->[SP])
FFFD
POP RP (RPL<-[SP], SP=SP+1, RPH=[SP+1], SP=SP+1)
SPHL (SP<- HL) SP
XTHL (Exchange TOS and TOS+1 data with HL Pair)
LXI SP, data16 (SP<- data16)
INX SP (SP=SP+1)
DCX SP (SP=SP-1)
DAD SP (HL=HL+SP)
Branching Instructions
Also known as Decision codes
Updates PC with new address
Alters the sequential execution pattern and transfers program control to another
address
Branching can be Conditional or Unconditional
Instructions:
JMP addr16
JZ addr16, JNZ addr16
JC addr16, JNC addr16
JPE addr16, JPO addr16
JM addr16, JP addr16
CALL addr16
RET
RSTn
PCHL
Machine control Instructions
MVI C, 05h
MVI B, 00H
MVI A, 00H
VERTADD: ADD M
JNC SKIPCARRYACCUM
INR B
SKIPCARRYACCUM: INX H
DCR C
JNZ VERTADD
STA 7000H
MOV A, B
STA 7001H
RST1/HLT