Reliable SR latches design using local Q0 ¼ S þ R
Q ð1Þ

redundancy QN 0 ¼ R þ S
QN ð2Þ
0 0
S.H. Lin and H.Z. Yang where Q and QN can be seen as the next states of the present states Q
and QN, respectively. Q0 can be implemented in negative logic as an
By using local redundancy, two improved soft-error-tolerant SR AND-OR structure where R and QN are in one OR branch, S̄ is in
latches are proposed. Experimental results show that the new latches another OR branch. Again, using positive logic, Q0 can be constructed
have superior delay performance compared to the traditional ones and by AND-OR topology where S̄ and QN are in one OR branch, R is in
can recover from the soft errors caused by cosmic rays and particle another OR branch. As a result, symmetrical pull-down and pull-up
strikes.
transistor networks can be obtained according to (1) and (2) [4].

Introduction: Soft errors are caused by alpha particles emitted by

packaging materials, and cosmic rays from deep space. As CMOS
technology advances into nanometre regime, the low energy particles p2 p5 p8 p11
p1 p4 p10
that used to have little impact on circuit performance are now S p7 R
p3 S p6 R p9 S p12
detrimental to total circuit performance because of smaller node R S R
Q QN QB QBN
capacitances, increased clock frequency, and lower supply voltage [1].
SR latches are basic sequential elements that can be used in S
n3 S n6 n4 n9 n12
asynchronous design. Though in today’s integrated circuits the preferred n1 S S
R R n7 R n10
strategy is still the synchronous design methodology and most commer- n2 n5 R n8 n11
cial design tools support synchronous design better than asynchronous
design, the asynchronous circuit is one of the best ways to overcome the
high power barrier of today’s integrated circuits. In addition, SR latches
are useful circuits that form the basis of the memory circuits. S S R R
Traditionally, soft errors occurring in memory can be corrected by a
error correction code (ECC) techniques, and many radiation harden
VDD
techniques for memory and latches have been proposed [2, 3]. However,
associated power and performance overheads are the greatest barriers to
p2 p5 p8 p11
adoption of classical fault tolerance techniques for soft error protection, S
p1 p4 R p10 R
R R S p7
e.g. in [3] the authors proposed a dual-port gate (DPG) technique to p3 p6 p9 p12
S S
mitigate both SEU and SET, however, this technique would require a Q QN QB QBN
process that supports isolated body contacts.
In this Letter we propose two novel soft-error-tolerant SR latches by n3
S R
n6 n4 n9 S n12
using local redundancy. Furthermore, to overcome the asymmetrical n1 S n7 R
R n10 S
rising and falling delay times, improvements are introduced in these n2 n5 n8 n11
R
new SR latches. Implemented in a standard 0.18 mm CMOS technology,
the proposed circuits show great improvement compared to traditional
ones.
S S R R
b

Fig. 2 New soft-error-tolerant SR latch

Proposed new SR latches: Fig. 1 shows the traditional CMOS NOR-
a NOR-based
based SR latch and the NAND-based SR latch, along with their b NAND-based
characteristic tables. Take the NOR-based SR latch for example.
When both S and R are 0, the latch is in a quiescent state and both
2.0
outputs retain their initial values. If a positive pulse (or 1) is generated
at the S input, the QN output will be forced into the 0 state. Then the 1.5 (V): t(s)
Q output is forced into the 1 state after a gate delay time. Similarly, if v(s)
1.0
V

a positive pulse (or 1) is generated at the R input, the Q output goes to v(r)
0.5
0 and then after a gate delay time, QN goes to 1. The condition of both
S and R are 1 is not allowed because in this case both Q and QN are 0
forced to zero and the next state of the latch is unpredictable when 2.0
both of the inputs return to 0. Similar analysis can be applied to the 1.5 (V): t(s)
NAND-based SR latch and similar problems exist. v(q)_TRADITION
1.0
V

0.5 v(qn)_TRADITION
0
–0.5
2.0
S R 1.5 (V): t(s)
S R
1.0 v(q)_NEW
V

0.5 v(qn)_NEW
QN Q
Q QN 0
–0.5
a b
25n
Fig. 1 Traditional SR latches t, s
a NOR-based Fig. 3 Timing characteristics of traditional NOR-based SR latch and
b NAND-based
new one

To overcome the asymmetrical problem of the rising and falling delay The soft-error-tolerant characteristic is achieved using local redun-
of the SR latch and further provide the latch with the soft-error-tolerant dancy. Traditionally, there are only two gates in one SR latch. However,
characteristic, we construct the new SR latches as shown in Fig. 2. Take in this Letter we use four gates in one SR latch. The soft-error-tolerant
the NOR-based SR latch for example. We get characteristic can be provided by the additional two gates as shown in

ELECTRONICS LETTERS 18th January 2007 Vol. 43 No. 2

Figs. 3 and 4. Take the new NOR-based SR latch for example. It utilises to-rail swing inverters in the new SR latch consume a large part of the
four nodes, Q, QN, QB, QBN, to store bit values 0 or 1 as logic values energy. However, an important characteristic of the new SR latch is that
0101 or 1010. Here, Q and QN are also the outputs of the latch. it is soft-error-tolerant whereas when stricken by particles the traditional
Suppose S ¼ 0, R ¼ 0, the initial pattern of Q, QN, QB and QBN is SR latch cannot recover from errors.
0101. Owing to the reason of particle striking, the pattern becomes Fig. 4 shows comparison of the transient recovery time of the
1101. Then the logic values at nodes Q, QN, QB and QNB will recover traditional SR NOR-based latch and the new SR latch. Transient
to 0101 pattern as illustrated below. Since S ¼ 0 and R ¼ 0, p1 and n1 recovery time is defined as the duration of the glitch at output Q
are off, p3 and n3 are on. QBN is 1 and therefore p2 is off. As a result, measured at 200 mV from the corresponding supply rail [5]. The
the erroneous value at Q cannot retain at value 1. Since QN is 1, n2 is particle strikes are modelled as a current source at the Q output with
on. Therefore, the charge at node Q will be discharged through path n2, the amplitude:
n3. Finally the Q, QN, QB and QBN pattern recovers to 0101 state.     
t t
Similar analysis can be applied to the NAND-based new SR latch. I ðtÞ ¼ Ipeak exp   exp  ð3Þ
ta tb
700
where Ipeak ¼ Qin=(ta  tb) and Qin is the charge collected as a result of
particle strikes, ta is the collection time-constant, and tb is the ion-track
600 establishment time-constant. ta and tb are the constants that depend
only on process-related factors. In this Letter, we use ta ¼ 1 ps, and
tb ¼ 40 ps. We can see that even with a very large Ipeak the new SR latch
500 can still recover to its initial state. However, for the traditional SR latch,
an error occurs when the collected peak current Ipeak is larger than a
recovery time, ps

400 certain value (or exceeds the light grey region in Fig. 4) and the latch
cannot recover to its initial state. Similar analysis can be applied to the
NAND-based SR latch.
300

200 Conclusion: We propose two soft-error-tolerant SR latches using

local redundancy. Experimental results show that the new latches
have superior delay performance compared to the original ones and
100 can recover from the soft errors caused by cosmic rays and particle
traditional latch
new latch
strikes at a penalty of power and area. Since the SR latch is a basic
0 element in asynchronous circuit design, the new proposed SR latch
0 1 2 3 4 5 6 should be a prospective candidate for reliable circuit design.
collected peak current, A (×10–3)

Fig. 4 Transient recovery times of traditional NOR-based SR latch and # The Institution of Engineering and Technology 2007
new latch 25 October 2006
Electronics Letters online no: 20073262
doi: 10.1049/el:20073262
Results: The new soft-error-tolerant SR latches are implemented in a
S.H. Lin and H.Z. Yang (Department of Electronic Engineering,
0.18 mm CMOS technology and optimised using HSPICE. We take
Tsinghua University, Beijing, People’s Republic of China)
the NOR-based SR latch for example. The transistor width of all eight
transistors can be adjusted and optimised using an HSPICE optimiser. E-mail: [email protected]
The transistor width of the keeper transistors in the new SR latch such
as p2, p3, p5, p6, n2, n3, n5, n6, etc., are chosen the minimum width.
The other transistors including those in the inverters can be optimised. References
All the transistors are chosen the minimum length. Fig. 3 shows the 1 Dhillon, Y.S., et al.: ‘Analysis and optimization of nanometer CMOS
typical output waveforms of two NOR-based SR latches when S ¼ 0 circuits for soft-error tolerance’, IEEE Trans. Very Large Scale Integr.
and R transits from 0 to 1 after optimisation. (VLSI) Syst., 2006, 14, (5), pp. 514–524
From Fig. 3 we can see clearly that the new SR latch has smaller 2 Ziegler, J., et al.: ‘IBM experiments in soft fails in computer electronics
delay than the traditional SR latch. The R-Q falling time of the (1978–1994)’, IBM J. Res. Dev., 1996, 40, (1), pp. 3–18
3 Zhang, M., et al.: ‘A CMOS design style for logic circuit hardening’.
traditional one is 37.802 ps and the R-QN rising time of the traditional
Proc. IEEE Int. Reliability Physics Symp., 2005, pp. 223–229
one is 79.39 ps. The average power is 1.909 mW. The R-Q falling time 4 Nikolic, B., et al.: ‘Improved sense amplifier-based flip-flop. Design and
and the R-QN rising time of the new one are the same, i.e. 37.75 ps. The measurements’, IEEE J. Solid-State Circuits, 2000, 35, (6), pp. 876–884
average power is 8.63 mW. Therefore, we can say that the new SR latch 5 Hzaucha, P., et al.: ‘Measurements and analysis of SER-tolerant latch in a
obtains a superior timing characteristic at a penalty of power. This is 90-nm dual-Vt CMOS process’, IEEE J. Solid-State Circuits, 2004, 39,
because more transistors are used in the new SR latch and the two rail- (9), pp. 1536–1543

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