Compal LA-5412P LA-5413P
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Hh woo't hoofCompal LA-5412P LA-5413P
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ZZZ1 PJP1
LA-5413P 45@ DCIN
ATIDA@
1 1
Compal Confidential
2 2
NBLB2 Schematics Document
Intel Clarksfield Processor with DDRIII + Ibex PM55
2009-11-17
REV:0.2
3 3
4 4
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5413P Schematic
Date: Thursday, November 19, 2009 Sheet 1 of 61
A B C D E
A B C D E
Compal Confidential
Clock Gen.
Model Name : NBLB2 SLG8SP587
9LRS3199AKLFT
File Name : LA-5413P(Madison) page23
1 1
LVDS Conn.
page 22 VRAM 64M*16
DDR3*8 Intel Mobile Clarkfield
DDR3-SO-DIMM X2
page 18,19 PCI-Express Dual Channel BANK 0, 1, 2, 3 page 11,12
ATI Madison uPGA989 DDR3-1066/1333(1.5V)
page5~10
Switch
Switch CRT
page 21
FDI*8 DMI*4
2
HDMI Switch 2
Level shift
page 20
USB conn x4 Bluetooth CMOS Camera Finger Print
page 42
Conn page 41 page 47
Conn page 47
3.3V 48MHz USB
Intel Ibex Peak-M
PCI-Express
3.3V 24.576MHz/48Mhz
FCBGA 1071 HD Audio
PM55/HM55 S-ATA
Card Reader
page24~32 RTS5159
port 0 port 1 page 34
New Card MINI Card x2 LAN(GbE) MDC 1.5 HDA Codec
Socket WLAN, Conn
page 47
ALC272
page 44
TV-Tuner AR8131 3 in 1
page 38 S-ATA HDD S-ATA ODD
3
page 37 page 35
LPC BUS Conn.page 33 Conn. page 33 socket 3
page 34
Audio AMP
RJ45 page 45
RTC CKT. page 36
page 43 EC
Conductive/B ENE KB926D3
Power USB/B page39 HP/MIC
Power On/Off CKT. EXT Jack
page 40
page 42 page 45
USB I/O Conn. Int.KBD
DC/DC Interface CKT. CIR Touch Pad page40
page41
page 48
LID SW BIOS
4 4
page41
Power Circuit DC/DC Debug port
page 42
page 48,49,50,52
53,54,55,56
TPM Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2009/02/04 Deciphered Date 2010/09/14 Title
CHARGER LED MB Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 51 page 47 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 2 of 61
A B C D E
A B C D E
DDR3 Voltage Rails
1 1
EC SM Bus1 address EC SM Bus2 address
+5VS Device Address Device Address
power
plane +3VS Smart Battery 0001 011X b EMCI 1402 100_1100X b
+1.5VS EEPROM(24C16/02) 1010 000X b NVIDIA N10P-GE1
+5VALW +CPU_CORE
+B +1.5V +VGA_CORE
+5VALW
+3VALW +1.8VS
+0.75VS
Battery EEPROM
State +1.05VS
+1.1VS_VTT SMB1 +3VALW
+1.5VS_VRAM +3VS
EC VGA Thermal
VGA PCH for thermal
Sensor Mornitor
2 2
S0 SMB2 2B7002
O O O O
S1
O O O O
S3
+3VALW
O O O X +3VALW
S5 S4/AC DDR VREF WLAN1 New Card CLK_GEN
O O X X
S5 S4/ Battery only
O X X X 2B7002
S5 S4/AC & Battery SMB
don't exist X X X X
DDR VREF WLAN2 DIMMI1 DIMMI2
PCH
+3VALW
GPIO PIN Define
3 3
SML0
ID3 ID2 ID1 ID0
NBLB2(1100 ) R358 R361 R766 R765
For system
Reserve (1101 ) X X X X +3VALW +3VS thermal mornitor
Reserve (1110 ) X X X X
Reserve (1111 ) X X X X EC_SMB1
NBLB1 (0000 ) R353 R350 R766 R765
Reserve( 0001 ) X X X X SML1 2B7002
Reserve( 0010 ) X X X X
Reserve( 0011 ) X X X X
Reserve( 0100 ) X X X X
Reserve( 0101 ) X X X X
Reserve (0110 ) X X X X
Reserve (0111 ) X X X X
4 4
Reserve (1000 ) X X X X
Reserve (1001 ) X X X X
Reserve (1010 ) X X X X
Reserve (1011 ) X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
MB Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 3 of 61
A B C D E
A B C D E
VGA (Madison)
+3VS_DELAY
power +1.8VS
plane +VGA_CORE
State +1.5VS_VRAM
+1.1VS
S0
1
O O 1
S1
O O
S3
S5 S4/AC
X X
S5 S4/ Battery only
X X
S5 S4/AC & Battery
X X
don't exist X X
Ref:46039_m97_ds_nda_1.00
M97 sequence
M97 has the following requirements with regards to power supply sequencing to avoid damaging the ASIC.
‧ All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.
‧ VDDC should ramp before or simultaneously with VDDCI.
‧ VDDCI should ramp before VDDR1.
‧ VDDC should ramp before VDDR4.
2 2
‧ VDDC should ramp before DPx_VDD18, DPx_VDD10, and DPx_PVDD.
‧ PWRGOOD must not be asserted, and must not exceed 300 mV, before all of VDDC, VDD_CT, and VDDR3 have
ramped up. Asserting PWRGOOD only after all ASIC supplies have ramped up is preferred for forward
compatibility.
‧ PWRGOOD must be de-asserted, and must be brought below 300 mV, before ramping down any of VDDC,
VDD_CT, or VDDR3.
‧ DDC3DATA_DP3_AUXN, DDC4DATA_DP4_AUXN, DDC3CLK_DP3_AUXP, and DDC4CLK_DP4_AUXP
must be pulled high either before or after both VDDC and VDD_CT have ramped up.
‧ For power down, reversing the ramp-up sequence is recommended.
POWER UP/DOWN Sequence
t0>=0
3 3
(VDDC) +VGA_CORE
+VDDCI
(DPX_PDD10) +1.0VS
(VDDR1) +1.5VS_VRAM
(VDD_CT,DPX_PVDD,DPX_VDD18) +1.8VS
(VDDR3) +3VS_DELAY
<=20ms <=20ms
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/24 Deciphered Date 2010/02/24 Title
VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 4 of 61
A B C D E
5 4 3 2 1
JCPU1E
JCPU1A R151 AJ13
PEG_IRCOMP RSVD32
PEG_ICOMPI B26 1 2 49.9_0402_1% RSVD33 AJ12
PEG_ICOMPO A26
DMI_PTX_HRX_N0 A24 B27 R152 AP25
DMI_PTX_HRX_N1 C23 DMI_RX#[0] PEG_RCOMPO EXP_RBIAS RSVD1
DMI_RX#[1] PEG_RBIAS A25 1 2 750_0402_1% AL25 RSVD2 RSVD34 AH25
DMI_PTX_HRX_N2 B22 AL24 AK26
DMI_PTX_HRX_N3 A21 DMI_RX#[2] PCIE_GTX_C_MRX_N15 RSVD3 RSVD35
DMI_RX#[3] PEG_RX#[0] K35 AL22 RSVD4
J34 PCIE_GTX_C_MRX_N14 AJ33 AL26
DMI_PTX_HRX_P0 PEG_RX#[1] PCIE_GTX_C_MRX_N13 RSVD5 RSVD36
B24 DMI_RX[0] PEG_RX#[2] J33 AG9 RSVD6 RSVD_NCTF_37 AR2
DMI_PTX_HRX_P1 D23 G35 PCIE_GTX_C_MRX_N12 M27
DMI_RX[1] PEG_RX#[3] RSVD7
DMI
DMI_PTX_HRX_P2 B23 G32 PCIE_GTX_C_MRX_N11 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] PCIE_GTX_C_MRX_N10 RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 11 H_DIMMA_REF J17 RSVD9 (SA_DIMM_VREF) RSVD39 AJ27 D
F31 PCIE_GTX_C_MRX_N9 H17
DMI_HTX_PRX_N0 D24 PEG_RX#[6] PCIE_GTX_C_MRX_N8
12 H_DIMMB_REF RSVD10(SB_DIMM_VREF)
DMI_TX#[0] PEG_RX#[7] D35 G25 RSVD11
DMI_HTX_PRX_N1 G24 E33 PCIE_GTX_C_MRX_N7 G17
DMI_HTX_PRX_N2 F23 DMI_TX#[1] PEG_RX#[8] PCIE_GTX_C_MRX_N6 RSVD12
DMI_TX#[2] PEG_RX#[9] C33 E31 RSVD13 RSVD_NCTF_40 AP1
DMI_HTX_PRX_N3 H23 D32 PCIE_GTX_C_MRX_N5 E30 AT2
DMI_TX#[3] PEG_RX#[10] PCIE_GTX_C_MRX_N4 RSVD14 RSVD_NCTF_41
PEG_RX#[11] B32
DMI_HTX_PRX_P0 D25 C31 PCIE_GTX_C_MRX_N3 AT3
DMI_HTX_PRX_P1 F24 DMI_TX[0] PEG_RX#[12] PCIE_GTX_C_MRX_N2 RSVD_NCTF_42
DMI_TX[1] PEG_RX#[13] B28 RSVD_NCTF_43 AR1
DMI_HTX_PRX_P2 E23 B30 PCIE_GTX_C_MRX_N1
DMI_HTX_PRX_P3 G23 DMI_TX[2] PEG_RX#[14] PCIE_GTX_C_MRX_N0
DMI_TX[3] PEG_RX#[15] A31
J35 PCIE_GTX_C_MRX_P15 R153 AL28
PEG_RX[0] PCIE_GTX_C_MRX_P14 3.01K_0402_1% RSVD45
PEG_RX[1] H34 1 @ 2 CFG0 AM30 CFG[0] RSVD46 AL29
H33 PCIE_GTX_C_MRX_P13 CFG1 AM28 AP30
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_C_MRX_P12 R154 CFG2 CFG[1] RSVD47
E22 FDI_TX#[0] PEG_RX[3] F35 AP31 CFG[2] RSVD48 AP32
FDI_CTX_PRX_N1 D21 G33 PCIE_GTX_C_MRX_P11 3.01K_0402_1% 1 2 CFG3 AL32 AL27
FDI_CTX_PRX_N2 FDI_TX#[1] PEG_RX[4] PCIE_GTX_C_MRX_P10 CFG[3] RSVD49
D19 FDI_TX#[2] PEG_RX[5] E34 1 @ 2 CFG4 AL30 CFG[4] RSVD50 AT31
FDI_CTX_PRX_N3 D18 F32 PCIE_GTX_C_MRX_P9 3.01K_0402_1% R155 CFG5 AM31 AT32
FDI_CTX_PRX_N4 FDI_TX#[3] PEG_RX[6] PCIE_GTX_C_MRX_P8 CFG6 CFG[5] RSVD51
G21 FDI_TX#[4] PEG_RX[7] D34 AN29 CFG[6] RSVD52 AP33
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
E19
F21
FDI_TX#[5]
FDI_TX#[6]
PCI EXPRESS -- GRAPHICS PEG_RX[8]
PEG_RX[9]
F33
B33
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P6
R156
3.01K_0402_1%
1 @ 2 CFG7
CFG8
AM32
AK32
CFG[7]
CFG[8]
RSVD53
RSVD_NCTF_54
AR33
AT33
Intel(R) FDI
FDI_CTX_PRX_N7 G18 D31 PCIE_GTX_C_MRX_P5 CFG9 AK31 AT34
RESERVED
FDI_TX#[7] PEG_RX[10] PCIE_GTX_C_MRX_P4 CFG10 CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 AK28 CFG[10] RSVD_NCTF_56 AP35
PEG_RX[12] C30 PCIE_GTX_C_MRX_P3 WW41 Recommend not pull down CFG11 AJ28 CFG[11] RSVD_NCTF_57 AR35
FDI_CTX_PRX_P0 D22 A28 PCIE_GTX_C_MRX_P2 PCIE2.0 Jitter is over on ES1 CFG12 AN30 AR32
FDI_CTX_PRX_P1 FDI_TX[0] PEG_RX[13] PCIE_GTX_C_MRX_P1 CFG13 CFG[12] RSVD58
C21 FDI_TX[1] PEG_RX[14] B29 AN32 CFG[13]
FDI_CTX_PRX_P2 D20 A30 PCIE_GTX_C_MRX_P0 CFG14 AJ32
FDI_CTX_PRX_P3 FDI_TX[2] PEG_RX[15] CFG15 CFG[14]
C18 FDI_TX[3] AJ29 CFG[15] RSVD_TP_59 E15
C FDI_CTX_PRX_P4 G22 L33 PEG_HTX_GRX_N15 C316 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15 CFG16 AJ30 F15 C
FDI_CTX_PRX_P5 FDI_TX[4] PEG_TX#[0] PEG_HTX_GRX_N14 C315 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14 CFG17 CFG[16] RSVD_TP_60
E20 FDI_TX[5] PEG_TX#[1] M35 1 2 AK30 CFG[17] KEY A2
FDI_CTX_PRX_P6 F20 M33 PEG_HTX_GRX_N13 C314 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13 CFG18 H16 D15 R157
FDI_CTX_PRX_P7 FDI_TX[6] PEG_TX#[2] PEG_HTX_GRX_N12 C313 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12 RSVD_TP_86 RSVD62 0_0402_5%
G19 FDI_TX[7] PEG_TX#[3] M30 1 2 RSVD63 C15
L31 PEG_HTX_GRX_N11 C312 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11 AJ15 RSVD64_R 2 @ 1
FDI_FSYNC0 PEG_TX#[4] PEG_HTX_GRX_N10 C311 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10 RSVD64 RSVD65_R 2 @
F17 FDI_FSYNC[0] PEG_TX#[5] K32 1 2 RSVD65 AH15 1
FDI_FSYNC1 E17 M29 PEG_HTX_GRX_N9 C310 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9 R158
FDI_FSYNC[1] PEG_TX#[6] PEG_HTX_GRX_N8 C309 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8 0_0402_5%
PEG_TX#[7] J31 1 2 B19 RSVD15
FDI_INT C17 K29 PEG_HTX_GRX_N7 C308 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7 R160 A19
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 C307 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 0_0402_5% RSVD16
PEG_TX#[9] H30 1 2
FDI_LSYNC0 F18 H29 PEG_HTX_GRX_N5 C306 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5 1 @ 2 H_RSVD17_R A20
FDI_LSYNC1 FDI_LSYNC[0] PEG_TX#[10] PEG_HTX_GRX_N4 C305 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4 @ H_RSVD18_R RSVD17
D17 FDI_LSYNC[1] PEG_TX#[11] F29 1 2 1 2 B20 RSVD18
E28 PEG_HTX_GRX_N3 C304 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3 AA5
PEG_TX#[12] PEG_HTX_GRX_N2 C303 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2 R159 RSVD_TP_66
PEG_TX#[13] D29 1 2 U9 RSVD19 RSVD_TP_67 AA4
D27 PEG_HTX_GRX_N1 C302 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1 0_0402_5% T9 R8
PEG_TX#[14] PEG_HTX_GRX_N0 C301 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 RSVD20 RSVD_TP_68
PEG_TX#[15] C26 1 2 RSVD_TP_69 AD3
AC9 RSVD21 RSVD_TP_70 AD2
L34 PEG_HTX_GRX_P15 C332 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15 AB9 AA2
PEG_TX[0] PEG_HTX_GRX_P14 C331 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14 RSVD22 RSVD_TP_71
PEG_TX[1] M34 1 2 RSVD_TP_72 AA1
M32 PEG_HTX_GRX_P13 C330 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13 R9
PEG_TX[2] DMI_PTX_HRX_N[0..3] 26 RSVD_TP_73
L30 PEG_HTX_GRX_P12 C329 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 AG7
PEG_TX[3] DMI_PTX_HRX_P[0..3] 26 RSVD_TP_74
M31 PEG_HTX_GRX_P11 C328 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11 C1 AE3
PEG_TX[4] PEG_HTX_GRX_P10 C327 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10 RSVD_NCTF_23 RSVD_TP_75
PEG_TX[5] K31 1 2 DMI_HTX_PRX_N[0..3] 26 A3 RSVD_NCTF_24
M28 PEG_HTX_GRX_P9 C326 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PEG_TX[6] DMI_HTX_PRX_P[0..3] 26
H31 PEG_HTX_GRX_P8 C325 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8 V4
PEG_TX[7] PEG_HTX_GRX_P7 C324 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7 RSVD_TP_76
PEG_TX[8] K28 1 2 RSVD_TP_77 V5
G30 PEG_HTX_GRX_P6 C323 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6 N2
PEG_TX[9] PEG_HTX_GRX_P5 C322 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5 RSVD_TP_78
PEG_TX[10] G29 1 2 J29 RSVD26 RSVD_TP_79 AD5
F28 PEG_HTX_GRX_P4 C321 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4 J28 AD7
B PEG_TX[11] PEG_HTX_GRX_P3 C320 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3 RSVD27 RSVD_TP_80 B
PEG_TX[12] E27 1 2 PCIE_GTX_C_MRX_N[0..15] 13 RSVD_TP_81 W3
D28 PEG_HTX_GRX_P2 C319 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 A34 W2
PEG_TX[13] PCIE_GTX_C_MRX_P[0..15] 13 RSVD_NCTF_28 RSVD_TP_82
C27 PEG_HTX_GRX_P1 C318 1 2 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1 A33 N3
PEG_TX[14] PEG_HTX_GRX_P0 C317 DIS@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0 RSVD_NCTF_29 RSVD_TP_83
PEG_TX[15] C25 1 2 PCIE_MTX_C_GRX_N[0..15] 13 RSVD_TP_84 AE5
PCIE_MTX_C_GRX_P[0..15] 13 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
B35 RSVD_NCTF_31
IC,AUB_CFD_rPGA,R0P9 AP34
CONN@ VSS
IC,AUB_CFD_rPGA,R0P9
08/20 ADD CONN@
FDI for SG
FDI_CTX_PRX_N[0..7] 26 CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence
FDI_CTX_PRX_P[0..7] 26
*1:Single PEG *1:Disabled; No Physical Display Port
FDI_FSYNC0 0:Bifurcation enabled attached to Embedded Display Port
FDI_LSYNC0 26
FDI_FSYNC1 0:Enabled; An external Display Port
FDI_LSYNC1 26
FDI_INT
device is connected to the Embedded
FDI_INT 26 Display Port
FDI_LSYNC0
FDI_FSYNC0 26 CFG3 - PCI-Express Static Lane Reversal
FDI_LSYNC1
FDI_FSYNC1 26
*:Default
A
*1 :Normal Operation A
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
PROCESSOR (1/6) DMI,FDI,PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 5 of 61
5 4 3 2 1
5 4 3 2 1
JCPU1B
H_COMP3 AT23 Leakage Issue
COMP3 CLK_CPU_BCLK_R R163 1
BCLK A16 2 0_0402_5% CLK_CPU_BCLK 29 +3VS
MISC
H_COMP2 AT24 B16 CLK_CPU_BCLK#_R R164 1 2 0_0402_5%
COMP2 BCLK# CLK_CPU_BCLK# 29
H_COMP1 CLK_CPU_XDP
CLOCKS
G16 COMP1 BCLK_ITP AR30
AT30 CLK_CPU_XDP# XDP_DBRESET# R165 1 2
H_COMP0 BCLK_ITP# 1K_0402_5%
AT26 COMP0
E16 CLK_CPU_DMI_R R166 1 2 0_0402_5%
PEG_CLK CLK_CPU_DMI 25
D16 CLK_CPU_DMI#_R R167 1 2 0_0402_5%
PEG_CLK# CLK_CPU_DMI# 25
@ SKTOCC#_R AH24
T11 PAD SKTOCC#
A18 CLK_CPU_DP_R R286 1 UMA@ 2 0_0402_5%
DPLL_REF_SSCLK CLK_CPU_DP 25 +1.1VS_VTT
D A17 CLK_CPU_DP#_R R307 1 2 0_0402_5% 2/28 Follow Module design Rev1.0 D
DPLL_REF_SSCLK# CLK_CPU_DP# 25
H_CATERR# AK14 UMA@
CATERR#
THERMAL
R309 1 DISO@ 2 0_0402_5% New add for SG Board
R308 1 2 0_0402_5% XDP_PRDY# R168 @ 51_0402_1%
F6 DISO@ 0826 XDP_TMS R169 @ 51_0402_1%
SM_DRAMRST# SM_DRAMRST# 11,12
R170 1 2 H_PECI_R AT15 XDP_TDI_R R171 @ 51_0402_1%
29 H_PECI 0_0402_5% PECI SM_RCOMP_0 XDP_PREQ# R172 @ 51_0402_1%
SM_RCOMP[0] AL1
AM1 SM_RCOMP_1 +1.1VS_VTT XDP_TDO R173 51_0402_1%
SM_RCOMP[1] SM_RCOMP_2
SM_RCOMP[2] AN1
H_PROCHOT# AN26 R174 1 2 10K_0402_5%
57 H_PROCHOT# PROCHOT# PM_EXTTS#0 R175 1
AN15 2 10K_0402_5%
DDR3
MISC
PM_EXT_TS#[0] PM_EXTTS#1_R R176 1
PM_EXT_TS#[1] AP15 2 0_0402_5% PM_EXTTS#0_1 11,12
XDP_TCLK R177 @ 51_0402_1%
R178 1 2 H_THERMTRIP#_R AK15
29 H_THERMTRIP# THERMTRIP#
0_0402_5%
XDP_TRST# R179 51_0402_1%
AT28 XDP_PRDY#
PRDY# XDP_PREQ#
PREQ# AP27
AN28 XDP_TCLK
H_CPURST# TCK XDP_TMS
AP26 RESET_OBS# TMS AP28
PWR MANAGEMENT
AT27 XDP_TRST#
TRST# XDP_TDI_R R180 1 2 0_0402_5% XDP_TDI
JTAG & BPM
R181 1 2 H_PM_SYNC_R AL15 AT29 XDP_TDI_R XDP_TDO_M R182 1 @ 2 0_0402_5% XDP_TDO
26 H_PM_SYNC 0_0402_5% PM_SYNC TDI XDP_TDO_R
TDO AR27
1
AR29 XDP_TDI_M
R183 1 H_CPUPWRGD_1 TDI_M XDP_TDO_M R184
2 AN14 VCCPWRGOOD_1 TDO_M AP29
0_0402_5% 0_0402_5%
AN25 XDP_DBR#_R R185 1 2 0_0402_5% XDP_DBRESET#
DBR# XDP_DBRESET# 26
C R186 1 2 H_CPUPWRGD_0 AN27 C
29 H_CPUPWRGD
2
0_0402_5% VCCPWRGOOD_0 XDP_TDI_M 1 @ 2
AJ22 XDP_OBS0_R R188 1 2 0_0402_5% XDP_OBS0 XDP_TDO_R R187 1 2 0_0402_5%
R190 1 PM_DRAM_PWRGD_R BPM#[0] XDP_OBS1_R R191 0_0402_5% XDP_OBS1 R189 0_0402_5%
26 PM_DRAM_PWRGD 2 AK13 SM_DRAMPWROK BPM#[1] AK22 1 2
0_0402_5% AK24 XDP_OBS2_R R192 1 2 0_0402_5% XDP_OBS2
BPM#[2] XDP_OBS3_R R193 0_0402_5% XDP_OBS3
BPM#[3] AJ24 1 2
AM15 AJ25 XDP_OBS4_R R194 1 2 0_0402_5% XDP_OBS4
54 H_VTTPWRGD VTTPWRGOOD BPM#[4]
BPM#[5] AH22 XDP_OBS5_R R195 1 2 0_0402_5% XDP_OBS5 JTAG MAPPING
AK23 XDP_OBS6_R R196 1 2 0_0402_5% XDP_OBS6
H_PWRGD_XDP BPM#[6]
1 R197 2 H_PWRGD_XDP_R AM26 TAPPWRGOOD BPM#[7] AH23 XDP_OBS7_R R198 1 2 0_0402_5% XDP_OBS7
0_0402_5% Scan Chain STUFF -> R653, R657, R662
(Default) NO STUFF -> R655, R660
R199 PLT_RST#_R AL14 3/3 Add(Follow KBLA0)
28,35,37,47 PLT_RST_BUF# RSTIN#
1.5K_0402_1%
CPU Only STUFF -> R653, R655
1
NO STUFF -> R657, R660, R662
IC,AUB_CFD_rPGA,R0P9
R200 CONN@
750_0402_1% GMCH Only STUFF -> R660, R662
NO STUFF -> R653, R655, R657
2
4/17 Modify R199 to 1.5K ohm, R200 to 750 ohm(see DG414044 p.8)
JP19
XDP Connector
C863 1 2
B PM_DRAM_PWRGD @ GND0 GND1 B
1 2 100P_0402_50V8J XDP_PREQ# 3 OBSFN_A0 OBSFN_C0 4
XDP_PRDY# 5 6
C864 OBSFN_A1 OBSFN_C1
7 GND2 GND3 8
H_PM_SYNC @ 1 2 100P_0402_50V8J XDP_OBS0 9 10
XDP_OBS1 OBSDATA_A0 OBSDATA_C0
11 OBSDATA_A1 OBSDATA_C1 12
+1.5V C865 13 14
H_VTTPWRGD @ GND4 GND5
1 2 100P_0402_50V8J XDP_OBS2 15 OBSDATA_A2 OBSDATA_C2 16
XDP_OBS3 17 18
OBSDATA_A3 OBSDATA_C3
19 GND6 GND7 20
21 OBSFN_B0 OBSFN_D0 22
R204 23 24
1.1K_0402_1%
4/2 Add by Vivian OBSFN_B1 OBSFN_D1 R207
25 GND8 GND9 26
XDP_OBS4 27 28 1K_0402_5%
+1.1VS_VTT XDP_OBS5 OBSDATA_B0 OBSDATA_D0 H_CPURST#
29 OBSDATA_B1 OBSDATA_D1 30 1 2
31 32 H_RESET#_R 1 @ 2 PLT_RST_BUF# PLT_RST_BUF# 28,35,37,47
PM_DRAM_PWRGD_R XDP_OBS6 GND10 GND11 R209
33 OBSDATA_B2 OBSDATA_D2 34
H_CATERR# R201 1 2 49.9_0402_1% R212 XDP_OBS7 35 36 0_0402_5%
H_PROCHOT# R202 1 OBSDATA_B3 OBSDATA_D3
2 68_0402_5% 1K_0402_5% 37 GND12 GND13 38
1
H_CPURST# R203 1 @ 2 68_0402_5% H_CPUPWRGD 1 2 H_PWRGOOD_R 39 40 CLK_CPU_XDP
R211 PWRGOOD/HOOK0 ITPCLK/HOOK4
26,39 PBTN_OUT# 1 2 PBTN_OUT#_XDP 41 HOOK1 ITPCLK#/HOOK5 42 CLK_CPU_XDP#
3K_0402_1% +1.1VS_VTT R213 0_0402_5% 43 44 +1.1VS_VTT
H_COMP0 R205 1 VCC_OBS_AB VCC_OBS_CD
2 49.9_0402_1% H_PWRGD_XDP 45 HOOK2 RESET#/HOOK6 46 H_RESET#_R
1 47 48 XDP_DBRESET#
2
H_COMP1 R206 1 49.9_0402_1% HOOK3 DBR#/HOOK7
2 49 GND14 GND15 50
H_COMP2 R208 1 2 20_0402_1% C333 51 52 XDP_TDO 1 2 R217 +1.1VS_VTT
H_COMP3 R210 1 20_0402_1% @ 11,12,23 D_CK_SDATA SDA TD0 XDP_TRST# 51_0402_5%
2 11,12,23 D_CK_SCLK 53 SCL TRST# 54
0.1U_0402_16V4Z 2 55 56 XDP_TDI
TCK1 TDI
Layout rule：：10mil width trace XDP_TCLK 57 TCK0 TMS 58 XDP_TMS
A length < 0.5", spacing 20mil 59 GND16 GND17 60 A
Intel Suggestion
DB CONN@ SAMTE_BSH-030-01-L-D-A
WW14_2009_Calpella_MoW SM_RCOMP_0 R214 1 100_0402_1%
2
Notice: V_SM should be available in S3 SM_RCOMP_1 R215 1 2 24.9_0402_1%
SM_RCOMP_2 R216 1 2 130_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
DDR3 Compensation Signals Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
Layout Note:Please these THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (2/6) CLK,JTAG
Size Document Number Rev
resistors near Processor AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 6 of 61
5 4 3 2 1
5 4 3 2 1
JCPU1D
12 DDR_B_D[0..63]
12 DDR_B_DM[0..7]
JCPU1C
11 DDR_A_D[0..63] 12 DDR_B_DQS#[0..7]
11 DDR_A_DM[0..7] 12 DDR_B_DQS[0..7]
11 DDR_A_DQS#[0..7] 12 DDR_B_MA[0..15]
11 DDR_A_DQS[0..7]
11 DDR_A_MA[0..15] SB_CK[0] W8 DDR_B_CLK0 12
SB_CK#[0] W9 DDR_B_CLK0# 12
AA6 DDR_B_D0 B5 M3
SA_CK[0] DDR_A_CLK0 11 SB_DQ[0] SB_CKE[0] DDR_B_CKE0 12
AA7 DDR_B_D1 A5
SA_CK#[0] DDR_A_CLK0# 11 SB_DQ[1]
P7 DDR_B_D2 C3
SA_CKE[0] DDR_A_CKE0 11 SB_DQ[2]
DDR_A_D0 A10 DDR_B_D3 B3 V7
SA_DQ[0] SB_DQ[3] SB_CK[1] DDR_B_CLK1 12
DDR_A_D1 C10 DDR_B_D4 E4 V6
SA_DQ[1] SB_DQ[4] SB_CK#[1] DDR_B_CLK1# 12
D DDR_A_D2 C7 DDR_B_D5 A6 M2 D
SA_DQ[2] SB_DQ[5] SB_CKE[1] DDR_B_CKE1 12
DDR_A_D3 A7 Y6 DDR_B_D6 A4
SA_DQ[3] SA_CK[1] DDR_A_CLK1 11 SB_DQ[6]
DDR_A_D4 B10 Y5 DDR_B_D7 C4
SA_DQ[4] SA_CK#[1] DDR_A_CLK1# 11 SB_DQ[7]
DDR_A_D5 D10 P6 DDR_B_D8 D1
SA_DQ[5] SA_CKE[1] DDR_A_CKE1 11 SB_DQ[8]
DDR_A_D6 E10 DDR_B_D9 D2
DDR_A_D7 SA_DQ[6] DDR_B_D10 SB_DQ[9]
A8 SA_DQ[7] F2 SB_DQ[10] SB_CS#[0] AB8 DDR_B_CS0# 12
DDR_A_D8 D8 DDR_B_D11 F1 AD6
SA_DQ[8] SB_DQ[11] SB_CS#[1] DDR_B_CS1# 12
DDR_A_D9 F10 AE2 DDR_B_D12 C2
SA_DQ[9] SA_CS#[0] DDR_A_CS0# 11 SB_DQ[12]
DDR_A_D10 E6 AE8 DDR_B_D13 F5
SA_DQ[10] SA_CS#[1] DDR_A_CS1# 11 SB_DQ[13]
DDR_A_D11 F7 DDR_B_D14 F3
DDR_A_D12 SA_DQ[11] DDR_B_D15 SB_DQ[14]
E9 SA_DQ[12] G4 SB_DQ[15] SB_ODT[0] AC7 DDR_B_ODT0 12
DDR_A_D13 B7 DDR_B_D16 H6 AD1
SA_DQ[13] SB_DQ[16] SB_ODT[1] DDR_B_ODT1 12
DDR_A_D14 E7 AD8 DDR_B_D17 G2
SA_DQ[14] SA_ODT[0] DDR_A_ODT0 11 SB_DQ[17]
DDR_A_D15 C6 AF9 DDR_B_D18 J6
SA_DQ[15] SA_ODT[1] DDR_A_ODT1 11 SB_DQ[18]
DDR_A_D16 H10 DDR_B_D19 J3
DDR_A_D17 SA_DQ[16] DDR_B_D20 SB_DQ[19]
G8 SA_DQ[17] G1 SB_DQ[20]
DDR_A_D18 K7 DDR_B_D21 G5 D4 DDR_B_DM0
DDR_A_D19 SA_DQ[18] DDR_B_D22 SB_DQ[21] SB_DM[0] DDR_B_DM1
J8 SA_DQ[19] J2 SB_DQ[22] SB_DM[1] E1
DDR_A_D20 G7 DDR_B_D23 J1 H3 DDR_B_DM2
DDR_A_D21 SA_DQ[20] DDR_B_D24 SB_DQ[23] SB_DM[2] DDR_B_DM3
G10 SA_DQ[21] J5 SB_DQ[24] SB_DM[3] K1
DDR_A_D22 J7 B9 DDR_A_DM0 DDR_B_D25 K2 AH1 DDR_B_DM4
DDR_A_D23 SA_DQ[22] SA_DM[0] DDR_A_DM1 DDR_B_D26 SB_DQ[25] SB_DM[4] DDR_B_DM5
J10 SA_DQ[23] SA_DM[1] D7 L3 SB_DQ[26] SB_DM[5] AL2
DDR_A_D24 L7 H7 DDR_A_DM2 DDR_B_D27 M1 AR4 DDR_B_DM6
DDR_A_D25 SA_DQ[24] SA_DM[2] DDR_A_DM3 DDR_B_D28 SB_DQ[27] SB_DM[6] DDR_B_DM7
M6 SA_DQ[25] SA_DM[3] M7 K5 SB_DQ[28] SB_DM[7] AT8
DDR_A_D26 M8 AG6 DDR_A_DM4 DDR_B_D29 K4
DDR_A_D27 SA_DQ[26] SA_DM[4] DDR_A_DM5 DDR_B_D30 SB_DQ[29]
L9 SA_DQ[27] SA_DM[5] AM7 M4 SB_DQ[30]
DDR_A_D28 L6 AN10 DDR_A_DM6 DDR_B_D31 N5
DDR_A_D29 SA_DQ[28] SA_DM[6] DDR_A_DM7 DDR_B_D32 SB_DQ[31]
K8 SA_DQ[29] SA_DM[7] AN13 AF3 SB_DQ[32]
DDR_A_D30 N8 DDR_B_D33 AG1
C DDR_A_D31 SA_DQ[30] DDR_B_D34 SB_DQ[33] DDR_B_DQS#0 C
P9 SA_DQ[31] AJ3 SB_DQ[34] SB_DQS#[0] D5
DDR_A_D32 AH5 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR_A_D33 SA_DQ[32] DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2
AF5 SA_DQ[33] AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D37 AG3 L4 DDR_B_DQS#3
DDR SYSTEM MEMORY A
DDR_A_D35 SA_DQ[34] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D38 SB_DQ[37] SB_DQS#[3] DDR_B_DQS#4
AK7 F8 AJ4 AH2
DDR SYSTEM MEMORY - B
DDR_A_D36 SA_DQ[35] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[4] DDR_B_DQS#5
AF6 SA_DQ[36] SA_DQS#[2] J9 AH4 SB_DQ[39] SB_DQS#[5] AL4
DDR_A_D37 AG5 N9 DDR_A_DQS#3 DDR_B_D40 AK3 AR5 DDR_B_DQS#6
DDR_A_D38 SA_DQ[37] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D41 SB_DQ[40] SB_DQS#[6] DDR_B_DQS#7
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AK4 SB_DQ[41] SB_DQS#[7] AR8
DDR_A_D39 AJ6 AK9 DDR_A_DQS#5 DDR_B_D42 AM6
DDR_A_D40 SA_DQ[39] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D43 SB_DQ[42]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AN2 SB_DQ[43]
DDR_A_D41 AJ9 AT13 DDR_A_DQS#7 DDR_B_D44 AK5
DDR_A_D42 SA_DQ[41] SA_DQS#[7] DDR_B_D45 SB_DQ[44]
AL10 SA_DQ[42] AK2 SB_DQ[45]
DDR_A_D43 AK12 DDR_B_D46 AM4
DDR_A_D44 SA_DQ[43] DDR_B_D47 SB_DQ[46]
AK8 SA_DQ[44] AM3 SB_DQ[47]
DDR_A_D45 AL7 DDR_B_D48 AP3 C5 DDR_B_DQS0
DDR_A_D46 SA_DQ[45] DDR_A_DQS0 DDR_B_D49 SB_DQ[48] SB_DQS[0] DDR_B_DQS1
AK11 SA_DQ[46] SA_DQS[0] C8 AN5 SB_DQ[49] SB_DQS[1] E3
DDR_A_D47 AL8 F9 DDR_A_DQS1 DDR_B_D50 AT4 H4 DDR_B_DQS2
DDR_A_D48 SA_DQ[47] SA_DQS[1] DDR_A_DQS2 DDR_B_D51 SB_DQ[50] SB_DQS[2] DDR_B_DQS3
AN8 SA_DQ[48] SA_DQS[2] H9 AN6 SB_DQ[51] SB_DQS[3] M5
DDR_A_D49 AM10 M9 DDR_A_DQS3 DDR_B_D52 AN4 AG2 DDR_B_DQS4
DDR_A_D50 SA_DQ[49] SA_DQS[3] DDR_A_DQS4 DDR_B_D53 SB_DQ[52] SB_DQS[4] DDR_B_DQS5
AR11 SA_DQ[50] SA_DQS[4] AH8 AN3 SB_DQ[53] SB_DQS[5] AL5
DDR_A_D51 AL11 AK10 DDR_A_DQS5 DDR_B_D54 AT5 AP5 DDR_B_DQS6
DDR_A_D52 SA_DQ[51] SA_DQS[5] DDR_A_DQS6 DDR_B_D55 SB_DQ[54] SB_DQS[6] DDR_B_DQS7
AM9 SA_DQ[52] SA_DQS[6] AN11 AT6 SB_DQ[55] SB_DQS[7] AR7
DDR_A_D53 AN9 AR13 DDR_A_DQS7 DDR_B_D56 AN7
DDR_A_D54 SA_DQ[53] SA_DQS[7] DDR_B_D57 SB_DQ[56]
AT11 SA_DQ[54] AP6 SB_DQ[57]
DDR_A_D55 AP12 DDR_B_D58 AP8
DDR_A_D56 SA_DQ[55] DDR_B_D59 SB_DQ[58]
AM12 SA_DQ[56] AT9 SB_DQ[59]
DDR_A_D57 AN12 DDR_B_D60 AT7
DDR_A_D58 SA_DQ[57] DDR_A_MA0 DDR_B_D61 SB_DQ[60]
AM13 SA_DQ[58] SA_MA[0] Y3 AP9 SB_DQ[61]
DDR_A_D59 AT14 W1 DDR_A_MA1 DDR_B_D62 AR10
B DDR_A_D60 SA_DQ[59] SA_MA[1] DDR_A_MA2 DDR_B_D63 SB_DQ[62] DDR_B_MA0 B
AT12 SA_DQ[60] SA_MA[2] AA8 AT10 SB_DQ[63] SB_MA[0] U5
DDR_A_D61 AL13 AA3 DDR_A_MA3 V2 DDR_B_MA1
DDR_A_D62 SA_DQ[61] SA_MA[3] DDR_A_MA4 SB_MA[1] DDR_B_MA2
AR14 SA_DQ[62] SA_MA[4] V1 SB_MA[2] T5
DDR_A_D63 AP14 AA9 DDR_A_MA5 V3 DDR_B_MA3
SA_DQ[63] SA_MA[5] DDR_A_MA6 SB_MA[3] DDR_B_MA4
SA_MA[6] V8 SB_MA[4] R1
T1 DDR_A_MA7 DDR_B_BS0 AB1 T8 DDR_B_MA5
SA_MA[7] 12 DDR_B_BS0 SB_BS[0] SB_MA[5]
Y9 DDR_A_MA8 DDR_B_BS1 W5 R2 DDR_B_MA6
SA_MA[8] 12 DDR_B_BS1 SB_BS[1] SB_MA[6]
DDR_A_BS0 AC3 U6 DDR_A_MA9 DDR_B_BS2 R7 R6 DDR_B_MA7
11 DDR_A_BS0 SA_BS[0] SA_MA[9] 12 DDR_B_BS2 SB_BS[2] SB_MA[7]
DDR_A_BS1 AB2 AD4 DDR_A_MA10 R4 DDR_B_MA8
11 DDR_A_BS1 SA_BS[1] SA_MA[10] SB_MA[8]
DDR_A_BS2 U7 T2 DDR_A_MA11 R5 DDR_B_MA9
11 DDR_A_BS2 SA_BS[2] SA_MA[11] SB_MA[9]
U3 DDR_A_MA12 DDR_B_CAS# AC5 AB5 DDR_B_MA10
SA_MA[12] 12 DDR_B_CAS# SB_CAS# SB_MA[10]
AG8 DDR_A_MA13 DDR_B_RAS# Y7 P3 DDR_B_MA11
SA_MA[13] 12 DDR_B_RAS# SB_RAS# SB_MA[11]
T3 DDR_A_MA14 DDR_B_WE# AC6 R3 DDR_B_MA12
SA_MA[14] 12 DDR_B_WE# SB_WE# SB_MA[12]
DDR_A_CAS# AE1 V9 DDR_A_MA15 AF7 DDR_B_MA13
11 DDR_A_CAS# SA_CAS# SA_MA[15] SB_MA[13]
DDR_A_RAS# AB3 P5 DDR_B_MA14
11 DDR_A_RAS# SA_RAS# SB_MA[14]
DDR_A_WE# AE9 N1 DDR_B_MA15
11 DDR_A_WE# SA_WE# SB_MA[15]
IC,AUB_CFD_rPGA,R0P9
CONN@
IC,AUB_CFD_rPGA,R0P9
A
CONN@ A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
PROCESSOR (3/6) DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 7 of 61
5 4 3 2 1
5 4 3 2 1
JCPU1F
WW15 MOW 3/3 Follow Module design
+CPU_CORE
Peak 21A +1.1VS_VTT
48A Continuous 18A
10U_0805_6.3V6M
AG35 AH14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC1 VTT0_1
AG34 VCC2 VTT0_2 AH12
AG33 AH11 3/3 Add +CPU_CORE
VCC3 VTT0_3
AG32 AH10 1 1 1 1 1 1 1 1 1
D VCC4 VTT0_4 C335 C336 C337 C338 C339 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M D
AG31 J14
VCC5 VTT0_5 C334 C340 C341 C342
AG30 J13
VCC6 VTT0_6
AG29 VCC7 VTT0_7 H14 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2
AG28 VCC8 VTT0_8 H12
AG27 G14 C343 C344 C345 C346 C347 C348 C349 C350 C351
VCC9 VTT0_9 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AG26 G13
VCC10 VTT0_10 10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2
AF35 G12
VCC11 VTT0_11
AF34 G11
VCC12 VTT0_12 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AF33 VCC13 VTT0_13 F14
AF32
VCC14 VTT0_14
F13 (Place these capacitors between inductor and socket on Bottom)
AF31 F12
VCC15 VTT0_15 +1.1VS_VTT
AF30
VCC16 VTT0_16
F11 3/12 Follow Module design
AF29 E14 +CPU_CORE
VCC17 VTT0_17 330U_X_2VM_R6M 22U_0805_6.3V6M
AF28 E12
VCC18 VTT0_18 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AF27 VCC19 VTT0_19 D14 1 1 1 3/12 Add
AF26 D13 1 1
VCC20 VTT0_20 + + +
1.1V RAIL POWER
AD35 D12 1 1 1 1 1 1 1
VCC21 VTT0_21 C352 C353 C354 C851 C852
AD34 D11
VCC22 VTT0_22 @ C355 C356 C357 C358 C359 C360 C361
AD33 C14
VCC23 VTT0_23 2 2 2 2 2
AD32 VCC24 VTT0_24 C13
2 2 2 2 2 2 2
AD31 C12
VCC25 VTT0_25 330U_X_2VM_R6M 330U_X_2VM_R6M 22U_0805_6.3V6M
AD30 C11
VCC26 VTT0_26 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AD29 B14
VCC27 VTT0_27
AD28
VCC28 VTT0_28
B12 (Place these capacitors under CPU socket, top layer)
AD27 VCC29 VTT0_29 A14
AD26
VCC30 VTT0_30
A13 CSC (Current Sense Configuration) 3/3 Follow Module design
AC35
VCC31 VTT0_31
A12 3/3 Follow Module design 8/25 +1.1VS_VTT
AC34 A11
VCC32 VTT0_32
AC33
AC32
VCC33 +1.1VS_VTT remove it from
+CPU_CORE
VCC34
AC31
VCC35 22U_0805_6.3V6M
CPU_VID0 R218 1
R219 1 @
2 1K_0402_1% BOM, DVT
AC30 AF10 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
C VCC36 VTT0_33 C
AC29
VCC37 VTT0_34
AE10 3/3 Add
AC28 AC10 1 1 1 CPU_VID1 R220 1 2 1K_0402_1% 1 1 1 1 1 1
VCC38 VTT0_35
CPU CORE SUPPLY
AC27 AB10 R221 1 @ 2 1K_0402_1% @ @ @
VCC39 VTT0_36 C362 C363 C364 C365 C366 C367 C368 C369 C370
AC26 Y10
VCC40 VTT0_37 CPU_VID2 R222 1
AA35 W10 2 1K_0402_1%
VCC41 VTT0_38 2 2 2 R223 1 @ 2 2 2 2 2 2
AA34 U10 2 1K_0402_1%
VCC42 VTT0_39
AA33 T10
VCC43 VTT0_40 22U_0805_6.3V6M 22U_0805_6.3V6M CPU_VID3 R224 1 @
AA32 J12 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC44 VTT0_41 R225 1
AA31 J11 2 1K_0402_1%
VCC45 VTT0_42
AA30
VCC46 VTT0_43
J16 (Place these capacitors on CPU cavity, Bottom Layer)
AA29 J15 CPU_VID4 R226 1 @ 2 1K_0402_1%
VCC47 VTT0_44 R227 1
AA28 2 1K_0402_1%
VCC48
AA27
VCC49 CPU_VID5 R228 1 +CPU_CORE
AA26 VCC50 2 1K_0402_1%
Y35 R229 1 @ 2 1K_0402_1%
VCC51 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
Y34
VCC52 CPU_VID6 R230 1 @
Y33 2 1K_0402_1%
VCC53 R231 1
Y32 2 1K_0402_1% 1 1 1 1 1 1
VCC54
Y31
VCC55 H_DPRSLPVR R232 1
Y30 2 1K_0402_1% C372 C373 C374 C375 C376 C371
VCC56 R233 1 @
Y29 2 1K_0402_1%
VCC57 2 2 2 2 2 2
Y28
VCC58 H_PSI# R234 1 @
Y27 VCC59 2 1K_0402_1%
Y26 R235 1 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC60
V35
VCC61 PSI#
AN33 H_PSI# 57 (Place these capacitors on CPU cavity, Bottom Layer)
V34
POWER
VCC62
V33
VCC63
V32 VCC64 VID[0] AK35 CPU_VID0 57
V31 AK33 +CPU_CORE 3/3 Add
VCC65 VID[1] CPU_VID1 57
V30 AK34 CPU_VID2 57
VCC66 VID[2] 22U_0805_6.3V6M 22U_0805_6.3V6M
V29 AL35 CPU_VID3 57
VCC67 VID[3]
CPU VIDS
V28 AL33 CPU_VID4 57
B VCC68 VID[4] B
V27 VCC69 VID[5] AM33 CPU_VID5 57 1 1 1 1
V26 AM35 CPU_VID6 57
VCC70 VID[6] C377 C378 C379 C380
U35 AM34 H_DPRSLPVR 57
VCC71 PROC_DPRSLPVR
U34
VCC72 2 2 2 2
U33
VCC73
U32
VCC74 H_VTTVID1 22U_0805_6.3V6M 22U_0805_6.3V6M
U31 G15 H_VTTVID1 54
VCC75 VTT_SELECT
U30
VCC76 (Place these capacitors on CPU cavity, Bottom Layer)
U29
VCC77 @
U28
VCC78
H_VTTVID1 = low, 1.1V VTT Rail
U27
VCC79
U26 VCC80
H_VTTVID1 = high, 1.05V
R35
VCC81 Auburndale +1.1VS_VTT=1.05V
R34
VCC82 Clarksfield +1.1VS_VTT=1.1V +CPU_CORE 470U_D2_2VM_R4.5M
R33
VCC83 4 x 470uF(6mohm@100kHz; 4.0mohm@SRF)
R32 AN35 IMVP_IMON 57
VCC84 ISENSE 470U_D2_2VM_R4.5M 470U_D2_2VM_R4.5M 470U_D2_2VM_R4.5M 470U_D2_2VM_R4.5M 470U_D2_2VM_R4.5M
R31 VCC85
R30 1 2 +CPU_CORE 1 1 1 1 1 1
VCC86 R236 100_0402_1%
R29
VCC87 VCCSENSE_R R237 1 VCCSENSE + + + + + +
2 0_0402_5%
SENSE LINES
R28 AJ34
VCC88 VCC_SENSE VSSSENSE_R R238 1 VSSSENSE VCCSENSE 57
R27 AJ35 2 0_0402_5% C381 3 C382 3 C383 3 C384 3 C385 3 C386 3
VCC89 VSS_SENSE VSSSENSE 57 @
R26 VCC90
P35 1 2 2 2 2 2 2 @ 2
VCC91 R239 100_0402_1%
P34 B15 VTT_SENSE 54
VCC92 VTT_SENSE VSS_SENSE_VTT
P33 A15
VCC93 VSS_SENSE_VTT R240 1
P32 2 0_0402_5% TOP side (under inductor)
VCC94
P31
VCC95
P30 VCC96
P29
VCC97 +CPU-CORE C,uF ESR, mohm Stuffing Option
P28
VCC98 Decoupling
P27
VCC99 change to SGA00001Q80
P26
VCC100 SPCAP,Polymer 4X470uF 4m ohm/4 2X470uF
A
DVT A
16X22uF 3m ohm/12
MLCC 0805 X5R
16X10uF 3m ohm/16
IC,AUB_CFD_rPGA,R0P9 Security Classification Compal Secret Data Compal Electronics, Inc.
CONN@ 2009/02/04 2010/02/04 Title
Issued Date Deciphered Date
PROCESSOR (4/6) PWR,Bypass
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 8 of 61
5 4 3 2 1
5 4 3 2 1
+VGFX_CORE
JCPU1G
AT21 VAXG1
330U_D2_2VM_R6M
330U_D2_2VM_R6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0603_10V4Z
1U_0603_10V4Z
10U_0805_6.3V6M
10U_0805_6.3V6M
AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE
R310
SENSE
LINES
1 1 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE
2
C933
C934
C835
C834
C779
C818
C816
C815
C817
C207
1 1 1 1 1 1 1 1 AT16 VAXG4
D 0_0402_5% + + AR21 D
VAXG5
AR19 VAXG6
DISO@ AR18
2 2 2 2 2 2 2 2 2 2 VAXG7
AR16 AM22 GFXVR_VID_0
1
VAXG8 GFX_VID[0]
AP21 VAXG9 GFX_VID[1] AP22 GFXVR_VID_1
GRAPHICS VIDs
@ @ @ @ @ UMA@ UMA@ UMA@ UMA@ AP19 AN22
VAXG10 GFX_VID[2] GFXVR_VID_2
UMA@ AP18 AP23
VAXG11 GFX_VID[3] GFXVR_VID_3
AP16 VAXG12 22A GFX_VID[4] AM23 GFXVR_VID_4
AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5
GRAPHICS
AN19 VAXG14 GFX_VID[6] AN24 GFXVR_VID_6
AN18 VAXG15
AN16 VAXG16
AM21 VAXG17 GFX_VR_EN AR25 GFXVR_EN
AM19 VAXG18 GFX_DPRSLPVR AT25 GFXVR_DPRSLPVR
AM18 VAXG19 GFX_IMON AM24 GFXVR_IMON
AM16 R241 1 2 1K_0402_5%
VAXG20 DISO@
AL21 VAXG21
AL19 VAXG22 Follow Module design
AL18 +1.5V
VAXG23 1U_0402_6.3V6K 1U_0402_6.3V6K
AL16 VAXG24
AK21 AJ1 22U_0805_6.3V6M
VAXG25 VDDQ1
AK19 VAXG26 VDDQ2 AF1 1
AK18 AE7
- 1.5V RAILS
VAXG27 VDDQ3 1 1 1 1 1 1 1
AK16 AE4 +
VAXG28 VDDQ4 C387 C388 C389 C390 C391 C392 C393 C394
AJ21 VAXG29 VDDQ5 AC1
AJ19 VAXG30 VDDQ6 AB7
2 2 2 2 2 2 2 2 330U_D2_2V_Y
AJ18 VAXG31 VDDQ7 AB4
AJ16 VAXG32 3A VDDQ8 Y1
AH21 VAXG33 VDDQ9 W7
POWER
C AH19 W4 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K C
VAXG34 VDDQ10 22U_0805_6.3V6M
AH18 VAXG35 VDDQ11 U1
AH16 VAXG36 VDDQ12 T7 4/15 Change Value of C387~C392 to 1uF(0402_6.3V4K)
VDDQ13 T4
VDDQ14 P1
+1.1VS_VTT N7
VDDQ15
VDDQ16 N4
DDR3
VDDQ17 L1
J24 VTT1_45 VDDQ18 H1
FDI
J23 VTT1_46
1 1 H25 VTT1_47 +1.1VS_VTT
C395 C396
P10 10U_0805_6.3V6M
22U_0805_6.3V6M 2 2 22U_0805_6.3V6M VTT0_59
VTT0_60 N10
VTT0_61 L10 3/3 Add 1 1
VTT0_62 K10
C397 C398
3/3 Follow Module design +1.1VS_VTT
2 2 10U_0805_6.3V6M
+1.1VS_VTT
1.1V
J22 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_63
K26 VTT1_48 VTT1_64 J20
J27 VTT1_49 VTT1_65 J18 3/3 Add 1 1
PEG & DMI
1 1 1 1 J26 VTT1_50 VTT1_66 H21
J25 H20 C403 C404
C399 C400 C401 C402 VTT1_51 VTT1_67
H27 VTT1_52 VTT1_68 H19
2 2 22U_0805_6.3V6M
G28 VTT1_53
22U_0805_6.3V6M 2 2 2 2
G27 VTT1_54
B B
G26 VTT1_55
3/3 Add F26 +1.8VS
22U_0805_6.3V6M VTT1_56 R242
E26 VTT1_57 VCCPLL1 L26
1.8V
E25 0.6A L27 0.022_0805_1%
VTT1_58 VCCPLL2 +1.8VS_VCCSFR 2.2U_0603_6.3V6K
VCCPLL3 M26 1 2
1 1 1 1 1
C405 C406 C407 C408 C409
1U_0402_6.3V4Z 2 2 2 2 2 22U_0805_6.3V6M
IC,AUB_CFD_rPGA,R0P9 1U_0402_6.3V4Z 4.7U_0805_10V4Z
CONN@
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
PROCESSOR (5/6) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 9 of 61
5 4 3 2 1
5 4 3 2 1
JCPU1I
JCPU1H
AT20 VSS1 VSS81 AE34
AT17 VSS2 VSS82 AE33 K27 VSS161
AR31 VSS3 VSS83 AE32 K9 VSS162
AR28 VSS4 VSS84 AE31 K6 VSS163
AR26 VSS5 VSS85 AE30 K3 VSS164
AR24 VSS6 VSS86 AE29 J32 VSS165
AR23 VSS7 VSS87 AE28 J30 VSS166
AR20 VSS8 VSS88 AE27 J21 VSS167
AR17 VSS9 VSS89 AE26 J19 VSS168
D AR15 VSS10 VSS90 AE6 H35 VSS169 D
AR12 VSS11 VSS91 AD10 H32 VSS170
AR9 VSS12 VSS92 AC8 H28 VSS171
AR6 VSS13 VSS93 AC4 H26 VSS172
AR3 VSS14 VSS94 AC2 H24 VSS173
AP20 VSS15 VSS95 AB35 H22 VSS174
AP17 VSS16 VSS96 AB34 H18 VSS175
AP13 VSS17 VSS97 AB33 H15 VSS176
AP10 VSS18 VSS98 AB32 H13 VSS177
AP7 VSS19 VSS99 AB31 H11 VSS178
AP4 VSS20 VSS100 AB30 H8 VSS179
AP2 VSS21 VSS101 AB29 H5 VSS180
AN34 VSS22 VSS102 AB28 H2 VSS181
AN31 VSS23 VSS103 AB27 G34 VSS182
AN23 VSS24 VSS104 AB26 G31 VSS183
AN20 VSS25 VSS105 AB6 G20 VSS184
AN17 VSS26 VSS106 AA10 G9 VSS185
AM29 VSS27 VSS107 Y8 G6 VSS186
AM27 VSS28 VSS108 Y4 G3 VSS187
AM25 VSS29 VSS109 Y2 F30 VSS188
AM20 VSS30 VSS110 W35 F27 VSS189
AM17 VSS31 VSS111 W34 F25 VSS190
AM14 VSS32 VSS112 W33 F22 VSS191
AM11 VSS33 VSS113 W32 F19 VSS192
AM8 VSS34 VSS114 W31 F16 VSS193
AM5 VSS35 VSS115 W30 E35 VSS194
AM2 W29 E32
AL34
AL31
VSS36
VSS37
VSS38 VSS
VSS116
VSS117
VSS118
W28
W27
E29
E24
VSS195
VSS196
VSS197
VSS
C AL23 W26 E21 C
VSS39 VSS119 VSS198
AL20 VSS40 VSS120 W6 E18 VSS199
AL17 VSS41 VSS121 V10 E13 VSS200
AL12 VSS42 VSS122 U8 E11 VSS201
AL9 VSS43 VSS123 U4 E8 VSS202
AL6 VSS44 VSS124 U2 E5 VSS203
AL3 T35 E2 AT35 H_NCTF1 @ PAD T12
VSS45 VSS125 VSS204 VSS_NCTF1 H_NCTF2 @
AK29 VSS46 VSS126 T34 D33 VSS205 VSS_NCTF2 AT1 PAD T13
AK27 VSS47 VSS127 T33 D30 VSS206 VSS_NCTF3 AR34
AK25 T32 D26 B34
FAN1 Conn AK20
VSS48 VSS128
T31 D9
VSS207 VSS_NCTF4
B2
NCTF
VSS49 VSS129 VSS208 VSS_NCTF5 H_NCTF6 @
AK17 VSS50 VSS130 T30 D6 VSS209 VSS_NCTF6 B1 PAD T14
AJ31 T29 D3 A35 H_NCTF7 @ PAD T15
@ VSS51 VSS131 VSS210 VSS_NCTF7
AJ23 VSS52 VSS132 T28 C34 VSS211
EN_FAN1 C410 2 1 100P_0402_50V8J AJ20 T27 C32
VSS53 VSS133 VSS212
AJ17 VSS54 VSS134 T26 C29 VSS213
AJ14 VSS55 VSS135 T6 C28 VSS214
AJ11 VSS56 VSS136 R10 C24 VSS215
AJ8 VSS57 VSS137 P8 C22 VSS216
+5VS AJ5 P4 C20
C411 VSS58 VSS138 VSS217
AJ2 VSS59 VSS139 P2 C19 VSS218
10U_0805_10V4Z 1 2 AH35 N35 C16
VSS60 VSS140 VSS219
AH34 VSS61 VSS141 N34 B31 VSS220
AH33 VSS62 VSS142 N33 B25 VSS221
U11 AH32 N32 B21
VSS63 VSS143 VSS222
1VEN GND 8 AH31 VSS64 VSS144 N31 B18 VSS223
2VIN GND 7 AH30 VSS65 VSS145 N30 B17 VSS224
+VCC_FAN1 3 6 AH29 N29 B13
EN_FAN1_R VO GND VSS66 VSS146 VSS225
39 EN_FAN1 1 2 4VSET GND 5 AH28 VSS67 VSS147 N28 B11 VSS226
B R243 B
AH27 VSS68 VSS148 N27 B8 VSS227
1
330_0402_5% G990P11U_SOP8 AH26 N26 B6
C412 VSS69 VSS149 VSS228
AH20 VSS70 VSS150 N6 B4 VSS229
0.047U_0402_16V7K AH17 M10 A29
2
VSS71 VSS151 VSS230
AH13 VSS72 VSS152 L35 A27 VSS231
+5VS AH9 L32 A23
VSS73 VSS153 VSS232
AH6 VSS74 VSS154 L29 A9 VSS233
AH3 VSS75 VSS155 L8
1
AG10 VSS76 VSS156 L5
D1 AF8 L2
VSS77 VSS157
BAS16_SOT23-3 AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 K30
2
D2 VSS80 VSS160
1 2
BAS16_SOT23-3 IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9 CONN@
C413
CONN@
+3VS 2.2U_0603_6.3V6K
C414
1 2
1
R244 1000P_0402_50V7K
10K_0402_5%
40mil JP1
2
A A
+VCC_FAN1 1 1
39 FAN_SPEED1 2 2
3 3
1
C415 4
1000P_0402_50V7K GND
5
2
GND Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
ACES_85205-03001
CONN@ PROCESSOR (6/6) VSS& FAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 10 of 61
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V
M1 Circuit M3 Circuit
7 DDR_A_DQS#[0..7] DISO@ JP2
+1.5V R245 1 2 0_0402_5% VREF_DQA 1 2
7 DDR_A_D[0..63] 5 H_DIMMA_REF VREF_DQ VSS DDR_A_D4
3 4
DDR_A_D0 VSS DQ4 DDR_A_D5
5 6
7 DDR_A_DM[0..7] DQ0 DQ5
1
R247 1 2 0_0402_5% DDR_A_D1 7 8
+V_DDR3_DIMM_REF +V_DDR3_DIMM_REF DQ1 VSS
R246 9 10 DDR_A_DQS#0
7 DDR_A_DQS[0..7] DDR_A_DM0 VSS DQS0# DDR_A_DQS0
11 DM0 DQS0 12
1K_0402_1% 13 14
7 DDR_A_MA[0..15] DDR_A_D2 VSS VSS DDR_A_D6
15 16
2
+V_DDR3_DIMM_REF DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 18
DQ3 DQ7
19 VSS VSS 20
1
1 1 DDR_A_D8 21 22 DDR_A_D12
R249 DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
D C417 C416 DQ9 DQ13 D
25 26
1K_0402_1% 0.1U_0402_16V4Z 2.2U_0805_16V4Z DDR_A_DQS#1 VSS VSS DDR_A_DM1
27 28
2 2 DDR_A_DQS1 DQS1# DM1 SM_DRAMRST#
29 30
2
DQS1 RESET# SM_DRAMRST# 6,12
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 38
DDR_A_D16 VSS VSS DDR_A_D20
39 40
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 44
DDR_A_DQS#2 VSS VSS DDR_A_DM2
45 46
DDR_A_DQS2 DQS2# DM2
47 48
DQS2 VSS DDR_A_D22
49 50
DDR_A_D18 VSS DQ22 DDR_A_D23
51 52
DDR_A_D19 DQ18 DQ23
53 DQ19 VSS 54
55 56 DDR_A_D28
DDR_A_D24 VSS DQ28 DDR_A_D29
57 58
DDR_A_D25 DQ24 DQ29
59 60
DQ25 VSS DDR_A_DQS#3
61 62
DDR_A_DM3 VSS DQS3# DDR_A_DQS3
63 DM3 DQS3 64
65 66
DDR_A_D26 VSS VSS DDR_A_D30
67 68
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 70
DQ27 DQ31
71 72
VSS VSS
DDR_A_CKE0 73 74 DDR_A_CKE1
7 DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 7
75 76
VDD VDD DDR_A_MA15
77 78
DDR_A_BS2 NC A15 DDR_A_MA14
7 DDR_A_BS2 79 BA2 A14 80 2/28 Module design don't use pin78(NC),need
81 82 double check it.
DDR_A_MA12 VDD VDD DDR_A_MA11
83 84
C DDR_A_MA9 A12/BC# A11 DDR_A_MA7 C
85 86
A9 A7
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 92
A5 A4
93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95 96
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
A1 A0
99 100
DDR_A_CLK0 VDD VDD DDR_A_CLK1
7 DDR_A_CLK0 101 102 DDR_A_CLK1 7
DDR_A_CLK0# CK0 CK1 DDR_A_CLK1#
7 DDR_A_CLK0# 103 104 DDR_A_CLK1# 7
CK0# CK1#
105 106
DDR_A_MA10 VDD VDD DDR_A_BS1
107 108 DDR_A_BS1 7
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
7 DDR_A_BS0 109 110 DDR_A_RAS# 7
BA0 RAS#
111 VDD VDD 112
DDR_A_WE# 113 114 DDR_A_CS0#
7 DDR_A_WE# DDR_A_CAS# WE# S0# DDR_A_ODT0 DDR_A_CS0# 7
7 DDR_A_CAS# 115 116 DDR_A_ODT0 7
CAS# ODT0
117 118
DDR_A_MA13 VDD VDD DDR_A_ODT1 +V_DDR3_DIMM_REF
119 120 DDR_A_ODT1 7
DDR_A_CS1# A13 ODT1
7 DDR_A_CS1# 121 122
S1# NC
123 124
VDD VDD DDR_VREF_CA_DIMMA R256 1
125 126 2 0_0402_5%
TEST VREF_CA
127 128
DDR_A_D32 VSS VSS DDR_A_D36
129 DQ32 DQ36 130
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37
Layout Note: DDR_A_DQS#4
133
VSS VSS
134
DDR_A_DM4
135 136
Place near JP2 DDR_A_DQS4 DQS4# DM4
137 138 1 1
DQS4 VSS DDR_A_D38
139 VSS DQ38 140
DDR_A_D34 141 142 DDR_A_D39 C421 C422
DDR_A_D35 DQ34 DQ39
Layout Note: Place these 4 Caps near Command 143
DQ35 VSS
144 2.2U_0603_6.3V4Z
2 2
0.1U_0402_16V4Z
Follow Module design 145 146 DDR_A_D44
and Control signals of DIMMA DDR_A_D40 147
VSS DQ44
148 DDR_A_D45
B DDR_A_D41 DQ40 DQ45 B
149 DQ41 VSS 150
+1.5V 151 152 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
153 154
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M DM5 DQS5
155 156
DDR_A_D42 VSS VSS DDR_A_D46
3/3 Add(Follow Module design) 157
DQ42 DQ46
158
1 DDR_A_D43 159 160 DDR_A_D47
DQ43 DQ47
1 1 1 1 1 1 1 1 1 1 1 1 161 162
C424 C426 C428 + DDR_A_D48 VSS VSS DDR_A_D52
163 164
C423 C425 C427 C429 C430 C431 C432 C433 C434 C435 DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
DQ49 DQ53
167 168
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS#6 VSS VSS DDR_A_DM6
169 170
DDR_A_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_A_D54
DDR_A_D50 VSS DQ54 DDR_A_D55
175 176
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 330U_D2_2V_Y 10U_0603_6.3V6M DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS DDR_A_D60
4/15 Change value of C423~C428 from 179
VSS DQ60
180
DDR_A_D56 181 182 DDR_A_D61
10uF(0805_6.3V6M) to 10uF(0603_6.3V6M) DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS DDR_A_DQS#7
185 186
DDR_A_DM7 VSS DQS7# DDR_A_DQS7
187 188
DM7 DQS7
189 190
DDR_A_D58 VSS VSS DDR_A_D62
Layout Note: DDR_A_D59
191 DQ58 DQ62 192
DDR_A_D63
193 194
Place near JP2.203 & JP2.204 DQ59 DQ63
195 196
R257 1 VSS VSS PM_EXTTS#0_1
2 10K_0402_5% 197 198 PM_EXTTS#0_1 6,12
SA0 EVENT# D_CK_SDATA
+3VS 199 200
VDDSPD SDA D_CK_SCLK D_CK_SDATA 6,12,23
201 202
SA1 SCL D_CK_SCLK 6,12,23
1 1 203 VTT VTT 204 +0.75VS
1
+0.75VS 4/15 Change value of C438~C442 from
1uF(0603_10V4Z) to 1U(0402_6.3V6K) C436 C437 205 206
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0805_6.3V6M 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z R258 GND1 BOSS1
207 208
2 2 10K_0402_5% GND2 BOSS2
Follow Module design
A
DDR3 SO-DIMM A A
2
FOX_AS0A626-U2SN-7F_204P
1
C439
1
C440
1
C441
1
C442
1 1
C853
3/16 Add C853= 10uF(0805_6.3V6M)(Intel's comment) Standard Type
CONN@
C438
2 2 2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0805_6.3V6M
DDRIII-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 11 of 61
5 4 3 2 1
5 4 3 2 1
+1.5V
M1 Circuit +1.5V
2008/9/8 #400755 JP3
Calpella Clarksfield R259 1 2 0_0402_5% VREF_DQB 1 2
7 DDR_B_DQS#[0..7] +V_DDR3_DIMM_REF VREF_DQ VSS
DDR3 SO-DIMM 3 4 DDR_B_D4
DDR_B_D0 VSS DQ4 DDR_B_D5
VREFDQ Platform 5 6
7 DDR_B_D[0..63] DQ0 DQ5
M3 Circuit DDR_B_D1 7 8
Design Guide Change Details R261 DQ1 VSS DDR_B_DQS#0
5 H_DIMMB_REF 1 2 0_0402_5% 9 VSS DQS0# 10
DISO@ DDR_B_DM0 11 12 DDR_B_DQS0
7 DDR_B_DM[0..7] DM0 DQS0
13 14
DDR_B_D2 VSS VSS DDR_B_D6
15 16
7 DDR_B_DQS[0..7] DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
19 VSS VSS 20
7 DDR_B_MA[0..15] DDR_B_D8 DDR_B_D12
21 22
D DDR_B_D9 DQ8 DQ12 DDR_B_D13 D
3/3 Change value and 23
DQ9 DQ13
24
symbol of C1833 to 25 26
DDR_B_DQS#1 VSS VSS DDR_B_DM1
27 28
2.2uF(0603_6.3V4Z) DDR_B_DQS1 29
DQS1# DM1
30 SM_DRAMRST#
1 1 DQS1 RESET# SM_DRAMRST# 6,11
31 32
C443 C444 DDR_B_D10 VSS VSS DDR_B_D14
33 34
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
2.2U_0603_6.3V4Z 2 2 DQ11 DQ15
37 38
DDR_B_D16 VSS VSS DDR_B_D20
39 DQ16 DQ20 40
Follow Module design DDR_B_D17 41 42 DDR_B_D21
0.1U_0402_16V4Z DQ17 DQ21
43 44
DDR_B_DQS#2 VSS VSS DDR_B_DM2
45 46
DDR_B_DQS2 DQS2# DM2
47 48
DQS2 VSS DDR_B_D22
49 50
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS DDR_B_D28
55 56
DDR_B_D24 VSS DQ28 DDR_B_D29
57 58
DDR_B_D25 DQ24 DQ29
59 60
DQ25 VSS DDR_B_DQS#3
61 VSS DQS3# 62
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
65 66
DDR_B_D26 VSS VSS DDR_B_D30
67 68
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 70
DQ27 DQ31
71 VSS VSS 72
DDR_B_CKE0 73 74 DDR_B_CKE1
7 DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 7
75 76
VDD VDD DDR_B_MA15
77 NC A15 78
DDR_B_BS2 79 80 DDR_B_MA14 2/28 Module design don't use pin78(NC),need
7 DDR_B_BS2 BA2 A14
81 82 double check it.
C DDR_B_MA12 VDD VDD DDR_B_MA11 C
83 84
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 88
DDR_B_MA8 VDD VDD DDR_B_MA6
89 90
DDR_B_MA5 A8 A6 DDR_B_MA4
91 92
A5 A4
93 94
DDR_B_MA3 VDD VDD DDR_B_MA2
95 96
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
DDR_B_CLK0 VDD VDD DDR_B_CLK1
7 DDR_B_CLK0 101 102 DDR_B_CLK1 7
DDR_B_CLK0# CK0 CK1 DDR_B_CLK1#
7 DDR_B_CLK0# 103 104 DDR_B_CLK1# 7
CK0# CK1#
105 106
DDR_B_MA10 VDD VDD DDR_B_BS1
107 108 DDR_B_BS1 7
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
7 DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# 7
111 112
DDR_B_WE# VDD VDD DDR_B_CS0#
7 DDR_B_WE# 113 114 DDR_B_CS0# 7
DDR_B_CAS# WE# S0# DDR_B_ODT0
7 DDR_B_CAS# 115 116 DDR_B_ODT0 7
CAS# ODT0
117 118
DDR_B_MA13 VDD VDD DDR_B_ODT1
Layout Note: DDR_B_CS1#
119
A13 ODT1
120 DDR_B_ODT1 7 +V_DDR3_DIMM_REF
7 DDR_B_CS1# 121 122
Place near JP3 S1# NC
123 124
VDD VDD DDR_VREF_CA_DIMMB R266 1
125 126 2 0_0402_5%
TEST VREF_CA
Layout Note: Place these 4 Caps near Command 127 VSS VSS 128
DDR_B_D32 129 130 DDR_B_D36
and Control signals of DIMMA DDR_B_D33 131
DQ32 DQ36
132 DDR_B_D37
DQ33 DQ37
133 134
+1.5V DDR_B_DQS#4 VSS VSS DDR_B_DM4
135 136
10U_0603_6.3V6M DDR_B_DQS4 DQS4# DM4
137 DQS4 VSS 138 1 1
10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 330U_D2_2V_Y 10U_0603_6.3V6M 139 140 DDR_B_D38 C447 C448
DDR_B_D34 VSS DQ38 DDR_B_D39
141 142
DDR_B_D35 DQ34 DQ39 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z
1 143 144
DQ35 VSS DDR_B_D44 2 2
1 1 1 1 1 1 1 1 1 1 1 1 145 146
B C450 C455 C456 C457 C458 C459 + DDR_B_D40 VSS DQ44 DDR_B_D45 B
147 DQ40 DQ45 148
C449 C451 C452 C453 C454 C460 C461 DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 152
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_B_DM5 VSS DQS5# DDR_B_DQS5
153 154
DM5 DQS5
155 156
DDR_B_D42 VSS VSS DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M DQ43 DQ47
161 162
DDR_B_D48 VSS VSS DDR_B_D52
3/3 Add(Follow Module design) 163
DQ48 DQ52
164
DDR_B_D49 165 166 DDR_B_D53
DQ49 DQ53
167 168
DDR_B_DQS#6 VSS VSS DDR_B_DM6
169 DQS6# DM6 170
DDR_B_DQS6 171 172
DQS6 VSS DDR_B_D54
Layout Note: DDR_B_D50
173
VSS DQ54
174
DDR_B_D55
175 176
Place near JP3.203 & JP3.204 DDR_B_D51 DQ50 DQ55
4/15 Change value of C462~C465 from 177
DQ51 VSS
178
179 180 DDR_B_D60
1uF(0603_10V4Z) to 1U(0402_6.3V6K) DDR_B_D56 VSS DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
Follow Module design 183
DQ57 VSS
184
185 186 DDR_B_DQS#7
+0.75VS DDR_B_DM7 VSS DQS7# DDR_B_DQS7
187 188
DM7 DQS7
189 VSS VSS 190
1U_0402_6.3V6K 1U_0402_6.3V6K DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
195 196
R267 1 VSS VSS PM_EXTTS#0_1
2 10K_0402_5% 197 198 PM_EXTTS#0_1 6,11
SA0 EVENT# D_CK_SDATA
1 1 1 1 1 +3VS 199 200
C462 C463 C464 C465 C466 VDDSPD SDA D_CK_SCLK D_CK_SDATA 6,11,23
1 2 201 SA1 SCL 202
10U_0805_6.3V6M R268 10K_0402_5% D_CK_SCLK 6,11,23
203 204 +0.75VS
VTT VTT
2 2 2 2 2 1 1
205 206
C467 C468 GND1 BOSS1
207 208
A GND2 BOSS2 A
1U_0402_6.3V6K 1U_0402_6.3V6K
2.2U_0603_6.3V4Z 2 2 0.1U_0402_16V4Z DDR3 SO-DIMM B
TYCO_2-2013310-1_204P
CONN@
Standard Type
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
DDRIII-SODIMM SLOT2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 12 of 61
5 4 3 2 1
5 4 3 2 1
PCIE_MTX_C_GRX_N[0..15]
5 PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
5 PCIE_MTX_C_GRX_P[0..15]
U4A PCIE_GTX_C_MRX_N[0..15]
5 PCIE_GTX_C_MRX_N[0..15]
D D
PCIE_GTX_C_MRX_P[0..15]
5 PCIE_GTX_C_MRX_P[0..15]
T2 PAD PCIE_MTX_C_GRX_P0 AA38 Y33 PCIE_GTX_MRX_P0 C58 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P0
T3 PAD PCIE_MTX_C_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_GTX_MRX_N0 C66
Y37 PCIE_RX0N PCIE_TX0N Y32 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N0
PCIE_MTX_C_GRX_P1 Y35 W33 PCIE_GTX_MRX_P1 C68 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P1
PCIE_MTX_C_GRX_N1 PCIE_RX1P PCIE_TX1P PCIE_GTX_MRX_N1 C79
W36 PCIE_RX1N PCIE_TX1N W32 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N1
PCIE_MTX_C_GRX_P2 W38 U33 PCIE_GTX_MRX_P2 C83 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P2
PCIE_MTX_C_GRX_N2 PCIE_RX2P PCIE_TX2P PCIE_GTX_MRX_N2 C86
V37 PCIE_RX2N PCIE_TX2N U32 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N2
the same with M86
PCIE_MTX_C_GRX_P3 V35 U30 PCIE_GTX_MRX_P3 C87 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P3
PCIE_MTX_C_GRX_N3 PCIE_RX3P PCIE_TX3P PCIE_GTX_MRX_N3 C94
U36 PCIE_RX3N PCIE_TX3N U29 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N3
U4G
PCIE_MTX_C_GRX_P4 U38 T33 PCIE_GTX_MRX_P4 C95 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P4
PCIE_MTX_C_GRX_N4 PCIE_RX4P PCIE_TX4P PCIE_GTX_MRX_N4 C104 1
T37 PCIE_RX4N PCIE_TX4N T32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N4 PM@ 10K_0402_5%
PCI EXPRESS INTERFACE
2 R161 1
LVDS CONTROL AK27
PCIE_MTX_C_GRX_P5 PCIE_GTX_MRX_P5 C105 1 VARY_BL VGA_PWM 22
T35 PCIE_RX5P PCIE_TX5P T30 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P5
DIGON AJ27 VGA_ENVDD 22
PCIE_MTX_C_GRX_N5 R36 T29 PCIE_GTX_MRX_N5 C108 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N5 2 R162 1
PCIE_RX5N PCIE_TX5N PM@10K_0402_5%
C C
PCIE_MTX_C_GRX_P6 R38 P33 PCIE_GTX_MRX_P6 C109 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P6
PCIE_MTX_C_GRX_N6 PCIE_RX6P PCIE_TX6P PCIE_GTX_MRX_N6 C116 1
P37 PCIE_RX6N PCIE_TX6N P32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N6
TXCLK_UP_DPF3P AK35 VGA_LVDS_BCLK 22
TXCLK_UN_DPF3N AL36 VGA_LVDS_BCLK# 22
T5 PAD PCIE_MTX_C_GRX_P7 P35 P30 PCIE_GTX_MRX_P7 C117 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P7 AJ38
T1 PAD PCIE_MTX_C_GRX_N7 PCIE_RX7P PCIE_TX7P PCIE_GTX_MRX_N7 C122 1 TXOUT_U0P_DPF2P VGA_LVDS_B0 22
N36 PCIE_RX7N PCIE_TX7N P29 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N7
TXOUT_U0N_DPF2N AK37 VGA_LVDS_B0# 22
TXOUT_U1P_DPF1P AH35 VGA_LVDS_B1 22
PCIE_MTX_C_GRX_P8 N38 N33 PCIE_GTX_MRX_P8 C124 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P8 AJ36
PCIE_MTX_C_GRX_N8 PCIE_RX8P PCIE_TX8P PCIE_GTX_MRX_N8 C128 1 TXOUT_U1N_DPF1N VGA_LVDS_B1# 22
M37 PCIE_RX8N PCIE_TX8N N32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N8
TXOUT_U2P_DPF0P AG38 VGA_LVDS_B2 22
TXOUT_U2N_DPF0N AH37 VGA_LVDS_B2# 22
PCIE_MTX_C_GRX_P9 M35 N30 PCIE_GTX_MRX_P9 C130 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P9
PCIE_MTX_C_GRX_N9 PCIE_RX9P PCIE_TX9P PCIE_GTX_MRX_N9 C135 1
L36 PCIE_RX9N PCIE_TX9N N29 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N9
TXOUT_U3P AF35
TXOUT_U3N AG36
PCIE_MTX_C_GRX_P10 L38 L33 PCIE_GTX_MRX_P10 C139 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P10
PCIE_MTX_C_GRX_N10 PCIE_RX10P PCIE_TX10P PCIE_GTX_MRX_N10 C144 1 LVTMDP
K37 PCIE_RX10N PCIE_TX10N L32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N10
TXCLK_LP_DPE3P AP34 VGA_LVDS_ACLK 22
PCIE_MTX_C_GRX_P11 K35 L30 PCIE_GTX_MRX_P11 C146 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P11 AR34
PCIE_MTX_C_GRX_N11 PCIE_RX11P PCIE_TX11P PCIE_GTX_MRX_N11 C149 1 TXCLK_LN_DPE3N VGA_LVDS_ACLK# 22
J36 PCIE_RX11N PCIE_TX11N L29 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N11
TXOUT_L0P_DPE2P AW37 VGA_LVDS_A0 22
TXOUT_L0N_DPE2N AU35 VGA_LVDS_A0# 22
PCIE_MTX_C_GRX_P12 J38 K33 PCIE_GTX_MRX_P12 C150 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P12
PCIE_MTX_C_GRX_N12 PCIE_RX12P PCIE_TX12P PCIE_GTX_MRX_N12 C157 1
H37 PCIE_RX12N PCIE_TX12N K32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N12
TXOUT_L1P_DPE1P AR37 VGA_LVDS_A1 22
TXOUT_L1N_DPE1N AU39 VGA_LVDS_A1# 22
B PCIE_MTX_C_GRX_P13 PCIE_GTX_MRX_P13 C158 1 B
H35 PCIE_RX13P PCIE_TX13P J33 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P13
TXOUT_L2P_DPE0P AP35 VGA_LVDS_A2 22
PCIE_MTX_C_GRX_N13 G36 J32 PCIE_GTX_MRX_N13 C162 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N13 AR35
PCIE_RX13N PCIE_TX13N TXOUT_L2N_DPE0N VGA_LVDS_A2# 22
TXOUT_L3P AN36
PCIE_MTX_C_GRX_P14 G38 K30 PCIE_GTX_MRX_P14 C163 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P14 AP37
PCIE_MTX_C_GRX_N14 PCIE_RX14P PCIE_TX14P PCIE_GTX_MRX_N14 C165 1 TXOUT_L3N
F37 PCIE_RX14N PCIE_TX14N K29 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N14
T6 PAD PCIE_MTX_C_GRX_P15 F35 H33 PCIE_GTX_MRX_P15 C166 1 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_P15
T7 PAD PCIE_MTX_C_GRX_N15 PCIE_RX15P PCIE_TX15P PCIE_GTX_MRX_N15 C168 1
E37 PCIE_RX15N PCIE_TX15N H32 2 PM@ 0.1U_0402_16V7K PCIE_GTX_C_MRX_N15
216-0729042-00 A13 M96 BGA 962P 030
PM@
CLOCK
CLK_PCIE_VGA AB35
25 CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AA36 Need check
25 CLK_PCIE_VGA# PCIE_REFCLKN +1.8VSDGPU +3VS_DELAY
CALIBRATION R44 1.27K_0402_1%
AJ21 NC#1 PCIE_CALRP Y30 PCIE_CALRP 1 2
AK21 PM@ R115 R116
PWRGOOD_BUF NC#2
AH16 NC_PWRGOOD PCIE_CALRN Y29 PCIE_CALRN 1 2 +1.1VS M97@ 2K_0402_1% @ 2K_0402_1%
R43 2K_0402_1%
PM@ R117
PLTRST_VGA# AA30 PWRGOOD_BUF 1 M97@ 2
28 PLTRST_VGA# PERSTB EC_VGAPWRGOOD 39
DVT Rual: Change this power to +1.0VS! 06/09 1 0_0402_5%
2
C251 R118
R339 M97@ 2.37K_0402_1% item 02, Add M97@ 05/06
A 10K_0402_5% 216-0729042-00 A13 M96 BGA 962P 030 0.22U_0402_10V4Z @ A
MAD@ PM@ 2
1
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2009/02/24 Deciphered Date 2009/07/15 Title
M96- PCIE Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 13 of 61
5 4 3 2 1
5 4 3 2 1
Strap Name Pin Straps description Default Value
U4B External VGA Thermal Sensor
TX_PWRS_ENB GPIO0 Transmitter Power Saving Enable 0
0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)
TX_DEEMPH_EN GPIO1 PCI Express Transmitter De-emphasis Enable 0 AU24 VGA_HDMI_CLK+ +3VS_DELAY +3VS_DELAY
0: Tx de-emphasis diabled for mobile mode TXCAP_DPA3P VGA_HDMI_CLK- VGA_HDMI_CLK+ 20
AV23
1: Tx de-emphasis enabled (Defailt setting for desktop) TXCAM_DPA3N VGA_HDMI_CLK- 20 R250 1 2 PM@
BIF_GEN2_EN GPIO2 0= Advertises the PCI-E device as 2.5 GT/s capable at power-on 0 AT25 VGA_HDMI_TX0+ 2
1
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on MUTI GFX TX0P_DPA2P VGA_HDMI_TX0- VGA_HDMI_TX0+ 20 C224 330_0402_5% R95 R94
AR24
5.0 GT/s capability will be controlled by software DPA TX0M_DPA2N VGA_HDMI_TX0- 20
GPIO23 Reserved 0 AU26 VGA_HDMI_TX1+ 0.1U_0402_16V4Z
TX1P_DPA1P VGA_HDMI_TX1- VGA_HDMI_TX1+ 20 PM@ 1 4.7K_0402_5% 4.7K_0402_5%
GPIO21 AV25
TX1M_DPA1N VGA_HDMI_TX1- 20 U1 @ @
2
GPIO13,12,11 (config 2,1,0) : 001 AR8 AT27 VGA_HDMI_TX2+ 1 8 EC_SMB_CK2
DVPCNTL_MVP_0 TX2P_DPA0P VGA_HDMI_TX2+ 20 VDD SCLK EC_SMB_CK2 25,39
CONFIG[2] GPIO13 memory apertures AU8 AR26 VGA_HDMI_TX2- 2200P_0402_50V7K
a) If BIOS_ROM_EN = 1, then Config[2:0] defines DVPCNTL_MVP_1 TX2M_DPA0N VGA_HDMI_TX2- 20 D+ EC_SMB_DA2
CONFIG[1] GPIO12 CONFIG[3:0] AP8
DVPCNTL_0
2
D+ SDATA
7 EC_SMB_DA2 25,39
CONFIG[0] GPIO11 the ROM type. 128 MB 000 AW8 AR30 C223
D
b) If BIOS_ROM_EN = 0, then Config[2:0] defines DVPCNTL_1 TXCBP_DPB3P VGA_THERM# D
256 MB 001 AR3 AT29 1 2 3 6 VGA_THERM# 39
DVPCNTL_2 TXCBM_DPB3N D- PM@ D- ALERT#
the primary memory aperture size. 64 MB 010 AR1
MEM_ID0 DVPCLK
AU1 AV31 4 5
MEM_ID1 DVPDATA_0 TX3P_DPB2P THERM# GND
BIOS_ROM_EN GPIO22 Enable external BIOS ROM device 0 AU3
DVPDATA_1 TX3M_DPB2N
AU30
1
0: Diable, 1: Enable MEM_ID2 AW3 DPB R817
00: No audio function; 10: Audio for DisplayPort only; MEM_ID3 DVPDATA_2 ADM1032ARMZ-2REEL_MSOP8
AUD[1] HSYNC 1 AP6
DVPDATA_3 TX4P_DPB1P
AR32
AUD(0) VSYNC 01: Audio for DisplayPort and HDMI if adapter is detected; 1 AW5 AT31 PM@
DVPDATA_4 TX4M_DPB1N 4.7K_0402_5%
11: Audio for both DisplayPort and HDMI AU5
DVPDATA_5 PM@
AR6 AT33
2
DVPDATA_6 TX5P_DPB0P
GENERICC Reserved 0 AW6
DVPDATA_7 TX5M_DPB0N
AU32
H2SYNC Reserved AU6
DVPDATA_8
0 AT7 AU14 03/06 Updated by Tock +3VS_DELAY
DVPDATA_9 TXCCP_DPC3P
VIP_DEVICE_ V2SYNC AV7
DVPDATA_10 TXCCM_DPC3N
AV13
MemoryID table AN7
STRAP_EN DVPDATA_11
0 AV9
DVPDATA_12 TX0P_DPC2P
AT15
AT9 AR14 +3VS_DELAY
DVPDATA_13 TX0M_DPC2N
AR10
DVPDATA_14 DPC
AW10
DVPDATA_15 TX1P_DPC1P
AU16 Location MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3 1 2 +3VS
AU10 AV15 R816 0_0805_5%
DVPDATA_16 TX1M_DPC1N
AP10
DVPDATA_17
VRAM (R110) (R109) (R108) (R8) PM@
+3VS_DELAY +1.8VSDGPU AV11 AT17
DVPDATA_18 TX2P_DPC0P
AT11
DVPDATA_19 TX2M_DPC0N
AR16 Samsung 1 O O O
@ R119 3K_0402_5% VGA_GPIO0 R110 1 2 10K_0402_5% MEM_ID0 AR12
@ R120 3K_0402_5% VGA_GPIO1 R109 MEM_ID1 DVPDATA_20
1 @ 2 10K_0402_5% AW12 AU20 HYNIX O O O O
@ R121 3K_0402_5% VGA_GPIO2 R108 1 @ 2 10K_0402_5% MEM_ID2 AU12
DVPDATA_21
DVPDATA_22
TXCDP_DPD3P
TXCDM_DPD3N
AT19 +3VS_DELAY
@ R122 3K_0402_5% SOUT_GPIO8 R8 1 @ 10K_0402_5% MEM_ID3
2 AP12
DVPDATA_23 SI2301BDS_SOT23
06/09 DVT, soft start
for use SBIOS TX3P_DPD2P
AT21
@ R123
R124 PM@
3K_0402_5%
3K_0402_5%
SIN_GPIO9
VGA_GPIO11
+3VS_DELAY TX3M_DPD2N
AR20
+3VS_DELAY
Q1 ice
1
@ R125 3K_0402_5% VGA_GPIO12 DPD
S
AU22 1 3
D
+3VS
0.1U_0402_16V7K
@ R126 3K_0402_5% VGA_GPIO13 R1 R2 TX4P_DPD1P
AV21 2
TX4M_DPD1N
R127 PM@ 3K_0402_5% VGA_VSYNC 4.7K_0402_5% 4.7K_0402_5% I2C @ C201
CRB recommend 4.7Kohm AT23
G
2
R128 PM@ 3K_0402_5% VGA_HSYNC PM@ PM@ TX5P_DPD0P
AR22
2
VGA_LVDS_SCL TX5M_DPD0N 1
22 VGA_LVDS_SCL AK26 @
@ R129 3K_0402_5% V2SYNC VGA_LVDS_SDA SCL
22 VGA_LVDS_SDA AJ26
@ R130 3K_0402_5% H2SYNC SDA R112 150_0402_1%
2
C @ R131 3K_0402_5% ROMSE_GPIO22 3/2 ATI benny suggest AD39 VGA_CRT_R VGA_CRT_R 1 2 C
GENERAL PURPOSE I/O R VGA_CRT_R 21 PM@ @ R103
AD37
@ R132 3K_0402_5% GENERICC VGA_GPIO0 RB R113 150_0402_1% R343
AH20
VGA_GPIO1 GPIO_0 VGA_CRT_G VGA_CRT_G 10K_0402_5% 100K_0402_5%
10/22 Add by Vivian AH18
GPIO_1 G
AE36
VGA_CRT_G 21
1 2
@ R133 3K_0402_5% VGA_AC_DET_R VGA_GPIO2 AN16 AD35 PM@ @
1
EC_SMB_DA2 R97 @ GPIO_2 GB
1 2 0_0402_5% SMB_DA AH23 R114 150_0402_1%
EC_SMB_CK2 R96 GPIO_3_SMBDATA
1 @ 2 0_0402_5% SMB_CLK AJ23 AF37 VGA_CRT_B VGA_CRT_B 1 2
@ R20 GPIO_4_SMBCLK B VGA_CRT_B 21
2 1 10K_0402_5% VGA_ENBKL
39 VGA_AC_DET
VGA_AC_DET 1 @ 2 VGA_AC_DET_R AH17 AE38 PM@
1
R27 0_0402_5% GPIO_5_AC_BATT DAC1 BB D
58 VDDC_VID0 AJ17
VGA_ENBKL GPIO_6 VGA_HSYNC
22 VGA_ENBKL AK17 AC36 43,48,56,58 VGA_ON 2 R111 100K_0402_5%
1 2 Q2
SOUT_GPIO8 GPIO_7_BLON HSYNC VGA_VSYNC VGA_HSYNC 21 @ G
Pull Low at LVDS side SIN_GPIO9
AJ13
GPIO_8_ROMSO VSYNC
AC38
VGA_VSYNC 21 C241
1
SSM3K7002FU_SC70-3
AH15 S
3
GPIO_9_ROMSI R40 PM@ @
AJ16
VGA_GPIO11 GPIO_10_ROMSCK 0.1U_0402_16V4Z
AK16 AB34 1 2
+3VS_DELAY VGA_GPIO12 GPIO_11 RSET 499_0402_1% L15 @ 2
VGA_GPIO13
AL16
GPIO_12 AVDD
70mA AVDD 0.1U_0402_16V4Z
AM16 AD34 AVDD 2 1 +1.8VSDGPU
VGA_THERM# GPIO_13 AVDD BLM18PG121SN1D_0603
1 2 AM14 AE34 1 1 1
GPIO_14_HPD2 AVSSQ
C30
C85
C29
R93 10K_0402_5% GPU_VID0 AM13 50mA PM@
56 GPU_VID0 GPIO_15_PWRCNTL_0
1 2 Check AK14 AC33 VDD1DI VDD1DI
@ R92 10K_0402_5% VGA_THERM# GPIO_16_SSIN VDD1DI
AG30 AC34
item 24, add test point for GPIO_17_THERMAL_INT VSS1DI PM@ 2 PM@ 2 PM@ 2
AN14
VBBP Controller 05/13 GPIO_18_HPD3 1U_0402_6.3V4Z 10U_0603_6.3V6M
AM17
PEG_CLKREQ# GPU_VID1 GPIO_19_CTF
1 2 AL13 AC30
R102 10K_0402_5%
56 GPU_VID1
16 VGA_GPIO21
VGA_GPIO21 AJ14
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
R2
R2B
AC31 L16 PWR Sequence +3VS_DELAY
ROMSE_GPIO22 AK13 VDD1DI 0.1U_0402_16V4Z 2 1 +1.8VSDGPU
PEG_CLKREQ# GPIO_22_ROMCSB BLM18PG121SN1D_0603
25 PEG_CLKREQ# AN13 AD30 1 1 1
GPIO24_TRSTB GPIO_23_CLKREQB G2
C89
C245
M96 can not support AM23 AD31 PM@
GPIO25_TDI JTAG_TRSTB G2B
C252
AN23
JTAG_TDI
VGA_CORE (VDDC)
GPIO26_TCK AK23 AF30
100P_0402_50V8J C227 GPU_VID1 GPIO27_TMS JTAG_TCK B2 PM@ 2 PM@ 2 PM@ 2
1 2 AL24
JTAG_TMS B2B
AF31 +1.8VS
2
GPIO28_TDO AM24 1U_0402_6.3V4Z 10U_0603_6.3V6M
R142 JTAG_TDO
@ AJ19
GENERICA
10/31 Add 10K_0402_5% AK19
GENERICB C
AC32
XTALIN XTALOUT @ GENERICC AJ20 AD32 VDD2DI L17 0_0603_5% +1.8VSDGPU
GENERICC Y PM@
AK20 AF32
1
GENERICD COMP
AJ24
R104 1M_0603_5% GENERICE_HPD4 DAC2
AH26
PM@ GENERICF H2SYNC
B 03/06 Add by Tock AH24
GENERICG H2SYNC
AD29
V2SYNC B
AC29
V2SYNC
1
Y1 VGA_HDMI_HPD AK24 40mA
20 VGA_HDMI_HPD HPD1
R98 4 3 AG31 VDD2DI VDD2DI
@ GND OUT VDD2DI A2VDD L18 PM@ 0_0603_5%
Change R1211 part number from SD034499080 to SD034249080 VSS2DI
AG32 +3VS_DELAY
1 2
75_0402_1% IN GND C229 +1.8VSDGPU 1 PM@ 2 135mA
2
27MHz_16PF_6P27000126 R32 499_0402_1% AG33 A2VDD A2VDD
C225 PM@ 18P_0402_50V8J A2VDD
1 PM@ 2 1mA
PM@ R19 249_0402_1% AD33 A2VDDQ A2VDDQ
18P_0402_50V8J VGA_VREF A2VDDQ
1 2 AH13
PM@ C54 0.1U_0402_16V4Z VREFG
AF33
+1.8VSDGPU PM@ A2VSSQ L19
120mA A2VDDQ 2 1 +1.8VSDGPU
BLM18PG121SN1D_0603 AA29 1 2 BLM18PG121SN1D_0603
+3VS_DELAY For ATI debug 2 1 0.1U_0402_16V4Z DPLL_PVDD R2SET R38 715_0402_1% PM@
PM@ L20 1 1 1 PM@ 1
C10
C41
C13
C202
1 2 GPIO24_TRSTB DDC/AUX AM26 VGA_DDC_CLK 0.1U_0402_16V4Z
@ R134 10K_0402_5% PLL/CLOCK DDC1CLK VGA_DDC_DATA
DDC1DATA
AN26 CRT
1 2 GPIO25_TDI PM@ 2 PM@ 2 PM@ 2 AM32 PM@ 2
@ R135 10K_0402_5% 10U_0603_6.3V6M 1U_0402_6.3V4Z DPLL_PVDD
AN32 AM27
GPIO26_TCK +1.1VS DPLL_PVSS AUX1P
1 2 AL27
@ R136 10K_0402_5% BLM18PG121SN1D_0603 AUX1N
GPIO27_TMS 0.1U_0402_16V4Z
300mA
DPLL_VDDC AN31 VGA_HDMI_SCL
1 2 2 1 AM19
@ R137 10K_0402_5% PM@ L21 DPLL_VDDC DDC2CLK VGA_HDMI_SDA
1 1 1 DDC2DATA
AL19 HDMI
C9
GPIO28_TDO
C33
C12
1 2
@ R138 10K_0402_5% XTALIN AV33 AN20
XTALOUT XTALIN AUX2P
AU34 AM20
PM@ 2 PM@ 2 PM@ 2 XTALOUT AUX2N
1 2GPIO24_TRSTB 10U_0603_6.3V6M 1U_0402_6.3V4Z AL30
@ R248 10K_0402_5% DDCCLK_AUX3P
AM30
DDCDATA_AUX3N +3VS_DELAY +3VS_DELAY
AL29
D+ DDCCLK_AUX4P
AF29 AM29
GPIO26_TCK D- DPLUS THERMAL DDCDATA_AUX4N
1 2 CLK_VGA_27M 23 AG29
1
1
@ R252 10K_0402_5% DMINUS
+1.8VSDGPU BLM18PG121SN1D_0603 DDCCLK_AUX5P
AN21
R10 R9 R101 R100
4/24 ATI suggest
A
+3VS_DELAY 20mA DDCDATA_AUX5N
AM21 A
AK32 2.2K_0402_5% 2.2K_0402_5%
1U_0402_6.3V4Z TSVDD TS_FDO 10K_0402_5% 10K_0402_5% PM@ PM@
15 TESTEN 1 2 2 1 AJ32 AJ30
@ R251 PM@ L22 TSVDD DDC6CLK PM@ PM@
1 1 1 AJ33 AJ31
2
2
TSVSS DDC6DATA
C21
C47
10K_0402_5% VGA_DDC_CLK VGA_HDMI_SCL
C253
VGA_DDC_CLK 21 VGA_HDMI_SCL 20
AK30 VGA_DDC_DATA VGA_HDMI_SDA
NC_DDCCLK_AUX7P VGA_DDC_DATA 21 VGA_HDMI_SDA 20
AK29
PM@ 2 PM@ 2 PM@ 2 NC_DDCDATA_AUX7N
ATI Option 2 debug 10U_0603_6.3V6M 0.1U_0402_16V4Z
item 15, Add @ M96@ add L31 05/06
4/2 Add by Vivian C814
Rual Change to M96@!
216-0729042-00 A13 M96 BGA 962P 030
Security Classification Compal Secret Data Compal Electronics, Inc.
100P_0402_50V8J GPU_VID0 PM@ 2009/02/24 2010/02/24 Title
2 1 Issued Date Deciphered Date
DVT Rual: Change this power to +1.0S M96 PCIE,LVDS,GPIO,CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 14 of 61
5 4 3 2 1
5 4 3 2 1
U4C U4D
MDB[0..63]
MDA[0..63] 19 MDB[0..63]
18 MDA[0..63]
MDA0 C37 G24 MAA0 MAA[0..13] MDB0 C5 P8 MAB0
DQA_0 MAA_0 MAA[0..13] 18 DQB_0 MAB_0
D MDA1 C35 J23 MAA1 MDB1 C3 T9 MAB1 D
DQA_1 MAA_1 DQB_1 MAB_1
MEMORY INTERFACE A
MEMORY INTERFACE B
MDA2 A35 H24 MAA2 MDB2 E3 P9 MAB2
MDA3 DQA_2 MAA_2 MAA3 A_BA[0..2] MDB3 DQB_2 MAB_2 MAB3
E34 DQA_3 MAA_3 J24 A_BA[0..2] 18 E1 DQB_3 MAB_3 N7
MDA4 G32 H26 MAA4 MDB4 F1 N8 MAB4
MDA5 DQA_4 MAA_4 MAA5 MDB5 DQB_4 MAB_4 MAB5
D33 DQA_5 MAA_5 J26 F3 DQB_5 MAB_5 N9
MDA6 F32 H21 MAA6 DQMA#[0..7] MDB6 F5 U9 MAB6
DQA_6 MAA_6 DQMA#[0..7] 18 DQB_6 MAB_6
MDA7 E32 G21 MAA7 MDB7 G4 U8 MAB7
MDA8 DQA_7 MAA_7 MAA8 MDB8 DQB_7 MAB_7 MAB8
D31 DQA_8 MAA_8 H19 H5 DQB_8 MAB_8 Y9
MDA9 F30 H20 MAA9 QSA[0..7] MDB9 H6 W9 MAB9
DQA_9 MAA_9 QSA[0..7] 18 DQB_9 MAB_9
MDA10 C30 L13 MAA10 MDB10 J4 AC8 MAB10
MDA11 DQA_10 MAA_10 MAA11 MDB11 DQB_10 MAB_10 MAB11
A30 DQA_11 MAA_11 G16 K6 DQB_11 MAB_11 AC9
MDA12 F28 J16 MAA12 QSA#[0..7] MDB12 K5 AA7 MAB12
DQA_12 MAA_12 QSA#[0..7] 18 DQB_12 MAB_12
MDA13 C28 H16 A_BA2 MDB13 L4 AA8 B_BA2
MDA14 DQA_13 MAA_13/BA2 A_BA0 MDB14 DQB_13 MAB_13/BA2 B_BA0
A28 DQA_14 MAA_14/BA0 J17 M6 DQB_14 MAB_14/BA0 Y8
MDA15 E28 H17 A_BA1 MAB[0..13] MDB15 M1 AA9 B_BA1
DQA_15 MAA_15/BA1 MAB[0..13] 19 DQB_15 MAB_15/BA1
MDA16 D27 MDB16 M3
MDA17 DQA_16 DQMA#0 MDB17 DQB_16 DQMB#0
F26 DQA_17 DQMA_0 A32 M5 DQB_17 DQMB_0 H3
MDA18 C26 C32 DQMA#1 B_BA[0..2] MDB18 N4 H1 DQMB#1
DQA_18 DQMA_1 B_BA[0..2] 19 DQB_18 DQMB_1
MDA19 A26 D23 DQMA#2 MDB19 P6 T3 DQMB#2
MDA20 DQA_19 DQMA_2 DQMA#3 MDB20 DQB_19 DQMB_2 DQMB#3
F24 DQA_20 DQMA_3 E22 P5 DQB_20 DQMB_3 T5
MDA21 C24 C14 DQMA#4 DQMB#[0..7] MDB21 R4 AE4 DQMB#4
DQA_21 DQMA_4 DQMB#[0..7] 19 DQB_21 DQMB_4
MDA22 A24 A14 DQMA#5 MDB22 T6 AF5 DQMB#5
MDA23 DQA_22 DQMA_5 DQMA#6 MDB23 DQB_22 DQMB_5 DQMB#6
E24 DQA_23 DQMA_6 E10 T1 DQB_23 DQMB_6 AK6
MDA24 C22 D9 DQMA#7 QSB[0..7] MDB24 U4 AK5 DQMB#7
+1.5VS_VRAM DQA_24 DQMA_7 QSB[0..7] 19 DQB_24 DQMB_7
MDA25 A22 MDB25 V6
MDA26 DQA_25 QSA0 MDB26 DQB_25 QSB0
F22 DQA_26 QSA_0/RDQSA_0 C34 V1 DQB_26 QSB_0/RDQSB_0 F6
MDA27 D21 D29 QSA1 QSB#[0..7] MDB27 V3 K3 QSB1
DQA_27 QSA_1/RDQSA_1 QSB#[0..7] 19 DQB_27 QSB_1/RDQSB_1
MDA28 A20 D25 QSA2 MDB28 Y6 P3 QSB2
DQA_28 QSA_2/RDQSA_2 DQB_28 QSB_2/RDQSB_2
2
MDA29 F20 E20 QSA3 MDB29 Y1 V5 QSB3
C R65 MDA30 DQA_29 QSA_3/RDQSA_3 QSA4 +1.5VS_VRAM MDB30 DQB_29 QSB_3/RDQSB_3 QSB4 C
D19 DQA_30 QSA_4/RDQSA_4 E16 Y3 DQB_30 QSB_4/RDQSB_4 AB5
40.2_0402_1% MDA31 E18 E12 QSA5 MDB31 Y5 AH1 QSB5
PM@ MDA32 DQA_31 QSA_5/RDQSA_5 QSA6 MDB32 DQB_31 QSB_5/RDQSB_5 QSB6
C18 DQA_32 QSA_6/RDQSA_6 J10 AA4 DQB_32 QSB_6/RDQSB_6 AJ9
MDA33 A18 D7 QSA7 MDB33 AB6 AM5 QSB7
1
DQA_33 QSA_7/RDQSA_7 DQB_33 QSB_7/RDQSB_7
2
MVREFDA MDA34 F18 MDB34 AB1
MDA35 DQA_34 QSA#0 R42 MDB35 DQB_34 QSB#0
D17 DQA_35 QSA_0B/WDQSA_0 A34 AB3 DQB_35 QSB_0B/WDQSB_0 G7
1
1 MDA36 A16 E30 QSA#1 40.2_0402_1% MDB36 AD6 K1 QSB#1
R64 C140 MDA37 DQA_36 QSA_1B/WDQSA_1 QSA#2 PM@ MDB37 DQB_36 QSB_1B/WDQSB_1 QSB#2
F16 DQA_37 QSA_2B/WDQSA_2 E26 AD1 DQB_37 QSB_2B/WDQSB_2 P1
MDA38 D15 C20 QSA#3 MDB38 AD3 W4 QSB#3
1
100_0402_1% 0.1U_0402_16V4Z MDA39 DQA_38 QSA_3B/WDQSA_3 QSA#4 MVREFDB MDB39 DQB_38 QSB_3B/WDQSB_3 QSB#4
E14 DQA_39 QSA_4B/WDQSA_4 C16 AD5 DQB_39 QSB_4B/WDQSB_4 AC4
PM@ 2 PM@ MDA40 QSA#5 MDB40 QSB#5
F14 C12 AF1 AH3
2
DQA_40 QSA_5B/WDQSA_5 DQB_40 QSB_5B/WDQSB_5
1
MDA41 D13 J11 QSA#6 change to 40.2 for Madison 1 MDB41 AF3 AJ8 QSB#6
MDA42 DQA_41 QSA_6B/WDQSA_6 QSA#7 MDB42 DQB_41 QSB_6B/WDQSB_6 QSB#7
F12 DQA_42 QSA_7B/WDQSA_7 F8 AF6 DQB_42 QSB_7B/WDQSB_7 AM3
MDA43 A12 R39 C103 MDB43 AG4
MDA44 DQA_43 ODTA0 100_0402_1% 0.1U_0402_16V4Z MDB44 DQB_43 ODTB0
D11 DQA_44 ODTA0 J21 ODTA0 18 AH5 DQB_44 ODTB0 T7 ODTB0 19
MDA45 ODTA1 PM@ 2 PM@ MDB45 ODTB1
F10 G19 ODTA1 18 AH6 W7 ODTB1 19
2
+1.5VS_VRAM MDA46 DQA_45 ODTA1 MDB46 DQB_45 ODTB1
A10 DQA_46 AJ4 DQB_46
MDA47 C10 H27 CLKA0 MDB47 AK3 L9 CLKB0
DQA_47 CLKA0 CLKA0 18 DQB_47 CLKB0 CLKB0 19
MDA48 G13 G27 CLKA0# MDB48 AF8 L8 CLKB0#
DQA_48 CLKA0B CLKA0# 18 DQB_48 CLKB0B CLKB0# 19
MDA49 H13 MDB49 AF9
DQA_49 DQB_49
2
MDA50 J13 J14 CLKA1 MDB50 AG8 AD8 CLKB1
DQA_50 CLKA1 CLKA1 18 +1.5VS_VRAM DQB_50 CLKB1 CLKB1 19
R50 MDA51 H11 H14 CLKA1# MDB51 AG7 AD7 CLKB1#
DQA_51 CLKA1B CLKA1# 18 DQB_51 CLKB1B CLKB1# 19
40.2_0402_1% MDA52 G10 MDB52 AK9
PM@ MDA53 DQA_52 RASA0# MDB53 DQB_52 RASB0#
G8 DQA_53 RASA0B K23 RASA0# 18 AL7 DQB_53 RASB0B T10 RASB0# 19
MDA54 K9 K19 RASA1# MDB54 AM8 Y10 RASB1#
RASA1# 18 RASB1# 19
1
DQA_54 RASA1B DQB_54 RASB1B
2
MVREFSA MDA55 K10 MDB55 AM7
MDA56 DQA_55 CASA0# R35 MDB56 DQB_55 CASB0#
G9 DQA_56 CASA0B K20 CASA0# 18 AK1 DQB_56 CASB0B W10 CASB0# 19
1
1 MDA57 A8 K17 CASA1# 40.2_0402_1% MDB57 AL4 AA10 CASB1#
DQA_57 CASA1B CASA1# 18 DQB_57 CASB1B CASB1# 19
R45 C129 MDA58 C8 PM@ MDB58 AM6
B MDA59 DQA_58 CSA0#_0 MDB59 DQB_58 CSB0#_0 B
E8 K24 CSA0#_0 18 AM1 P10 CSB0#_0 19
1
100_0402_1% 0.1U_0402_16V4Z MDA60 DQA_59 CSA0B_0 MVREFSB MDB60 DQB_59 CSB0B_0
A6 DQA_60 CSA0B_1 K27 AN4 DQB_60 CSB0B_1 L10
PM@ 2 PM@ MDA61 MDB61
C6 AP3
2
DQA_61 DQB_61
1
MDA62 E6 M13 CSA1#_0 1 MDB62 AP1 AD10 CSB1#_0
DQA_62 CSA1B_0 CSA1#_0 18 DQB_62 CSB1B_0 CSB1#_0 19
MDA63 A5 K16 R36 C84 MDB63 AP5 AC10
DQA_63 CSA1B_1 DQB_63 CSB1B_1
MVREFDA L18 K21 CKEA0 100_0402_1% 0.1U_0402_16V4Z U10 CKEB0
MVREFDA CKEA0 CKEA0 18 2 PM@ CKEB0 CKEB0 19
MVREFSA L20 J20 CKEA1 PM@ MVREFDB Y12 AA11 CKEB1
CKEA1 18 CKEB1 19
2
MVREFSA CKEA1 MVREFSB AA12 MVREFDB CKEB1
R48 MVREFSB
+1.5VS_VRAM 1 MAD@ 2 243_0402_1% L27 NC_MEM_CALRN0 WEA0B K26 WEA0#
WEA0# 18 WEB0B N10 WEB0#
WEB0# 19
R58 1 MAD@ 2 243_0402_1% N12 L15 WEA1# AB11 WEB1#
NC_MEM_CALRN1 WEA1B WEA1# 18 WEB1B WEB1# 19
R31 1 MAD@ 2 243_0402_1% AG12 NC_MEM_CALRN2 R271 1 MAD@ 2+VGASENSE change at 1112 pvt
RSVD#1 AF28 +VGASENSE 56
R54 1 PM@ 2 243_0402_1% M12 AG28 0_0402_5% TESTEN AD28
MEM_CALRP1 RSVD#2 14 TESTEN TESTEN
R46 1 2 243_0402_1% M27 AL31
NC_MEM_CALRP0 RSVD#3
2
R26 1 MAD@ 2 243_0402_1% AH12 item 20, Add R271 add M97@ TEST_MCLK AK10
MAD@ NC_MEM_CALRP2 MAA13 Need doube check! R41 TEST_YCLK CLKTESTA R23 51_0402_1%
RSVD#5 H23 AL10 CLKTESTB DRAM_RST AH11 MEM_RST 18,19
RSVD#6 J19
1K_0402_5%
item 01,Bom structure from M97@ to mount 05/06 T8 MAB13 PM@ 1 1
1
RSVD#9
1
W8 C254 C255
RSVD#11 @ @ C38 R17 R13
item 01,Bom structure to MAD@ 0827
0.1U_0402_16V4Z 0.1U_0402_16V4Z PM@
2 2 216-0729042-00 A13 M96 BGA 962P 030 10K_0402_5% 4.7K_0402_5%
216-0729042-00 A13 M96 BGA 962P 030 PM@ 68p_0402_50V7M @
2
PM@
R21 R18
Note: 51.1_0402_1% 51.1_0402_1%
A
@ @ +1.5VS_VRAM A
route 50ohms single-ended/100ohms diff
and keep short
REF137-03 suggest
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/24 Deciphered Date 2010/02/24 Title
M96 Memory
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 15 of 61
5 4 3 2 1
5 4 3 2 1
U4F U4E
MEM I/O 220 Ohm@100Mhz,3A
PCIE L23
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
4A 400mA PCIE_VDDR 1U_0402_6.3V4Z 10U_0805_6.3V6M 0.1U_0402_16V4Z 2
AB39 PCIE_VSS#1 GND#1 A3 +1.5VS_VRAM AC7 VDDR1#1 PCIE_VDDR#1 AA31 1 +1.8VSDGPU
E39 A37 AD11 AA32 KC FBM-L11-201209-221LMAT_0805
PCIE_VSS#2 GND#2 VDDR1#2 PCIE_VDDR#2
F34 PCIE_VSS#3 GND#3 AA16 1 1 1 1 1 1 1 AF7 VDDR1#3 PCIE_VDDR#3 AA33 1 1 1 1 1 1 PM@ 12/23 Change C20 from 220u to 330u
C76
C78
C96
C153
C154
C142
C148
C106
C257
C107
C246
C258
C256
F39 PCIE_VSS#4 GND#4 AA18 AG10 VDDR1#4 PCIE_VDDR#4 AA34
G33 PCIE_VSS#5 GND#5 AA2 AJ7 VDDR1#5 PCIE_VDDR#5 V28 1/19 Change C20 from 330u to 470u(SGA00001U00)
G34 AA21 AK8 W29 PM@
PCIE_VSS#6 GND#6 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 VDDR1#6 PCIE_VDDR#6 2 2 2 2 2 2
H31 PCIE_VSS#7 GND#7 AA23 AL9 VDDR1#7 PCIE_VDDR#7 W30
H34 AA26 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z G11 Y31 PM@ PM@ PM@ PM@ PM@
PCIE_VSS#8 GND#8 VDDR1#8 PCIE_VDDR#8 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z
H39 PCIE_VSS#9 GND#9 AA28 G14 VDDR1#9 +VGA_CORE
J31 PCIE_VSS#10 GND#10 AA6 G17 VDDR1#10 2A 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
J34 PCIE_VSS#11 GND#11 AB12 G20 VDDR1#11 PCIE_VDDC#1 G30 +1.1VS
K31 PCIE_VSS#12 GND#12 AB15 G23 VDDR1#12 PCIE_VDDC#2 G31
D K34 AB17 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z G26 H29 1 D
PCIE_VSS#13 GND#13 VDDR1#13 PCIE_VDDC#3 item 14, Add @ M96@ add R950, R675 05/06
K39 PCIE_VSS#14 GND#14 AB20 G29 VDDR1#14 PCIE_VDDC#4 H30 1 1 1 1 1 1 1 1
Rual: Del R650 and R675! C2 +
C265
C266
C123
C110
C191
C267
C268
C269
L31 PCIE_VSS#15 GND#15 AB22 1 1 1 1 1 1 1 1 1 H10 VDDR1#15 PCIE_VDDC#5 J29
DVT, change to +1.1VS 470U_D2E_2.5VM_R9
C46
C141
C152
C259
C260
C261
C262
C263
C264
L34 PCIE_VSS#16 GND#16 AB24 J7 VDDR1#16 PCIE_VDDC#6 J30
M34 AB27 J9 L28 PM@
PCIE_VSS#17 GND#17 VDDR1#17 PCIE_VDDC#7 PM@ 2 2 2 2 2 2 2 2 PM@ 2
M39 PCIE_VSS#18 GND#18 AC11 K11 VDDR1#18 PCIE_VDDC#8 M28
PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ PM@ PM@ PM@ PM@ PM@
N31 PCIE_VSS#19 GND#19 AC13 K13 VDDR1#19 PCIE_VDDC#9 N28
N34 AC16 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z K8 R28 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0805_6.3V6M 0.1U_0402_16V4Z
PCIE_VSS#20 GND#20 VDDR1#20 PCIE_VDDC#10
P31 PCIE_VSS#21 GND#21 AC18 L12 VDDR1#21 PCIE_VDDC#11 T28
P34 PCIE_VSS#22 GND#22 AC2 L16 VDDR1#22 PCIE_VDDC#12 U28
P39 PCIE_VSS#23 GND#23 AC21 L21 VDDR1#23
R34 AC23 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z L23
PCIE_VSS#24 GND#24 VDDR1#24 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
T31 PCIE_VSS#25 GND#25 AC26 L26 VDDR1#25 VDDC#1 AA15 +VGA_CORE
T34 AC28 1 1 1 1 1 1 1 1 1 L7 CORE AA17
PCIE_VSS#26 GND#26 VDDR1#26 VDDC#2
C57
C210
C211
C212
C205
C204
C138
C131
C156
T39 PCIE_VSS#27 GND#27 AC6 M11 VDDR1#27 VDDC#3 AA20 1 1 1 1 1 1 1 1
C91
C90
C113
C120
C119
C112
C121
C114
U31 PCIE_VSS#28 GND#28 AD15 N11 VDDR1#28 VDDC#4 AA22
U34 PCIE_VSS#29 GND#29 AD17 P7 VDDR1#29 VDDC#5 AA24
2 2 2 2 2 2 2 2 2
V34 PCIE_VSS#30 GND#30 AD20 R11 VDDR1#30 VDDC#6 AA27
V39 AD22 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ U11 AB13 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2
PCIE_VSS#31 GND#31 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR1#31 VDDC#7 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
W31 PCIE_VSS#32 GND#32 AD24 U7 VDDR1#32 VDDC#8 AB16
W34 PCIE_VSS#33 GND#33 AD27 Y11 VDDR1#33 VDDC#9 AB18
Y34 PCIE_VSS#34 GND#34 AD9 Y7 VDDR1#34 VDDC#10 AB21
Y39 AE2 L24 AB23
PCIE_VSS#35 GND#35 1U_0402_6.3V4Z 1U_0402_6.3V4Z VDDC#11
GND#36 AE6 +1.8VSDGPU 2 1 VDDC#12 AB26
AF10 BLM18PG121SN1D_0603 AB28 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
GND#37 PM@ VDDC#13
GND#38 AF16 1 1 1 1 1 VDDC#14 AC12
LEVEL
C15
C49
C34
C270
C271
GND#39 AF18 150mA TRANSLATION VDDC#15 AC15 1 1 1 1 1 1 1 1 1
C99
C93
C98
C92
C115
C102
C101
C100
C125
GND GND#40 AF21 VDDC#16 AC17
POWER
AG17 VDD_CT AF26 AC20
GND#41 item 21, Add R272 add M97@ PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 VDD_CT#1 VDDC#17
F15 GND#101 GND#42 AG2 AF27 VDD_CT#2 VDDC#18 AC22
F17 AG20 Need double check! AG26 AC24 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2
GND#102 GND#43 10U_0805_6.3V6M 0.1U_0402_16V4Z 1U_0402_6.3V4Z VDD_CT#3 VDDC#19 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
F19 GND#103 GND#44 AG22 AG27 VDD_CT#4 VDDC#20 AC27
F21 AG6 +VGAVSSSENSE 56 AD13
GND#104 GND#45 1U_0402_6.3V4Z 1U_0402_6.3V4Z VDDC#21
F23 GND#105 GND#46 AG9 +3VS_DELAY VDDC#22 AD16
2
I/O
C
F25 GND#106 GND#47 AH21 1 1 1 1 100mA VDDC#23 AD18 C
AH29 +VGAVSSSENSE R272 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
C14
C48
C272
C273
F27 GND#107 GND#48 AF23 VDDR3#1 VDDC#24 AD21
F29 GND#108 GND#49 AJ10 0_0402_5% AF24 VDDR3#2 VDDC#25 AD23
F31 GND#109 GND#50 AJ11 M96@ AG23 VDDR3#3 VDDC#26 AD26 1 1 1 1 1 1 1 1 1 1
PM@ 2 PM@ 2 PM@ 2 PM@ 2
C97
C71
C70
C75
C74
C73
C65
C64
C63
C62
F33 AJ2 AG24 AF17
1
GND#110 GND#51 VDDR3#4 VDDC#27
F7 GND#111 GND#52 AJ28 VDDC#28 AF20
F9 AJ6 10U_0805_6.3V6M 1U_0402_6.3V4Z 300mA AF22
GND#112 GND#53 VDDR4_5 VDDC#29 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2
G2 GND#113 GND#54 AK11 AF13 VDDR5#1 VDDC#30 AG16
G6 AK31 L25 AF15 AG18 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
GND#114 GND#55 1U_0402_6.3V4Z VDDR5#2 VDDC#31
H9 GND#115 GND#56 AK7 +1.8VSDGPU 1 2 AG13 VDDR5#3 VDDC#32 AG21
J2 AL11 MBK1608121YZF_0603 1 1 1 AG15 AH22
GND#116 GND#57 120Ohm@100MHz, 600mA C56 VDDR5#4 VDDC#33
C67
C59
J27 GND#117 GND#58 AL14 VDDC#34 M16
J6 AL17 M18 del C231,C232,C233,C234
GND#118 GND#59 PM@ VDDC#35
J8 AL2 @ VDDR4_5 AD12 M23 09/08
GND#119 GND#60 2 PM@ 2 PM@ 2 VDDR4#1 VDDC#36
K14 GND#120 GND#61 AL20 AF11 VDDR4#2 VDDC#37 M26
K7 AL21 10U_0805_6.3V6M 0.1U_0402_16V4Z AF12 N15 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
GND#121 GND#62 VDDR4#3 VDDC#38
L11 GND#122 GND#63 AL23 AG11 VDDR4#4 VDDC#39 N17
L17 GND#123 GND#64 AL26 VDDC#40 N20 1 1 1 1 1 1 1 1 1 1
C8
C88
C40
C274
C234
C233
C231
C232
C275
C276
L2 GND#124 GND#65 AL32 VDDC#41 N22
L22 GND#125 GND#66 AL6 VDDC#42 N24
L24 AL8 1U_0402_6.3V4Z MEM CLK N27
GND#126 GND#67 VDDC#43 2 PM@ 2 2 PM@ 2 2 PM@ 2 PM@ 2 PM@ 2 2 PM@ 2
L6 GND#127 GND#68 AM11 +1.5VS_VRAM R22 M96@ 0_0603_5%
1 1 M20 VDDRHA VDDC#44 R13 PM@ PM@ PM@ PM@
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
C60
C132
M17 GND#128 GND#69 AM31 M21 VSSRHA VDDC#45 R16
M22 AM9 item 13, Add @ M96@ add R22, C132, C60 05/06 R18 +VGA_CORE
GND#129 GND#70 VDDC#46
M24 GND#130 GND#71 AN11 VDDC#47 R21
N16 AN2 M96@ 2 M96@ 2 V12 R23
GND#131 GND#72 VDDRHB VDDC#48
KC FBM-L11-201209-221LMAT_0805
N18 AN30 0.1U_0402_16V4Z U12 R26 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z +VGA_VDDCI 2 1
GND#132 GND#73 VSSRHB VDDC#49
N2 GND#133 GND#74 AN6 VDDC#50 T15
N21 AN8 NC for Madison T17 PM@ L30
GND#134 GND#75 VDDC#51
N23 GND#135 GND#76 AP11 VDDC#52 T20 1 1 1 1 1 1 1 1
change PN to SM01000CE00
C277
C278
C279
C280
C281
C283
C284
C137
N26 GND#136 GND#77 AP7 60mA PLL VDDC#53 T22
PVT 1117
N6 GND#137 GND#78 AP9 VDDC#54 T24
R15 AR5 PCIE_PVDD AB37 T27
GND#138 GND#79 PCIE_PVDD VDDC#55 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2 PM@ 2
R17 GND#139 GND#80 AW34
MPV18
500mA VDDC#56 U16
R2 GND#140 GND#81 B11 H7 NC_MPV18#1 VDDC#57 U18
B R20 B13 H8 U21 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z B
GND#141 GND#82 NC_MPV18#2 VDDC#58
R22 GND#142 GND#83 B15 VDDC#59 U23
R24 GND#143 GND#84 B17
SPV18
75mA VDDC#60 U26
10U_0805_6.3V6M 10U_0805_6.3V6M
R27 GND#144 GND#85 B19 AM10 NC_SPV18 VDDC#61 V15
R6 GND#145 GND#86 B21
SPV10
120mA VDDC#62 V17 4A
T11 GND#146 GND#87 B23 AN9 SPV10 VDDC#63 V20 1 1 1
C286
C195
C196
T13 GND#147 GND#88 B25 VDDC#64 V22
T16
T18
GND#148 GND#89 B27
B29
AN10 SPVSS VDDC#65 V24
V27
item 22, Add JP21,JP22 add M97@
GND#149 GND#90 VDDC#66 PM@ 2 PM@ 2 PM@ 2
T21 GND#150 GND#91 B31 VDDC#67 Y16 Rual: Del JP21 and JP22! Connect
T23 B33 Y18
T26
GND#151
GND#152
GND#92
GND#93 B7
VDDC#68
VDDC#69 Y21 VDDCI to +VGA_Core! 10U_0805_6.3V6M
U15 B9 BACK BIAS Y23
GND#153 GND#94 VDDC#70
U17 GND#154 GND#95 C1 VDDC#71 Y26
item 19, Add L32,L33,L34 add M97@
U2 GND#155 GND#96 C39
need double check!
+BBP AA13 BBP#1 VDDC#72 Y28 CRB recommend 470 Ohm, 1A
U20 GND#156 GND#97 E35 1 Y13 BBP#2 VDDC#73 AH27
del L32 L33 L34 0512
C171
U22 GND#157 GND#98 E5 VDDC#74 AH28
U24 F11 item 17, Add @ M97@
GND#158 GND#99 L26 L28
U27 GND#159 GND#100 F13 M15
U6 +BBP PM@ 2 ISOLATED VDDCI#1 N13 2 1 0.1U_0402_16V4Z PCIE_PVDD 2 1 1U_0402_6.3V4Z 0.1U_0402_16V4Z MPV18
GND#160 +1.8VSDGPU +1.8VSDGPU
V11 CORE I/O VDDCI#2 R12 BLM18PG121SN1D_0603 2 2 2 2 1 1 1 1
GND#161 MAD@ L99 VDDCI#3 PM@ MAD@
C242
C243
C244
C287
C155
C160
C288
C289
V16 GND#162 VDDCI#4 T12
V18 +VGA_CORE 2 1 0.1U_0402_16V4Z KC FBM-L11-201209-221LMAT_0805
GND#163 BLM18PG121SN1D_0603
V21 GND#164
V23 +1.8VSDGPU PM@ 1 PM@ 1 PM@ 1 MAD@ 1 MAD@ 2 MAD@ 2 MAD@ 2 MAD@ 2
GND#165 216-0729042-00 A13 M96 BGA 962P 030 10U_0603_6.3V6M 1U_0402_6.3V4Z 10U_0603_6.3V6M 0.1U_0402_16V4Z 1U_0402_6.3V4Z
V26 GND#166
W2 +VGA_CORE L98 PM@
GND#167
1
W6 2 1 1 item 18, Add @ M97@
GND#168 BLM18PG121SN1D_0603 C1420 R1240 change to 1.1VS L6 L27
Y15 GND#169
Y17 GND#170 +1.1VS 2 1PM@ 0.1U_0402_16V4Z SPV10 +1.8VSDGPU 2 1 0.1U_0402_16V4Z SPV18
Y20 @ Q96 1U_0402_6.3V4Z 10_0402_5% KC FBM-L11-201209-221LMAT_0805 BLM18PG121SN1D_0603 1 1 2
GND#171 Q95 @ 2 @ MAD@
C36
C27
C290
Y22 A39 2 2 2
2
GND#172 VSS_MECH#1 +BBP_R item 16, Add @ M96@ add L7 05/06
C19
C37
C26
S
Y24 AW1 1 3
D
GND#173 VSS_MECH#2 Rual: L7, change power plane to VGA_Core!
S
Y27 GND#174 VSS_MECH#3 AW39 3 1
U13 SI2301BDS_SOT23 MAD@ 2 MAD@ 2 MAD@ 1
A GND#175 SSM3K7002FU_SC70-3 @ +5VS PM@ 1 PM@ 1 PM@ 1 1U_0402_6.3V4Z 10U_0603_6.3V6M A
V13
G
2
GND#176 @ 220 Ohm@100Mhz, 3A
G
2
10U_0603_6.3V6M 1U_0402_6.3V4Z
216-0729042-00 A13 M96 BGA 962P 030 2 R1241 1 CRB recommend 470 Ohm, 1A
PM@ Q97 100K_0402_5%
D
1
10/22 Modify to NC by Vivian @ L6 can change small current.
VGA_GPIO21 2
14 VGA_GPIO21
G
2
S
Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
3
R1242 SSM3K7002FU_SC70-3
@ 2009/02/24 2010/02/24 Title
Issued Date Deciphered Date
10K_0402_5%
add MAD@0903 MAD@ M97 Power,GND
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 16 of 61
5 4 3 2 1
5 4 3 2 1
item 03, Add M97@ 05/06
130mA L14
DPA_VDD18 0.1U_0402_16V4Z 2 1 +1.8VSDGPU
1 1 1 BLM18PG121SN1D_0603
C291
C292
C293
U4H MAD@
D D
item 05, Add M97@ 05/06 130mA DP C/D POWER DP A/B POWER
MAD@ 2 MAD@ 2 MAD@ 2
AP20 NC_DPC_VDD18#1 NC_DPA_VDD18#1 AN24 10U_0603_6.3V6M 1U_0402_6.3V4Z item 07, L30, Add M97@ M96@ 05/06
R139 MAD@ 0_0603_5% DPC_VDD18 AP21 AP24
+1.8VSDGPU NC_DPC_VDD18#2 NC_DPA_VDD18#2 Rual：Del L30 change 1.0VS to 1.1VS_VTT 05/12
110mA DVT, change power to +1.1VS 06/09
PM@ 110mA L29
+1.1VS R5 0_0603_5% DPC_VDD10 AP13 AP31 DPA_VDD10 0.1U_0402_16V4Z 2 1 +1.1VS
DPC_VDD10#1 DPA_VDD10#1 BLM18PG121SN1D_0603
AT13 AP32 1 1 1
DPC_VDD10#2 DPA_VDD10#2
C17
C16
C28
item 09, Add M97@ M96@ add R12 05/06 PM@
Rual: Del R12! change 1.0VS to 1.1VS_VTT 05/12
DVT, change power to +1.1VS 06/09 AN17 AN27
DPC_VSSR#1 DPA_VSSR#1 PM@ 2 PM@ 2 PM@ 2
AP16 AP27
DPC_VSSR#2 DPA_VSSR#2 10U_0603_6.3V6M 1U_0402_6.3V4Z
AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
AW14 AW24
DPC_VSSR#4 DPA_VSSR#4
AW16 AW26
DPC_VSSR#5 DPA_VSSR#5
item 06, Add M97@ 05/06 130mA item 04, Add M97@ 05/06
DPD_VDD18
130mA
+1.8VSDGPU R140 MAD@ 0_0603_5% AP22 AP25 R141
NC_DPD_VDD18#1 NC_DPB_VDD18#1 DPB_VDD18
AP23 AP26 2 1 +1.8VSDGPU
NC_DPD_VDD18#2 NC_DPB_VDD18#2 BLM18PG121SN1D_0603
110mA PM@ item 08,R11, Add M97@ M96@ 05/06
PM@ 110mA
R6 0_0603_5% DPD_VDD10 AP14 AN33 R7
Rua：Del R11!,change 1.0VS to 1.1VS_VTT 05/12
+1.1VS DPD_VDD10#1 DPB_VDD10#1 DVT, change power to +1.1VS 06/09
AP15 AP33 DPB_VDD10 2 1
DPD_VDD10#2 DPB_VDD10#2 +1.1VS
item 10, Add M97@ M96@ add R15 05/06 BLM18PG121SN1D_0603
Rual: Del R15 change 1.0VS to 1.1VS_VTT 05/12 PM@
DVT, change power to +1.1VS 06/09
AN19 AN29
J11 DPD_VSSR#1 DPB_VSSR#1
AP18 AP29
C @ DPD_VSSR#2 DPB_VSSR#2 C
AP19 AP30
JUMP_43X39 DPD_VSSR#3 DPB_VSSR#3
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
+1.1VS 1 2 +1.1VS_VTT AW22 AW32 L12
1 2 DPD_VSSR#5 DPB_VSSR#5 0.1U_0402_16V4Z 2 1 +1.8VSDGPU
1 2 2 BLM18PG121SN1D_0603
C226
C228
C230
DVT, 06/09 add 2
R106
1 AW18 AW28 1
R105 150_0402_1%
2
PM@
150_0402_1% DPCD_CALR DPAB_CALR PM@
PM@ 200mA 20mA PM@ 2 PM@ 1 PM@ 1
DP E/F POWER DP PLL POWER 10U_0603_6.3V6M 1U_0402_6.3V4Z
DPF_VDD18 AH34 AU28 DPA_PVDD
DPE_VDD18#1 DPA_PVDD R99
AJ34 AV27
item 11, Add M97@ M96@ add L2 05/06 DPE_VDD18#2 DPA_PVSS 0.1U_0402_16V4Z 2 1
Rual: Del L2! change 1.0VS to 1.1VS_VTT 05/12 BLM18PG121SN1D_0603
120mA 20mA 2
C235
DVT, change power to +1.1VS 06/09 PM@
DPE_VDD10 AL33 AV29 DPB_PVDD
DPE_VDD10#1 DPB_PVDD
AM33 AR28
L1 DPE_VDD10#2 DPB_PVSS PM@ 1
+1.1VS 2 1 0.1U_0402_16V4Z 20mA
BLM18PG121SN1D_0603 1 1 1
C18
C42
C45
PM@ AN34 AU18 DPC_PVDD
DPE_VSSR#1 DPC_PVDD 0.1U_0402_16V4Z R4 PM@ 0_0603_5%
AP39 AV17
PM@ PM@ PM@ DPE_VSSR#2 DPC_PVSS
AR39 DPE_VSSR#3 1
2 2 2
C1
AU37
DPE_VSSR#4 20mA
10U_0603_6.3V6M 1U_0402_6.3V4Z AW35
DPE_VSSR#5 DPD_PVDD
AV19
DPD_PVDD PM@ 2
200mA DPD_PVSS
AR18
+1.8VSDGPU 2 1 L3 0.1U_0402_16V4Z
BLM18PG121SN1D_0603 1 1 1 DPF_VDD18 AF34 20mA
DPF_VDD18#1
C22
C55
C51
PM@ AG34
item 12, Add M97@ M96@ add L4 05/06 DPF_VDD18#2 DPE_PVDD R3 PM@ 0_0603_5%
AM37
Rual Del L4！ change 1.0VS to 1.1VS_VTT 05/12 DPE_PVDD
120mA DPE_PVSS
AN38 1
B DVT, change power to +1.1VS 06/09 PM@ 2 PM@ 2 PM@ 2 C11 B
10U_0603_6.3V6M 1U_0402_6.3V4Z DPE_VDD10 AK33
DPF_VDD10#1 0.1U_0402_16V4Z
AK34
DPF_VDD10#2 2 PM@
AL38
NC_DPF_PVDD
AM35
NC_DPF_PVSS
AF39 L13
DPF_VSSR#1 0.1U_0402_16V4Z
AH39 2 1
DPF_VSSR#2 BLM18PG121SN1D_0603
AK39 1 1 2
DPF_VSSR#3
C238
C237
C236
AL34 PM@
DPF_VSSR#4
AM34
DPF_VSSR#5
PM@ 2 PM@ 2 PM@ 1
R107 10U_0603_6.3V6M 1U_0402_6.3V4Z
2 1 AM39
DPEF_CALR
150_0402_1%
PM@ 216-0729042-00 A13 M96 BGA 962P 030
PM@
There is no use on DPB/DPC/DPD,DPB_VDD10, DPC_VDD10,
DPD_VDD10, DPB_PVDD, DPC_PVDD and DPD_PVDD can be
A
powered without filter A
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2009/02/24 Deciphered Date 2010/02/24 Title
M96
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 17 of 61
5 4 3 2 1
5 4 3 2 1
U6 U7 U8 U9
MAA[0..13] VREFC_U6 M9 E4 MDA9 VREFC_U7 M9 E4 MDA30 VREFC_U8 M9 E4 MDA34 VREFC_U9 M9 E4 MDA52
15 MAA[0..13] VREFCA DQL0 VREFCA DQL0 VREFCA DQL0 VREFCA DQL0
VREFD_U6 H2 F8 MDA13 VREFD_U7 H2 F8 MDA27 VREFD_U8 H2 F8 MDA36 VREFD_U9 H2 F8 MDA51
QSA#[0..7] VREFDQ DQL1 MDA8 VREFDQ DQL1 MDA31 VREFDQ DQL1 MDA35 VREFDQ DQL1 MDA53
15 QSA#[0..7] DQL2 F3 DQL2 F3 DQL2 F3 DQL2 F3
MAA0 N4 F9 MDA14 MAA0 N4 F9 MDA25 MAA0 N4 F9 MDA39 MAA0 N4 F9 MDA48
QSA[0..7] MAA1 A0 DQL3 MDA12 MAA1 A0 DQL3 MDA28 MAA1 A0 DQL3 MDA32 MAA1 A0 DQL3 MDA54
15 QSA[0..7] P8 A1 DQL4 H4 P8 A1 DQL4 H4 P8 A1 DQL4 H4 P8 A1 DQL4 H4
MAA2 P4 H9 MDA15 MAA2 P4 H9 MDA26 MAA2 P4 H9 MDA38 MAA2 P4 H9 MDA50
DQMA#[0..7] MAA3 A2 DQL5 MDA10 MAA3 A2 DQL5 MDA29 MAA3 A2 DQL5 MDA33 MAA3 A2 DQL5 MDA55
15 DQMA#[0..7] N3 A3 DQL6 G3 N3 A3 DQL6 G3 N3 A3 DQL6 G3 N3 A3 DQL6 G3
MAA4 P9 H8 MDA11 MAA4 P9 H8 MDA24 MAA4 P9 H8 MDA37 MAA4 P9 H8 MDA49
MDA[0..63] MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7 MAA5 A4 DQL7
15 MDA[0..63] P3 A5 P3 A5 P3 A5 P3 A5
MAA6 R9 MAA6 R9 MAA6 R9 MAA6 R9
A_BA[0..2] MAA7 A6 MDA4 MAA7 A6 MDA16 MAA7 A6 MDA45 MAA7 A6 MDA56
15 A_BA[0..2] R3 A7 DQU0 D8 R3 A7 DQU0 D8 R3 A7 DQU0 D8 R3 A7 DQU0 D8
MAA8 T9 C4 MDA2 MAA8 T9 C4 MDA20 MAA8 T9 C4 MDA42 MAA8 T9 C4 MDA60
MEM_RST MAA9 A8 DQU1 MDA6 MAA9 A8 DQU1 MDA18 MAA9 A8 DQU1 MDA47 MAA9 A8 DQU1 MDA58
15,19 MEM_RST R4 A9 DQU2 C9 R4 A9 DQU2 C9 R4 A9 DQU2 C9 R4 A9 DQU2 C9
D MAA10 L8 C3 MDA3 MAA10 L8 C3 MDA23 MAA10 L8 C3 MDA43 MAA10 L8 C3 MDA63 D
MAA11 A10/AP DQU3 MDA5 MAA11 A10/AP DQU3 MDA19 MAA11 A10/AP DQU3 MDA44 MAA11 A10/AP DQU3 MDA59
R8 A11 DQU4 A8 R8 A11 DQU4 A8 R8 A11 DQU4 A8 R8 A11 DQU4 A8
+1.5VS_VRAM MAA12 N8 A3 MDA0 MAA12 N8 A3 MDA22 MAA12 N8 A3 MDA40 MAA12 N8 A3 MDA62
ODTA0_M MAA13 A12 DQU5 MDA7 MAA13 A12 DQU5 MDA17 MAA13 A12 DQU5 MDA46 MAA13 A12 DQU5 MDA57
T4 A13 DQU6 B9 T4 A13 DQU6 B9 T4 A13 DQU6 B9 T4 A13 DQU6 B9
T8 A4 MDA1 T8 A4 MDA21 T8 A4 MDA41 T8 A4 MDA61
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 A15/BA3 M8 A15/BA3 M8 A15/BA3 M8 A15/BA3
ODTA0 R144 1 2 2 R146 1 +1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM
15 ODTA0
0_0402_5% 56_0402_5%
ODTA1 R145 1 2 2 R147 1 A_BA0 M3 B3 A_BA0 M3 B3 A_BA0 M3 B3 A_BA0 M3 B3
15 ODTA1 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
0_0402_5% 56_0402_5% A_BA1 N9 D10 A_BA1 N9 D10 A_BA1 N9 D10 A_BA1 N9 D10
A_BA2 BA1 VDD A_BA2 BA1 VDD A_BA2 BA1 VDD A_BA2 BA1 VDD
M4 BA2 VDD G8 M4 BA2 VDD G8 M4 BA2 VDD G8 M4 BA2 VDD G8
VDD K3 VDD K3 VDD K3 VDD K3
ODTA1_M K9 K9 K9 K9
VDD VDD VDD VDD
VDD N2 VDD N2 VDD N2 VDD N2
RASA0# CLKA0 J8 N10 CLKA0 J8 N10 CLKA1 J8 N10 CLKA1 J8 N10
15 RASA0# CK VDD CK VDD CK VDD CK VDD
CLKA0# K8 R2 CLKA0# K8 R2 CLKA1# K8 R2 CLKA1# K8 R2
RASA1# CKEA0 CK VDD CKEA0 CK VDD CKEA1 CK VDD CKEA1 CK VDD
15 RASA1# K10 CKE/CKE0 VDD R10 K10 CKE/CKE0 VDD R10 K10 CKE/CKE0 VDD R10 K10 CKE/CKE0 VDD R10
+1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM
CASA0# ODTA0_M K2 A2 ODTA0_M K2 A2 ODTA1_M K2 A2 ODTA1_M K2 A2
15 CASA0# ODT/ODT0 VDDQ ODT/ODT0 VDDQ ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CSA0#_0 L3 A9 CSA0#_0 L3 A9 CSA1#_0 L3 A9 CSA1#_0 L3 A9
CASA1# RASA0# CS VDDQ RASA0# CS VDDQ RASA1# CS VDDQ RASA1# CS VDDQ
15 CASA1# J4 RAS VDDQ C2 J4 RAS VDDQ C2 J4 RAS VDDQ C2 J4 RAS VDDQ C2
CASA0# K4 C10 CASA0# K4 C10 CASA1# K4 C10 CASA1# K4 C10
WEA0# CAS VDDQ WEA0# CAS VDDQ WEA1# CAS VDDQ WEA1# CAS VDDQ
L4 WE VDDQ D3 L4 WE VDDQ D3 L4 WE VDDQ D3 L4 WE VDDQ D3
WEA0# E10 E10 E10 E10
15 WEA0# VDDQ VDDQ VDDQ VDDQ
VDDQ F2 VDDQ F2 VDDQ F2 VDDQ F2
WEA1# QSA1 F4 H3 QSA3 F4 H3 QSA4 F4 H3 QSA6 F4 H3
15 WEA1# DQSL VDDQ DQSL VDDQ DQSL VDDQ DQSL VDDQ
QSA0 C8 H10 QSA2 C8 H10 QSA5 C8 H10 QSA7 C8 H10
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ
CSA0#_0
15 CSA0#_0
DQMA#1 E8 A10 DQMA#3 E8 A10 DQMA#4 E8 A10 DQMA#6 E8 A10
CSA1#_0 DQMA#0 DML VSS DQMA#2 DML VSS DQMA#5 DML VSS DQMA#7 DML VSS
15 CSA1#_0 D4 DMU VSS B4 D4 DMU VSS B4 D4 DMU VSS B4 D4 DMU VSS B4
VSS E2 VSS E2 VSS E2 VSS E2
VSS G9 VSS G9 VSS G9 VSS G9
CKEA0 QSA#1 G4 J3 QSA#3 G4 J3 QSA#4 G4 J3 QSA#6 G4 J3
15 CKEA0 DQSL VSS DQSL VSS DQSL VSS DQSL VSS
C QSA#0 B8 J9 QSA#2 B8 J9 QSA#5 B8 J9 QSA#7 B8 J9 C
CKEA1 DQSU VSS DQSU VSS DQSU VSS DQSU VSS
15 CKEA1 VSS M2 VSS M2 VSS M2 VSS M2
VSS M10 VSS M10 VSS M10 VSS M10
VSS P2 VSS P2 VSS P2 VSS P2
CLKA0 2 R695 1 CLKA0_R MEM_RST T3 P10 MEM_RST T3 P10 MEM_RST T3 P10 MEM_RST T3 P10
15 CLKA0 RESET VSS RESET VSS RESET VSS RESET VSS
56_0402_5% T2 T2 T2 T2
CLKA0# CLKA0_R VSS VSS VSS VSS
15 CLKA0# 2 R696 1 L9 ZQ/ZQ0 VSS T10 L9 ZQ/ZQ0 VSS T10 L9 ZQ/ZQ0 VSS T10 L9 ZQ/ZQ0 VSS T10
56_0402_5% 1
0.01U_0402_16V7K C298 J2 B2 R148 J2 B2 R149 J2 B2 R150 J2 B2
R143 NC/ODT1 VSSQ 240_0402_1% NC/ODT1 VSSQ 240_0402_1% NC/ODT1 VSSQ 240_0402_1% NC/ODT1 VSSQ
L2 NC/CS1 VSSQ B10 L2 NC/CS1 VSSQ B10 L2 NC/CS1 VSSQ B10 L2 NC/CS1 VSSQ B10
2 240_0402_1% J10 NC/CE1 VSSQ D2 J10 NC/CE1 VSSQ D2 J10 NC/CE1 VSSQ D2 J10 NC/CE1 VSSQ D2
L10 NCZQ1 VSSQ D9 L10 NCZQ1 VSSQ D9 L10 NCZQ1 VSSQ D9 L10 NCZQ1 VSSQ D9
VSSQ E3 VSSQ E3 VSSQ E3 VSSQ E3
A1 NC VSSQ E9 A1 NC VSSQ E9 A1 NC VSSQ E9 A1 NC VSSQ E9
CLKA1 2 R697 1 CLKA1_R A11 F10 A11 F10 A11 F10 A11 F10
15 CLKA1 NC VSSQ NC VSSQ NC VSSQ NC VSSQ
56_0402_5% T1 G2 T1 G2 T1 G2 T1 G2
CLKA1# CLKA1_R NC VSSQ NC VSSQ NC VSSQ NC VSSQ
15 CLKA1# 2 R698 1 T11 NC VSSQ G10 T11 NC VSSQ G10 T11 NC VSSQ G10 T11 NC VSSQ G10
56_0402_5% 1
100-BALL 100-BALL 100-BALL 100-BALL
C299 0.01U_0402_16V7K SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
2 H5TQ1G63BFR-12C FBGA H5TQ1G63BFR-12C FBGA H5TQ1G63BFR-12C FBGA Need check part number H5TQ1G63BFR-12C FBGA
@ Need check part number Need check part number Need check part number
@ @ @
MIRROR U8
U9
U6 U7
+1.5VS_VRAM
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 1 1 1 1 1 1 K4W1G1646E-HC12
K4W1G1646E-HC12
C176 C222 C220 C177 C218 C217 C214 C215 K4W1G1646E-HC12 K4W1G1646E-HC12
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
2 2 2 2 2 2 2 2
B 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z B
+1.5VS_VRAM
+1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 1 1 1 1 1 1
2
2
+1.5VS_VRAM
R74 R73 R687 R691 C175 C213 C221 C178 C208 C219 C183 C206
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1
1
C180 C194 C184 C181 C185 C187 C209 C190 VREFC_U6 VREFC_U7 VREFC_U8 VREFC_U9
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
1
1
2 2 2 2 2 2 2 2
1 1 1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C197 R80 C199 R83 C294 R688 C296 R692
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% +1.5VS_VRAM
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 PM@ 2 PM@ 2 PM@ 2 PM@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2
2
1 1 1 1 1 1 1 1
C188 C182 C216 C189 C179 C192 C186 C193
+1.5VS_VRAM PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.5VS_VRAM +1.5VS_VRAM
1 1 1 1 1 1 1 1
+1.5VS_VRAM +1.5VS_VRAM
C784 C786 C300 C781 C785 C782 C787 C783
2
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
2
2 2 2 2 2 2 2 2 R689 R693 +1.5VS_VRAM
0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z R77 R75 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 4.99K_0402_1% 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 1 1 1 1 1 1
1
VREFD_U8 VREFD_U9
1
VREFD_U6 VREFD_U7 C794 C795 C788 C789 C790 C791 C792 C793
1
1
1 1 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
1
C295 R690 C297 R694 2 2 2 2 2 2 2 2
1 1
1
A C200 C198 R78 4.99K_0402_1% 4.99K_0402_1% 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z A
R84 4.99K_0402_1% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.5VS_VRAM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 PM@ 2 PM@
4.99K_0402_1%
2
2
2 PM@ 2 PM@
2
2
1
+ C250
220U_D2_4VM_R15
2 @ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/24 Deciphered Date 2010/02/24 Title
VRAM DDRA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
10/22 Add C1554 and close to U8 and U9
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBLB2 M/B LA-5412P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 17, 2009 Sheet 18 of 61
5 4 3 2 1
5 4 3 2 1
U2 U3 U5 U10
MAB[0..13]
15 MAB[0..13]
VREFC_U2 M9 E4 MDB3 VREFC_U3 M9 E4 MDB27 VREFC_U5 M9 E4 MDB43 VREFC_U10 M9 E4 MDB51
QSB#[0..7] VREFD_U2 VREFCA DQL0 MDB6 VREFD_U3 VREFCA DQL0 MDB28 VREFD_U5 VREFCA DQL0 MDB44 VREFD_U10 VREFCA DQL0 MDB52
15 QSB#[0..7] H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8
F3 MDB2 F3 MDB26 F3 MDB42 F3 MDB49
QSB[0..7] MAB0 DQL2 MDB7 MAB0 DQL2 MDB29 MAB0 DQL2 MDB45 MAB0 DQL2 MDB54
15 QSB[0..7] N4 A0 DQL3 F9 N4 A0 DQL3 F9 N4 A0 DQL3 F9 N4 A0 DQL3 F9
MAB1 P8 H4 MDB1 MAB1 P8 H4 MDB25 MAB1 P8 H4 MDB41 MAB1 P8 H4 MDB50
DQMB#[0..7] MAB2 A1 DQL4 MDB5 MAB2 A1 DQL4 MDB31 MAB2 A1 DQL4 MDB47 MAB2 A1 DQL4 MDB55
15 DQMB#[0..7] P4 A2 DQL5 H9 P4 A2 DQL5 H9 P4 A2 DQL5 H9 P4 A2 DQL5 H9
MAB3 N3 G3 MDB0 MAB3 N3 G3 MDB24 MAB3 N3 G3 MDB40 MAB3 N3 G3 MDB48
MDB[0..63] MAB4 A3 DQL6 MDB4 MAB4 A3 DQL6 MDB30 MAB4 A3 DQL6 MDB46 MAB4 A3 DQL6 MDB53
15 MDB[0..63] P9 A4 DQL7 H8 P9 A4 DQL7 H8 P9 A4 DQL7 H8 P9 A4 DQL7 H8
MAB5 P3 MAB5 P3 MAB5 P3 MAB5 P3
B_BA[0..2] MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
15 B_BA[0..2] R9 A6 R9 A6 R9 A6 R9 A6
MAB7 R3 D8 MDB14 MAB7 R3 D8 MDB21 MAB7 R3 D8 MDB38 MAB7 R3 D8 MDB61
MAB8 A7 DQU0 MDB10 MAB8 A7 DQU0 MDB16 MAB8 A7 DQU0 MDB32 MAB8 A7 DQU0 MDB59
T9 A8 DQU1 C4 T9 A8 DQU1 C4 T9 A8 DQU1 C4 T9 A8 DQU1 C4
MEM_RST MAB9 R4 C9 MDB15 MAB9 R4 C9 MDB20 MAB9 R4 C9 MDB39 MAB9 R4 C9 MDB63
15,18 MEM_RST +1.5VS_VRAM A9 DQU2 A9 DQU2 A9 DQU2 A9 DQU2
D MAB10 L8 C3 MDB11 MAB10 L8 C3 MDB18 MAB10 L8 C3 MDB35 MAB10 L8 C3 MDB58 D
ODTB0_M MAB11 A10/AP DQU3 MDB12 MAB11 A10/AP DQU3 MDB23 MAB11 A10/AP DQU3 MDB37 MAB11 A10/AP DQU3 MDB60
R8 A11 DQU4 A8 R8 A11 DQU4 A8 R8 A11 DQU4 A8 R8 A11 DQU4 A8
MAB12 N8 A3 MDB8 MAB12 N8 A3 MDB19 MAB12 N8 A3 MDB34 MAB12 N8 A3 MDB56
MAB13 A12 DQU5 MDB13 MAB13 A12 DQU5 MDB22 MAB13 A12 DQU5 MDB36 MAB13 A12 DQU5 MDB62
T4 A13 DQU6 B9 T4 A13 DQU6 B9 T4 A13 DQU6 B9 T4 A13 DQU6 B9
ODTB0 R703 1 2 2 R705 1 T8 A4 MDB9 T8 A4 MDB17 T8 A4 MDB33 T8 A4 MDB57
15 ODTB0 A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
0_0402_5% 56_0402_5% M8 M8 M8 M8
ODTB1 R704 1 A15/BA3 +1.5VS_VRAM A15/BA3 +1.5VS_VRAM A15/BA3 +1.5VS_VRAM A15/BA3 +1.5VS_VRAM
15 ODTB1 2 2 R706 1
0_0402_5% 56_0402_5%
B_BA0 M3 B3 B_BA0 M3 B3 B_BA0 M3 B3 B_BA0 M3 B3
B_BA1 BA0 VDD B_BA1 BA0 VDD B_BA1 BA0 VDD B_BA1 BA0 VDD
N9 BA1 VDD D10 N9 BA1 VDD D10 N9 BA1 VDD D10 N9 BA1 VDD D10
ODTB1_M B_BA2 M4 G8 B_BA2 M4 G8 B_BA2 M4 G8 B_BA2 M4 G8
BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K3 VDD K3 VDD K3 VDD K3
RASB0# K9 K9 K9 K9
15 RASB0# VDD VDD VDD VDD
VDD N2 VDD N2 VDD N2 VDD N2
RASB1# CLKB0 J8 N10 CLKB0 J8 N10 CLKB1 J8 N10 CLKB1 J8 N10
15 RASB1# CK VDD CK VDD CK VDD CK VDD
CLKB0# K8 R2 CLKB0# K8 R2 CLKB1# K8 R2 CLKB1# K8 R2
CKEB0 CK VDD CKEB0 CK VDD CKEB1 CK VDD CKEB1 CK VDD
K10 CKE/CKE0 VDD R10 K10 CKE/CKE0 VDD R10 K10 CKE/CKE0 VDD R10 K10 CKE/CKE0 VDD R10
CASB0# +1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM
15 CASB0#
CASB1# ODTB0_M K2 A2 ODTB0_M K2 A2 ODTB1_M K2 A2 ODTB1_M K2 A2
15 CASB1# ODT/ODT0 VDDQ ODT/ODT0 VDDQ ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CSB0#_0 L3 A9 CSB0#_0 L3 A9 CSB1#_0 L3 A9 CSB1#_0 L3 A9
RASB0# CS VDDQ RASB0# CS VDDQ RASB1# CS VDDQ RASB1# CS VDDQ
J4 RAS VDDQ C2 J4 RAS VDDQ C2 J4 RAS VDDQ C2 J4 RAS VDDQ C2
WEB0# CASB0# K4 C10 CASB0# K4 C10 CASB1# K4 C10 CASB1# K4 C10
15 WEB0# CAS VDDQ CAS VDDQ CAS VDDQ CAS VDDQ
WEB0# L4 D3 WEB0# L4 D3 WEB1# L4 D3 WEB1# L4 D3
WEB1# WE VDDQ WE VDDQ WE VDDQ WE VDDQ
15 WEB1# VDDQ E10 VDDQ E10 VDDQ E10 VDDQ E10
VDDQ F2 VDDQ F2 VDDQ F2 VDDQ F2
QSB0 F4 H3 QSB3 F4 H3 QSB5 F4 H3 QSB6 F4 H3
CSB0#_0 QSB1 DQSL VDDQ QSB2 DQSL VDDQ QSB4 DQSL VDDQ QSB7 DQSL VDDQ
15 CSB0#_0 C8 DQSU VDDQ H10 C8 DQSU VDDQ H10 C8 DQSU VDDQ H10 C8 DQSU VDDQ H10
CSB1#_0
15 CSB1#_0
DQMB#0 E8 A10 DQMB#3 E8 A10 DQMB#5 E8 A10 DQMB#6 E8 A10
DQMB#1 DML VSS DQMB#2 DML VSS DQMB#4 DML VSS DQMB#7 DML VSS
D4 DMU VSS B4 D4 DMU VSS B4 D4 DMU VSS B4 D4 DMU VSS B4
CKEB0 E2 E2 E2 E2
15 CKEB0 VSS VSS VSS VSS
VSS G9 VSS G9 VSS G9 VSS G9
CKEB1 QSB#0 G4 J3 QSB#3 G4 J3 QSB#5 G4 J3 QSB#6 G4 J3
15 CKEB1 DQSL VSS DQSL VSS DQSL VSS DQSL VSS
C QSB#1 B8 J9 QSB#2 B8 J9 QSB#4 B8 J9 QSB#7 B8 J9 C
DQSU VSS DQSU VSS DQSU VSS DQSU VSS
VSS M2 VSS M2 VSS M2 VSS M2
VSS M10 VSS M10 VSS M10 VSS M10
CLKB0 2 R710 1 CLKB0_R P2 P2 P2 P2
15 CLKB0 VSS VSS VSS VSS
56_0402_5% MEM_RST T3 P10 MEM_RST T3 P10 MEM_RST T3 P10 MEM_RST T3 P10
CLKB0# RESET VSS RESET VSS RESET VSS RESET VSS
15 CLKB0# 2 R707 1 CLKB0_R
VSS T2 VSS T2 VSS T2 VSS T2
56_0402_5% 1 L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
C796
0.01U_0402_16V7K R699 J2 B2 R700 J2 B2 R701 J2 B2 R702 J2 B2
2 240_0402_1% NC/ODT1 VSSQ 240_0402_1% NC/ODT1 VSSQ 240_0402_1% NC/ODT1 VSSQ 240_0402_1% NC/ODT1 VSSQ
L2 NC/CS1 VSSQ B10 L2 NC/CS1 VSSQ B10 L2 NC/CS1 VSSQ B10 L2 NC/CS1 VSSQ B10
J10 NC/CE1 VSSQ D2 J10 NC/CE1 VSSQ D2 J10 NC/CE1 VSSQ D2 J10 NC/CE1 VSSQ D2
L10 NCZQ1 VSSQ D9 L10 NCZQ1 VSSQ D9 L10 NCZQ1 VSSQ D9 L10 NCZQ1 VSSQ D9
CLKB1 2 R709 1 CLKB1_R E3 E3 E3 E3
15 CLKB1 VSSQ VSSQ VSSQ VSSQ
56_0402_5% A1 E9 A1 E9 A1 E9 A1 E9
CLKB1# 2 R708 CLKB1_R NC VSSQ NC VSSQ NC VSSQ NC VSSQ
15 CLKB1# 1 A11 NC VSSQ F10 A11 NC VSSQ F10 A11 NC VSSQ F10 A11 NC VSSQ F10
56_0402_5% 1 T1 G2 T1 G2 T1 G2 T1 G2
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
T11 NC VSSQ G10 T11 NC VSSQ G10 T11 NC VSSQ G10 T11 NC VSSQ G10
C797
0.01U_0402_16V7K 100-BALL 100-BALL 100-BALL 100-BALL
2 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
Need check part number
H5TQ1G63BFR-12C FBGA H5TQ1G63BFR-12C FBGA H5TQ1G63BFR-12C FBGA H5TQ1G63BFR-12C FBGA
@ @ @
@
+1.5VS_VRAM U2 U3 U5
U10
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 1 1 1 1 1 1 1 1
C249 C136 C167 C169 C248 C143 C173 C172 C147 C161 K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ K4W1G1646E-HC12
2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
B B
+1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
2
2
+1.5VS_VRAM
1 1 1 1 1 1 1 1 1 1
R47 R14 R711 R715
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% C72 C239 C69 C35 C24 C240 C20 C25 C39 C82
1 1 1 1 1 1 1 1 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
2 2 2 2 2 2 2 2 2 2
1
1
C145 C159 C164 C151 C133 C134 C127 C174 VREFC_U2 VREFC_U3 VREFC_U5 VREFC_U10 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
1
1
2 2 2 2 2 2 2 2
1 1 1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C126 R49 C23 R16 C798 R712 C800 R716
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +1.5VS_VRAM
2 PM@ 2 PM@ 2 PM@ 2 PM@
2
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1
C52 C53 C81 C50 C43 C31 C44 C80
+1.5VS_VRAM PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM +1.5VS_VRAM
1 1 1 1 1 1
C802 C803 C804 C805 C806 C807
2
2
PM@ PM@ PM@ PM@ PM@ PM@
2 2 2 2 2 2 R63 R34 R713 R717
0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% +1.5VS_VRAM
0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1
1
VREFD_U2 VREFD_U3 VREFD_U5 VREFD_U10 1 1 1 1 1 1
1
1
1 1 1 1 C808 C809 C810 C811 C812 C813
A C170 R62 C77 R33 C799 R714 C801 R718 PM@ PM@ PM@ PM@ PM@ PM@ A
2 2 2 2 2 2
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
+1.5VS_VRAM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
2 PM@ 2 PM@ 2 PM@ 2 PM@
2
2
1
+ C247
220U_D2_4VM_R15
2 @ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/24 Deciphered Date 2010/02/24 Title
VRAM DDRA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
10/22 Add C1555 and close to U10 and U11 Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NBLB2 M/B LA-5412P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 17, 2009 Sheet 19 of 61
5 4 3 2 1
5 4 3 2 1
+3VS
have the pull high on PCH/VGA side
UMA@
UMA@
UMA@
UMA@
UMA@
UMA@
UMA@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VGA_HDMI_C_CLK- DISO@R296
DISO@R296 1 2 0_0402_5% HDMI_R_CLK- DISO@R783
DISO@R783 1 2 0_0402_5% HDMI_CLK- 1 1 1 1 1 1 1
VGA_HDMI_C_CLK+ DISO@R297
DISO@ R297 1 2 0_0402_5% HDMI_R_CLK+ DISO@R784
DISO@ R784 1 2 0_0402_5% HDMI_CLK+
VGA_HDMI_C_TX0- DISO@R298
DISO@ R298 1 2 0_0402_5% HDMI_R_TX0- DISO@R785
DISO@ R785 1 2 0_0402_5% HDMI_TX0-
C932
C935
C931
C936
C937
C938
C939
VGA_HDMI_C_TX0+ DISO@R359
DISO@ R359 1 2 0_0402_5% HDMI_R_TX0+ DISO@R786
DISO@ R786 1 2 0_0402_5% HDMI_TX0+ +3VS UMAO@ 1 2 R418 0_0402_5%
VGA_HDMI_C_TX1+ DISO@R362
DISO@ R362 0_0402_5% HDMI_R_TX1+ DISO@R788
DISO@ R788 0_0402_5% HDMI_TX1+ SG@ 2 2 2 2 2 2 2
1 2 1 2 21,22,29 DGPU_EDIDSEL# 1 2 R424 0_0402_5%
VGA_HDMI_C_TX1- DISO@R365
DISO@ R365 1 2 0_0402_5% HDMI_R_TX1- DISO@R787
DISO@ R787 1 2 0_0402_5% HDMI_TX1-
2
VGA_HDMI_C_TX2+ DISO@R385
DISO@ R385 1 2 0_0402_5% HDMI_R_TX2+ DISO@R789
DISO@ R789 1 2 0_0402_5% HDMI_TX2+ 2N7002DW-T/R7_SOT363-6
VGA_HDMI_C_TX2- DISO@R367
DISO@ R367 1 2 0_0402_5% HDMI_R_TX2- DISO@R790
DISO@ R790 1 2 0_0402_5% HDMI_TX2-
D 27 PCH_DDPDATA 1 6 HDMIDAT_R D
UMA@
5
C469 1 2 DIS@ 0.1U_0402_16V7K VGA_HDMI_C_CLK- Q2050A +3VS DGPU_SELECT#
14 VGA_HDMI_CLK-
C470 1 2 DIS@ 0.1U_0402_16V7K VGA_HDMI_C_CLK+
14 VGA_HDMI_CLK+
4 3 HDMICLK_R L: 0 -> Y(Madison)
27 PCH_DDPCLK
C471 1 2 DIS@ 0.1U_0402_16V7K VGA_HDMI_C_TX0- UMA@ H: 1 -> Y(PCH)
48
41
35
19
13
14 VGA_HDMI_TX0-
7
1
C472 1 2 DIS@ 0.1U_0402_16V7K VGA_HDMI_C_TX0+ 2N7002DW-T/R7_SOT363-6 Q2050B 1 1 U50
14 VGA_HDMI_TX0+
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C473 1 2 DIS@ 0.1U_0402_16V7K VGA_HDMI_C_TX1- C820 C819
14 VGA_HDMI_TX1-
C474 1 2 DIS@ 0.1U_0402_16V7K VGA_HDMI_C_TX1+ @ @ VGA_HDMI_C_CLK- 55
14 VGA_HDMI_TX1+ CLK-A
12P_0402_50V8J 2 2 12P_0402_50V8J VGA_HDMI_C_CLK+ 56
C475 1 CLK+A
14 VGA_HDMI_TX2- 2 DIS@ 0.1U_0402_16V7K VGA_HDMI_C_TX2- VGA_HDMI_C_TX2+ 2 D0-A HPD_SINK 47
C476 1 2 DIS@ 0.1U_0402_16V7K VGA_HDMI_C_TX2+ VGA_HDMI_C_TX2- 3 46
14 VGA_HDMI_TX2+ D0+A SDA_SINK
VGA_HDMI_C_TX1+ 5 45
VGA_HDMI_C_TX1- D1-A SCL_SINK
6 D1+A
+3VS_DELAY DISO@ 1 2 R842 0_0402_5% VGA_HDMI_C_TX0+ 8
C647 1 D2-A
27 PCH_HDMI_CLK- 2 UMA@ 0.1U_0402_16V7K PCH_HDMI_C_CLK-
21,22 IGPU_EDIDSEL#
SG@ 1 2 R843 0_0402_5% VGA_HDMI_C_TX0- 9 D2+A CLK- 43 HDMI_CLK-
C645 1 2 UMA@ 0.1U_0402_16V7K PCH_HDMI_C_CLK+ 42 HDMI_CLK+
27 PCH_HDMI_CLK+ CLK+
40 HDMI_TX2+
C646 1 D0-
27 PCH_HDMI_TX0- 2 UMA@ 0.1U_0402_16V7K PCH_HDMI_C_TX0- 51 HPDA D0+ 39 HDMI_TX2-
2
C643 1 2 UMA@ 0.1U_0402_16V7K PCH_HDMI_C_TX0+ 2N7002DW-T/R7_SOT363-6 52 37 HDMI_TX1+
27 PCH_HDMI_TX0+ SDAA D1-
53 36 HDMI_TX1-
C478 1 SCLA D1+
27 PCH_HDMI_TX1- 2 UMA@ 0.1U_0402_16V7K PCH_HDMI_C_TX1- 14 VGA_HDMI_SDA 1 6 HDMIDAT_R 23 HDPB D2- 34 HDMI_TX0+
C644 1 2 UMA@ 0.1U_0402_16V7K PCH_HDMI_C_TX1+ DIS@ 24 33 HDMI_TX0-
27 PCH_HDMI_TX1+ SDAB D2+
5
Q38A 25
C648 1 SCLB
27 PCH_HDMI_TX2- 2 UMA@ 0.1U_0402_16V7K PCH_HDMI_C_TX2-
C477 1 2 UMA@ 0.1U_0402_16V7K PCH_HDMI_C_TX2+ 14 VGA_HDMI_SCL 4 3 HDMICLK_R 26 R773 1 @ 2 0_0402_5%
27 PCH_HDMI_TX2+ EQ_S1
PCH_HDMI_C_CLK- 11 28 R774 1 @ 2 0_0402_5%
2N7002DW-T/R7_SOT363-6 Q38B DIS@ PCH_HDMI_C_CLK+ CLK-B EQ_S0 R775 1 @ 0_0402_5%
12 CLK+B OC_S2 29 2
C PCH_HDMI_C_TX2+ 14 30 R776 1 @ 2 0_0402_5% C
PCH_HDMI_C_TX2- D0-B OC_S1 R777 1 @ 0_0402_5%
15 D0+B OC_S0 31 2
PCH_HDMI_C_TX1+ 17 50 HDMI_OE#
+5VS +5VS 0_0402_5% PCH_HDMI_C_TX1- D1-B /OE
18 D1+B SEL2 27 DGPU_SELECT# 22,28
+3VS UMA@ 1 2 R849 PCH_HDMI_C_TX0+ 20 49
D2-B SEL1 IGPU_SELECT# 21,22
3 3 PCH_HDMI_C_TX0- 21
GND
GND
GND
GND
GND
GND
GND
GND
GND
DISO@ 1 0_0402_5% R850 D2+B
+3VS_Delay 2
1 HDMIDAT_R 1 HDMICLK_R
PI3HDMI201ZFEX_TQFN56_11X5
4
10
16
22
32
38
44
54
57
1
@ @ C R770 UMA@
2
D3
2
D4
DVT, change HDMI detec 06/09 New add in 0824 Q40 2 1 2 HP_DET
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 B 150K_0402_5%
0_0402_5% E MMBT3904_NL_SOT23-3 150K_0402_5% OE#--SEL1--SEL2--Result
2
VGA_HDMI_HPD DISO@ 1 2 R851 HDMI_DET_SW
0_0402_5% R814
1----X----X----Hi-Z
TMDS pull down (500ohm) resistors G9x only PCH_HDMI_HPD UMAO@ 1 2 R853 0----1----X----A active
1
0----0----1----B activve
R285 need change to 365 K
0----0----0----B all port dis
1
VGA_HDMI_C_CLK+ 1 2 10K_0402_1% 11/11
R269 PM@ 499_0402_1%
VGA_HDMI_C_CLK- 1 2
2
R270 PM@ 499_0402_1% @
VGA_HDMI_C_TX0+ 1 2
R273 PM@ 499_0402_1% +5VS
VGA_HDMI_C_TX0- 1 2
Same as Nvidia and ATI
R274 PM@ 499_0402_1%
VGA_HDMI_C_TX1+ 1 2 RB491D_SC59-3
R275 PM@ 499_0402_1% 0_0402_5% 0_0805_5%
D D7
1
VGA_HDMI_C_TX1- 1 2 NV@ 2 R277 1 +3VS R281 @
B R276 PM@ 499_0402_1% B
2 2 1 +5VS 2 1
VGA_HDMI_C_TX2+ 1 2 G ATI@ R278
R279 PM@ 499_0402_1% S PM@ 0_0402_5% +5VS +VCC_HDMI +5VS_HDMI
1 2
3
VGA_HDMI_C_TX2- 1 2 Q14 R282 @ 1
R280 PM@ 499_0402_1% 0.1U_0402_16V4Z 0_0805_5% F1
2N7002W-T/R7_SOT323-3 1.1A_6VDC_FUSE C479
NEAR CONNECT SG@
1 2
0.1U_0402_16V4Z
U54 +5VS_HDMI 2
C827
1
WCM-2012-900T_4P 2 8
14 VGA_HDMI_HPD 1A VCC
HDMI_CLK+ 4 3 HDMI_CLK+_CONN 5 3 HDMI_DET_SW R283 R284 JHDMI1
4 3 27 PCH_HDMI_HPD 2A 1B
1 6 2.2K_0402_5% 2.2K_0402_5% HP_DET 19
21,22,29 DGPU_EDIDSEL# 1OE# 2B HP_DET
L36 7 4 18
+3VS 21,22 IGPU_EDIDSEL# 2OE# GND +5V
HDMI_CLK- 1 HDMI_CLK-_CONN
2 2 17
2
1 SN74CBTD3306CPWR_TSSOP8 HDMIDAT_R DDC/CEC_GND
16 SDA
WCM-2012-900T_4P HDMICLK_R
HDMI_TX0+ HDMI_TX0+_CONN
L: A=B 15 SCL
4 4 3 3 14 Reserved
2
13 CEC
L37 R287 HDMI_CLK-_CONN 12 20
HDMI_TX0- HDMI_TX0-_CONN +5VS CK- GND
1 1 2 2 10K_0402_1% 11 CK_shield GND 21
HDMI_CLK+_CONN 10 22
WCM-2012-900T_4P UMA@ HDMI_TX0-_CONN CK+ GND
9 23
1
D0- GND
3
HDMI_TX1+ 4 3 HDMI_TX1+_CONN 8
4 3 HDMI_OE# HDMI_TX0+_CONN D0_shield
7 D0+
L39 HDMI_TX1-_CONN 6
HDMI_TX1- HDMI_TX1-_CONN UMA@ D8 D1-
1 1 2 2 D 5 D1_shield
1
@ BAT54S-7-F_SOT23-3 HDMI_TX1+_CONN 4
WCM-2012-900T_4P Q207 HP_DET HDMI_TX2-_CONN D1+
2 3
1
HDMI_TX2+ HDMI_TX2+_CONN G D2-
4 4 3 3 2 D2_shield
2
S HP_DET HDMI_TX2+_CONN 1
3
A D2+ A
SSM3K7002FU_SC70-3 R340
HDMI_TX2- 1 2 HDMI_TX2-_CONN 100K_0402_1% TYCO_1775040-6
1 2 CONN@
L40 UMA@
1
HDMI_CLK+ @ R288 1 2 0_0402_5% HDMI_CLK+_CONN
HDMI_CLK- @ R289 1 2 0_0402_5% HDMI_CLK-_CONN
HDMI_TX0+ @ R290 1 2 0_0402_5% HDMI_TX0+_CONN Security Classification Compal Secret Data Compal Electronics,Ltd.
HDMI_TX0- @ R291 1 2 0_0402_5% HDMI_TX0-_CONN 2009/02/04 2010/02/04 Title
Issued Date Deciphered Date
HDMI_TX1+ @ R292 0_0402_5% HDMI_TX1+_CONN
HDMI_TX1- @ R293
1
1
2
2 0_0402_5% HDMI_TX1-_CONN HDMI Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI_TX2+ @ R294 1 2 0_0402_5% HDMI_TX2+_CONN Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
HDMI_TX2- @ R295 0_0402_5% HDMI_TX2-_CONN Custom 0.1
1 2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 20 of 61
5 4 3 2 1
A B C D E
+5VS
Checklist recommend: 2-pole filter on R/G/B signals
CRT Connector C-L-C-L-C D12 D13 D14
Change PCB footprint of L43 from L_0805 to R_0805
2
@ @ @
DAN217_SC59 DAN217_SC59 DAN217_SC59 L41 +CRT_VCC
10p - 47 Ohm/100MHz - 22p - 47 Ohm/100MHz - 10p KC FBM-L11-201209-221LMAT_0805
1
+R_CRT_VCC
W=40mils
12/15 Modified. Note L26~L30 are 0 Ohm resisters
1
D15 F2 W=40mils
+L_CRT_VCC 2
(IFTXX) 1 1 2
3
RB491D_SC59-3 1.1A_6VDC_FUSE
Change PCB footprint of L45/ L47/ L49 from L_0603 to R_0603 +3VS 1
1 1
C481
0.1U_0402_16V4Z
2
CRT_R CRT_R_1 L43 1 2 CRT_R_2 JCRT1
L42 0_0603_5% FBMA-L10-160808-800LMT_0603 6
11
CRT_G CRT_G_1 L45 1 2 CRT_G_2 1
L44 0_0603_5% FBMA-L10-160808-800LMT_0603 7
12
CRT_B CRT_B_1 L47 1 2 CRT_B_2 2
L46 0_0603_5% FBMA-L10-160808-800LMT_0603 8
1
13
1
R299 R300 1 1 1 1 1 1 3
R301 C484 C485 C486 C487 C488 C489 1 1 1 9
@ @ @ 14
150_0402_1% C482 C483 C490 4
2
2 2 2 2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 10 16
2
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 2 2 2
15 17
150_0402_1% 22P_0402_50V8J 22P_0402_50V8J 1 5
10P_0402_50V8J
SUYIN_070546FR015S233CR
+CRT_VCC 1 2 CRT_HSYNC_2 C491
L48 FCM1608C-121T_0603 <EMI> 2
1 2 2 1 100P_0402_50V8J DSUB_12
<EMI>
C492 0.1U_0402_16V4Z R302 10K_0402_5% 1 2 CRT_VSYNC_2
L49 FCM1608C-121T_0603 1
1
U15 <EMI> C493
1 1 <EMI>
OE#
P
CRT_H_SYNC 1 2 VGA_HSYNC_R 2 4 CRT_HSYNC_0 1 2 CRT_HSYNC_1 C495 68P_0402_50V8K
+3VS R303 0_0402_5% A Y R304 39_0402_1% C494 2
G
10P_0402_50V8J 10P_0402_50V8J DSUB_15
2 TC7SET125FUF_SC70 <EMI> 2 2 <EMI> 2
3
+CRT_VCC 1
SG@ SG@ SG@ SG@ Place closed to chipset C496
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 2 2 2 1 2 68P_0402_50V8K
C531 C532 C641 C642 C497 0.1U_0402_16V4Z 2
1
U16
<EMI>
OE#
P
1 1 1 1 CRT_V_SYNC VGA_VSYNC_R CRT_VSYNC_0
1 2 2 4 1 2 CRT_VSYNC_1 12/22 Change to SE071680J80
R305 0_0402_5% A Y R306 39_0402_1%
(IFTXX)
1
TC7SET125FUF_SC70
3
D16 D17 Add IFTXX
<EMI> <EMI> Andy_1102
Change PCB footprint of L50/L51 from L_0603 to R_0603 DAN217_SC59 DAN217_SC59
+3VS @ @
3
U43 +5VS
1
VDD
4 12 IGPU_SELECT# 20,22
VDD SEL
9 VDD
19 2 CRT_R
VDD YA CRT_G
5
YB
27 DAC_RED 24
A0 YC
6 CRT_B L: 0 -> Y(PCH) R845
22 DISO@ 0_0402_5%
27 DAC_GRN
18
B0
8 CRT_H_SYNC
H: 1 -> Y(M96) 2 1
27 DAC_BLU C0 YD +3VS_DELAY
17 11 CRT_V_SYNC
27 CRT_HSYNC D0 YE
27 CRT_VSYNC 14
E0 SG@ R846
14 VGA_CRT_R 23 3 2 1 IGPU_EDIDSEL# 20,22
3 A1 GND 3
14 VGA_CRT_G 21 B1 GND 7
2
16 10 0_0402_5%
14 VGA_CRT_B C1 GND
15 20 DIS@
14 VGA_HSYNC D1 GND DSUB_12
14 VGA_VSYNC 13 6 1 VGA_DDC_DATA 14
SG@ E1
PI3V512QE_QSOP24 Q39A
5
2N7002DW-T/R7_SOT363-6
DAC_RED UMAO@ R791 1 2 0_0402_5% DAC_RED_R UMAO@ R801 1 2 0_0402_5% CRT_R DSUB_15 DIS@ 3 4
DAC_GRN DAC_GRN_R UMAO@ CRT_G VGA_DDC_CLK 14
UMAO@ R794 1 2 0_0402_5% R804 1 2 0_0402_5%
DAC_BLU UMAO@ R792 1 2 0_0402_5% DAC_BLU_R UMAO@ R802 1 2 0_0402_5% CRT_B Q39B
CRT_HSYNC UMAO@ R793 1 2 0_0402_5% CRT_HSYNC_R UMAO@ R803 1 2 0_0402_5% CRT_H_SYNC 2N7002DW-T/R7_SOT363-6
CRT_VSYNC UMAO@ R795 1 2 0_0402_5% CRT_VSYNC_R UMAO@ R805 1 2 0_0402_5% CRT_V_SYNC
DGPU_EDIDSEL# 20,22,29
VGA_CRT_R DISO@ R796 1 2 0_0402_5% DAC_RED_R1 DISO@ R822 1 2 0_0402_5% CRT_R +CRT_VCC R847
2
VGA_CRT_G DISO@ R799 1 2 0_0402_5% DAC_GRN_R1 DISO@ R826 1 2 0_0402_5% CRT_G
0_0402_5%
VGA_CRT_B DISO@ R797 1 2 0_0402_5% DAC_BLU_R1 DISO@ R824 1 2 0_0402_5% CRT_B
+3VS
VGA_HSYNC DISO@ R798 1 2 0_0402_5% CRT_HSYNC_R1 DISO@ R823 1 2 0_0402_5% CRT_H_SYNC SG@
2
R848
VGA_VSYNC DISO@ R800 1 2 0_0402_5% CRT_VSYNC_R1 DISO@ R825 1 2 0_0402_5% CRT_V_SYNC UMAO@
0_0402_5%
1
1
1
2.2K_0402_5%
R3070 R3080 R3090 R3100
2.2K_0402_5%
1
2.2K_0402_5% 2.2K_0402_5%
UMA@
UMA@
2
2
2
UMA@
DSUB_12 6 1 CRT_DDC_DATA 27
Q3900A
5
2N7002DW-T/R7_SOT363-6
4 UMA@ 4
DSUB_15 3 4 CRT_DDC_CLK 27
Q3900B
2N7002DW-T/R7_SOT363-6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
CRT Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 21 of 61
A B C D E
5 4 3 2 1
LCD POWER CIRCUIT +3VS
+3VALW +3VS
1
+LCDVDD U48 100P_0402_50V8J
W=60mils 1 2 C498 BKOFF#
SG@ @
NC
2 4 PCH_PWM# 100P_0402_50V8J 1 2 C879 VGA_ENVDD
27 PCH_INV_PWM
1
A Y
1
G
R312 2 C499 470P_0402_50V7K 1 2 C501 INVTPWM
300_0603_5% R313 C500 NC7SZ14P5X_NL_SC70-5~D
3
100K_0402_5% 4.7U_0805_10V4Z 470P_0402_50V7K 1 2 C502 DAC_BRIG
0.1U_0402_10V7K 2 @ @
1 2
1 PCH_INV_PWM R844 1 2 0_0402_5%PCH_PWM# 470P_0402_50V7K 1 2 C503 DISPOFF#
3
D S
G <BOM Structure>
Q19 <BOM Structure>
2 2 1 <BOM Structure>
2 Q16 +3VS 0.1U_0402_16V4Z 2@ 1C509 +LCDVDD_CONN
SSM3K7002FU_SC70-3 G <BOMR315
Structure> 100K_0402_5% SI2301BDS_SOT23
S <BOM Structure>
1
U53
D
SG@
For EMI
NC
1
1
<BOM Structure> D +LCDVDD
20,21,29 DGPU_EDIDSEL# 2 4 IGPU_EDIDSEL# 20,21
D LCDVDD_ON R317 1 A Y D
2 0_0402_5% 2 Q20
Plac C484 close to JLVDS2
G
G SSM3K7002FU_SC70-3 <BOM Structure>
<BOM Structure> S NC7SZ14P5X_NL_SC70-5~D
3
1 1 1
@ C504 C505
R318 <BOM Structure>
100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2
modify on 08/20 by Jeson
2
<BOM Structure> +3VS Change PCB footprint of L22/L23
<BOM Structure>
from L_0805 to R_0805
1
U52 +LEDVDD
SG@ B+ FBMA-L11-201209-221LMA30T_0805
NC
2 4 IGPU_PWMSEL# 1 2 L50 R649
28 DGPU_PWMSEL# A Y
+5VS 2 1+5V_CAMERA
G
U45 0_0603_5%
SELx NC7SZ14P5X_NL_SC70-5~D C506 1 1 1 1
3
16 680P_0402_50V7K C507 C756 C757
L---B1=>A SLE1 IGPU_SELECT# 20,21
4.7U_0805_25V6-K
H---B2=>A 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 5 @ 2 2 2 2
0B1 A0 +LCDVDD
1 6
1B1 A1
80 +LEDVDD
0B2 JLVDS2
79
1B2 +3VS +LCDVDD_CONN
(60 MIL) 1
1 2
2
78 8 LVDS_B2# L51 3 4 +LCDVDD_CONN
27 PCH_LVDS_B2# 2B1 A2 3 4
77 9 LVDS_B2 2 1 5 6 +5V_CAMERA
27 PCH_LVDS_B2
1
3B1 A3 U49 FBMA-L11-201209-221LMA30T_0805 5 6
+3VS 7 8 +3VS
SG@ USB20_R_P2 7 8 LVDS_B2#
76 9 10
NC
13 VGA_LVDS_B2# 2B2 @ 9 10
75 2 4 1 USB20_R_N2 11 12 LVDS_B2
13 VGA_LVDS_B2 3B2 20,28 DGPU_SELECT# A Y IGPU_SELECT# 20,21 680P_0402_50V7K 11 12
INVTPWM 13 14 LVDS_BCLK#
G
LVDS_BCLK# C508 DISPOFF# 13 14 LVDS_BCLK
27 PCH_LVDS_BCLK# 73 11 15 16
4B1 A4 LVDS_BCLK NC7SZ14P5X_NL_SC70-5~D 15 16 LVDS_B1#
27 PCH_LVDS_BCLK 72 12 39 DAC_BRIG 17 18
3
5B1 A5 2 17 18 LVDS_B1
19 20
19 20 LVDS_A0#
13 VGA_LVDS_BCLK# 71 21 22
4B2 21 22 LVDS_A0
13 VGA_LVDS_BCLK 70 23 24
5B2 23 24 LVDS_B0
25 26
LVDS_B1 25 26 LVDS_B0#
27 PCH_LVDS_B1 68 14 27 28
6B1 A6 LVDS_B1# 27 28 LVDS_A1
27 PCH_LVDS_B1# 67 15 29 30
7B1 A7 29 30 LVDS_A1#
31 32
C 31 32 LVDS_A2# C
13 VGA_LVDS_B1 66 33 34
6B2 33 34 LVDS_A2
13 VGA_LVDS_B1# 65 35 36
7B2 LVDS_SCL 35 36 LVDS_ACLK#
37 38
LVDS_B0# LVDS_DAT 37 38 LVDS_ACLK
27 PCH_LVDS_B0# 64 17 39 40
8B1 A8 LVDS_B0 +5VS 39 40
27 PCH_LVDS_B0 63 18 41 42
9B1 A9 GND1GND2
62 0.1U_0402_16V4Z ACES_87142-4041-BS
13 VGA_LVDS_B0# 8B2
13 VGA_LVDS_B0 61 1 2
9B2
IGPU_SELECT# R8621 @ U47
34 13 VGA_PWM 2 0_0402_5% C825 SG@ DISO@
SEL2
39 INVT_PWM 1R861 2 0_0402_5% 2 8 39 INVT_PWM
INVT_PWM R837 1 2 0_0402_5% INVTPWM
SG@ PCH_PWM# 1A VCC INVTPWM
5 3
LVDS_A0 2A 1B PCH_PWM# UMAO@ R827 1
27 PCH_LVDS_A0 60 23 28 DGPU_PWMSEL# 1 6 2 0_0402_5%
10B1 A10 LVDS_A0# IGPU_PWMSEL#7 1OE# 2B VGA_PWM @ R828 1
27 PCH_LVDS_A0# 59 24 4 13 VGA_PWM 2 0_0402_5%
11B1 A11 2OE# GND
58 SN74CBTD3306CPWR_TSSOP8 PCH_ENVDD UMAO@ R829 1 2 0_0402_5% LCDVDD_ON
13 VGA_LVDS_A0 10B2
57 L: A=B VGA_ENVDD DISO@ R830 1 2 0_0402_5%
13 VGA_LVDS_A0# 11B2
56 26 LVDS_A1# SG@ PCH_ENBKL UMAO@ R831 1 2 0_0402_5% LCD_ENBKL
27 PCH_LVDS_A1# 12B1 A12 +5VS
55 27 LVDS_A1 VGA_ENBKL DISO@ R832 1 2 0_0402_5%
27 PCH_LVDS_A1 13B1 A13 +3VS
0.1U_0402_16V4Z
13 VGA_LVDS_A1# 54 1 2
12B2
13 VGA_LVDS_A1 53 U46
1
13B2 C824
51 29 LVDS_A2# 13 VGA_ENVDD 2 8 R311
27 PCH_LVDS_A2# 14B1 A14 1A VCC
50 30 LVDS_A2 27 PCH_ENVDD 5 3 LCDVDD_ON
27 PCH_LVDS_A2 15B1 A15 2A 1B
20,28 DGPU_SELECT# 1 6 SG@ 4.7K_0402_5%
1OE# 2B D18
13 VGA_LVDS_A2# 49 20,21 IGPU_SELECT# 7 4
2
14B2 2OE# GND BKOFF# DISPOFF#
13 VGA_LVDS_A2 48 39 BKOFF# 1 2
15B2 SN74CBTD3306CPWR_TSSOP8
46 32 LVDS_ACLK# CH751H-40PT_SOD323-2
27 PCH_LVDS_ACLK# 16B1 A16 +5VS
45 33 LVDS_ACLK LCD_ENBKL 2 1 ENBKL
27 PCH_LVDS_ACLK 17B1 A17 SG@ ENBKL 39
0.1U_0402_16V4Z R314 0_0402_5%
13 VGA_LVDS_ACLK# 44 L: A=B 1 2
2
16B2
13 VGA_LVDS_ACLK 43
17B2 U51 C826 SG@ R316
42 35 2 8 100K_0402_1%
18B1 A18 +3VS 14 VGA_ENBKL 1A VCC
41 36 5 3 LCD_ENBKL
19B1 A19 27 PCH_ENBKL 2A 1B
1 6 change from 10K to 100K
28 DGPU_PWMSEL#
1
IGPU_PWMSEL#7 1OE# 2B 5/8 by checklist
40 4
18B2 2OE# GND
39
+3VS 19B2 SN74CBTD3306CPWR_TSSOP8
B B
L: A=B
3 4
GND1 VDD1 SG@
10K_0402_5%
SG@ 13 10
2
GND2 VDD2
20 19
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
GND3 VDD3
R1309
LCDVDD_ON 21 22 1 1 1 +3VS
GND4 VDD4
31 28
GND5 VDD5
R1340
38 37 new add in 08/31
2
GND6 VDD6
G
C823
C822
C821
R1343
52 47
1
SG@ GND7 VDD7 2 2 2 UMAO@ R836 1 2 0_0402_5%
4.7K_0402_5%
74 69 +3VS
1
1
GND8 VDD8 USB20_N2 R654 1 2 0_0402_5% USB20_R_N2
4.7K_0402_5%
3 1 25 28 USB20_N2
OE2# SG@ R833 1 Need check
2 0_0402_5% USB20_P2 R653 1 2 0_0402_5% USB20_R_P2
S
7 20,21,29 DGPU_EDIDSEL# 28 USB20_P2
OE1# SG@ SG@ SG@ <BOM Structure>
<BOM Structure> D38
Q30
+3VS 2 1 2 3
2
2
2
SSM3K7002FU_SC70-3 PI3LVD1012BE_BQSOP80 R1339 4.7K_0402_5% UMA@ @ I/O I/O
WCM2012F2SF-121T04_0805
UMA@
SG@ 27 PCH_LVDS_SDA 1 6 LVDS_DAT 4 3 1 4 +5VS
PCH_LVDS_B2# UMAO@ R386 LVDS_B2# 4 3 GND VCC
1 20_0402_5%
PCH_LVDS_B2 UMAO@ R387 1 20_0402_5% LVDS_B2 Q203A PJLCR05 SOT143
PCH_LVDS_BCLK# UMAO@ R397 1 20_0402_5% LVDS_BCLK# 2N7002DW-T/R7_SOT363-6 1 2 @
PCH_LVDS_BCLK UMAO@ R398 1 2
1 20_0402_5% LVDS_BCLK +3VS 2 1
5
PCH_LVDS_B1# UMAO@ R402 1 20_0402_5% LVDS_B1# R1342 4.7K_0402_5% L80
PCH_LVDS_B1 UMAO@ R400 1 20_0402_5% LVDS_B1 UMA@ UMA@
PCH_LVDS_B0# UMAO@ R543 1 20_0402_5% LVDS_B0# 27 PCH_LVDS_SCL 4 3 LVDS_SCL
PCH_LVDS_B0 UMAO@ R544 1 20_0402_5% LVDS_B0
PCH_LVDS_A0# UMAO@ R651 1 20_0402_5% LVDS_A0# Q203B
PCH_LVDS_A0 UMAO@ R655 1 20_0402_5% LVDS_A0 2N7002DW-T/R7_SOT363-6
PCH_LVDS_A1# UMAO@ R652 1 20_0402_5% LVDS_A1#
PCH_LVDS_A1 UMAO@ R731 1 20_0402_5% LVDS_A1
PCH_LVDS_A2# UMAO@ R733 1 20_0402_5% LVDS_A2#
PCH_LVDS_A2 UMAO@ R732 1 20_0402_5% LVDS_A2 +3VS_DELAY DISO@ R835 1 2 0_0402_5%
PCH_LVDS_ACLK# UMAO@ R734 1 20_0402_5% LVDS_ACLK#
PCH_LVDS_ACLK UMAO@ R735 1 20_0402_5% LVDS_ACLK SG@ R834 1 2 0_0402_5%
20,21 IGPU_EDIDSEL#
2
VGA_LVDS_B2# DISO@ R744 1 2 0_0402_5% LVDS_B2# DIS@
VGA_LVDS_B2 DISO@ R746 1 2 0_0402_5% LVDS_B2
VGA_LVDS_BCLK# DISO@ R745 1 2 0_0402_5% LVDS_BCLK# 14 VGA_LVDS_SDA 1 6 LVDS_DAT
VGA_LVDS_BCLK DISO@ R747 1 2 0_0402_5% LVDS_BCLK
VGA_LVDS_B1# DISO@ R749 1 2 0_0402_5% LVDS_B1# Q205A
VGA_LVDS_B1 DISO@ R748 1 2 0_0402_5% LVDS_B1 2N7002DW-T/R7_SOT363-6
VGA_LVDS_B0# DISO@ R750 1 2 0_0402_5% LVDS_B0#
5
A VGA_LVDS_B0 DISO@ R751 1 2 0_0402_5% LVDS_B0 A
VGA_LVDS_A0# DISO@ R753 1 2 0_0402_5% LVDS_A0# DIS@
VGA_LVDS_A0 DISO@ R755 1 2 0_0402_5% LVDS_A0 14 VGA_LVDS_SCL 4 3 LVDS_SCL
VGA_LVDS_A1# DISO@ R752 1 2 0_0402_5% LVDS_A1#
VGA_LVDS_A1 DISO@ R754 1 2 0_0402_5% LVDS_A1 Q205B
VGA_LVDS_A2# DISO@ R758 1 2 0_0402_5% LVDS_A2# 2N7002DW-T/R7_SOT363-6
VGA_LVDS_A2 DISO@ R756 1 2 0_0402_5% LVDS_A2
VGA_LVDS_ACLK# DISO@ R757 0_0402_5% LVDS_ACLK#
VGA_LVDS_ACLK DISO@ R759
1
1
2
2 0_0402_5% LVDS_ACLK NBLB2 M/B LA-5412P Schematic
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
LVDS & DVI Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 17, 2009 Sheet 22 of 61
5 4 3 2 1
A B C D E F G H
+CLK_VDD
+CLK_VDDSRC
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS L52 2 1 +3VS L53 2 1
FBMA-L11-201209-221LMA30T_0805 FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1 1 1 1 1 1 1
C511 C512 C513 C515 C516 C517 C518 C519 C520
C510 C514
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2
1 1
0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0_0402_5%
CLK_VGA_27M R743 1 2 CLK_VGA_27M_R1
@
+CLK_VDDSRC
+CLK_VDDSRC +CLK_VDD
+CLK_VDD
Clock Generator
U17
Integrated 33ohm Resistor
1 32 D_CK_SCLK
0_0404_4P2R_5% VDD_USB_48 SCL D_CK_SDATA D_CK_SCLK 6,11,12
2 VSS_48M SDA 31 D_CK_SDATA 6,11,12
CLK_BUF_DREF_96M 1 4 CLK_BUF_DREF_96M_R 3 30 REF_0/CPU_SEL R319 1 2 33_0402_5%
25 CLK_BUF_DREF_96M DOT_96 REF_0/CPU_SEL CLK_BUF_ICH_14M 25
CLK_BUF_DREF_96M# 2 3 CLK_BUF_DREF_96M#_R 4 29
25 CLK_BUF_DREF_96M# DOT_96# VDD_REF
RP1 5 28 CLK_XTAL_IN
CLK_VGA_27M_R1 VDD_27 XTAL_IN CLK_XTAL_OUT
6 27MHZ XTAL_OUT 27
CLK_VGA_27M R742 10_0402_5% 2CLK_VGA_27M_R 7 26
14 CLK_VGA_27M 27MHZ_SS VSS_REF
CLK_SD_48M 1 2 CLK_SD_48M_R 8 25 CK505_PWRGD
34 CLK_SD_48M USB_48 CKPWRGD/PD#
R320 33_0402_5%
2 9 24 2
CLK_BUF_PCIE_SATA CLK_BUF_PCIE_SATA_R VSS_27M VDD_CPU CLK_BUF_CPU_BCLK_R CLK_BUF_CPU_BCLK
25 CLK_BUF_PCIE_SATA 1 4 10 SATA CPU_0 23 1 4 CLK_BUF_CPU_BCLK 25
CLK_BUF_PCIE_SATA# 2 3 CLK_BUF_PCIE_SATA#_R 11 22 CLK_BUF_CPU_BCLK#_R 2 3 CLK_BUF_CPU_BCLK#
25 CLK_BUF_PCIE_SATA# SATA# CPU_0# CLK_BUF_CPU_BCLK# 25
RP2 0_0404_4P2R_5% 12 21 0_0404_4P2R_5%
CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI_R VSS_SRC VSS_CPU RP3
25 CLK_BUF_CPU_DMI 1 4 13 SRC_1 CPU_1 20
CLK_BUF_CPU_DMI# 2 3 CLK_BUF_CPU_DMI#_R 14 19
25 CLK_BUF_CPU_DMI# SRC_1# CPU_1#
RP4 0_0404_4P2R_5% 15 VDD_SRC_IO VDD_CPU_IO 18 Integrated 33ohm Resistor C872
H_STP_CPU# 16 17 D_CK_SCLK @ 1 2 100P_0402_50V8J
CPU_STOP# VDD_SRC
Integrated 33ohm Resistor 33 IDT SA000030P00 C873
TGND
D_CK_SDATA @ 1 2 100P_0402_50V8J
SLG8SP587VTR_QFN32_5X5
IDT: 9LRS3199AKLFT, SA000030P00 +3VS 4/2 Add by Vivian
SILEGO: SLG8SP587, SA00002XY00
2
R321
10K_0402_5%
R322
+3VS 0_0402_5%
1
Silego Have Internal Pull-Up CK505_PWRGD 1 2 VGATE 26,57
@
D
1
R323 1 2 10K_0402_5% H_STP_CPU# +3VS 2 CLK_ENABLE# 57
R324 G 4/2 Add by Vivian
4.7K_0402_5% S Q9 C871
3
2
G
1 2 +3VS 2N7002_SOT23 CLK_ENABLE# @ 1 2 100P_0402_50V8J
3 3
1 3 D_CK_SDATA
25,37 PCH_SMBDATA
S
IDT Have Internal Pull-Down Q11
2N7002_SOT23 C521
CLK_XTAL_IN 2 1
R325 1 2 10K_0402_5% REF_0/CPU_SEL +3VS
1
R326 27P_0402_50V8J
2 4.7K_0402_5% Y6
G 1 2 +3VS 14.31818MHz_20P_FSX8L14.318181M20FDB C522
27P_0402_50V8J
2
PIN 30 CPU_0 CPU_1 25,37 PCH_SMBCLK 1 3 D_CK_SCLK CLK_XTAL_OUT 2 1
D
Q10
0 (Default) 133MHz 133MHz 2N7002_SOT23
1 100MHz 100MHz
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
Clock Generator (CK505)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 23 of 61
A B C D E F G H
5 4 3 2 1
1 2 PCH_RTCRST#
DVT 06/09 ice add
+RTCVCC
R327 C523
20K_0402_1% RC Delay 18~25mS 18P_0402_50V8J
2 1 PCH_RTCX1
close to RAM door 2 1
J5 JOPEN @ X1
1
1 @ 2 3 4
R328 NC OSC R329
2 1
10K_0603_5% J6 JOPEN @ 2 1
C524 NC OSC 10M_0402_5% U18A
1U_0603_10V6K
REV1.0
2
1 2 32.768KHZ_12.5PF_Q13MC14610002 C525 B13 D33 LPC_AD0
PCH_RTCX2 RTCX1 FWH0 / LAD0 LPC_AD1 LPC_AD0 37,39,42,47
D 2 1 D13 RTCX2 FWH1 / LAD1 B33 LPC_AD1 37,39,42,47 D
C32 LPC_AD2
18P_0402_50V8J FWH2 / LAD2 LPC_AD3 LPC_AD2 37,39,42,47
FWH3 / LAD3 A32 LPC_AD3 37,39,42,47
+RTCVCC 1 2 PCH_SRTCRST# PCH_RTCRST# C14
R330 RTCRST# LPC_FRAME#
FWH4 / LFRAME# C34 LPC_FRAME# 37,39,42,47
20K_0402_1% RC Delay 18~25mS +RTCVCC PCH_SRTCRST# D17 SRTCRST#
A34
RTC
LPC
LDRQ0#
close to RAM door R331 1 2 1M_0402_5% SM_INTRUDER# A16 INTRUDER# LDRQ1# / GPIO23 F34
1 @ 2
R332 R333 330K_0402_5% PCH_INTVRMEN A14 AB9 SERIRQ
10K_0603_5% INTVRMEN SERIRQ SERIRQ 39,47
2/26 Change R1519 to 330K
C526
1U_0603_10V6K INTVRMEN - Integrated SUS 1.1V VRM Enable
1 2 HDA_BITCLK_PCH A30
High - Enable Internal VRs HDA_BCLK SATA_DTX_C_IRX_N0
SATA0RXN AK7 SATA_DTX_C_IRX_N0 33
HDA_SYNC_PCH D29 AK6 SATA_DTX_C_IRX_P0 0.01U_0402_16V7K SATA for HDD1
HDA_SYNC SATA0RXP SATA_DTX_C_IRX_P0 33
HDA for AUDIO AK11 SATA_ITX_DRX_N0 C527 1 2 SATA_ITX_C_DRX_N0
SATA0TXN SATA_ITX_C_DRX_N0 33
PCH_SPKR P1 AK9 SATA_ITX_DRX_P0 C528 1 2 SATA_ITX_C_DRX_P0
44 PCH_SPKR SPKR SATA0TXP SATA_ITX_C_DRX_P0 33
1 2 HDA_BITCLK_PCH 0.01U_0402_16V7K
44 HDA_BITCLK_AUDIO
R334 33_0402_5% HDA_RST_PCH# C30
HDA_SYNC_PCH HDA_RST# SATA_DTX_C_IRX_N1
44 HDA_SYNC_AUDIO 1 2 SATA1RXN AH6 SATA_DTX_C_IRX_N1 33
R335 33_0402_5% AH5 SATA_DTX_C_IRX_P1 0.01U_0402_16V7K SATA for ODD
SATA1RXP SATA_DTX_C_IRX_P1 33
1 2 HDA_RST_PCH# G30 AH9 SATA_ITX_DRX_N1 C529 1 2 SATA_ITX_C_DRX_N1
44 HDA_RST_AUDIO# 44 HDA_SDIN0 HDA_SDIN0 SATA1TXN SATA_ITX_C_DRX_N1 33
R336 33_0402_5% AH8 SATA_ITX_DRX_P1 C530 1 2 SATA_ITX_C_DRX_P1
SATA1TXP SATA_ITX_C_DRX_P1 33
1 2 HDA_SDOUT_PCH F30 0.01U_0402_16V7K
44 HDA_SDOUT_AUDIO HDA_SDIN1
R337 33_0402_5% AF11
SATA2RXN
E32 AF9
IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6
C 12/26 SATA2/SATA3 Desktop Only C
SATA3RXN AH3
HDA_SDOUT_PCH B29 AH1
HDA_SDO SATA3RXP
SATA3TXN AF3
SATA3TXP AF1
PWRME_CTRL H32
39 PWRME_CTRL
SATA
HDA_DOCK_EN# / GPIO33
SATA4RXN AD9
1 J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8
SATA4TXN AD6
R341
1K_0402_5%
SATA4TXP AD5
@ PCH_JTAG_TCK M3 AD3
JTAG_TCK SATA5RXN Project ID table
AD1
2
PCH_JTAG_TMS SATA5RXP
K3 JTAG_TMS SATA5TXN AB3
SATA5TXP AB1 ID1 ID0
PCH_JTAG_TDI K1 JTAG_TDI +1.05VS
0
JTAG
+3VS DIS 0
R348 PCH_JTAG_TDO J2 AF16
1K_0402_5% JTAG_TDO SATAICOMPO
SG 0 1
1 2 PCH_SPKR PCH_JTAG_RST# J4 AF15 SATA_COMP R347 1 2 37.4_0402_1%
TRST# SATAICOMPI
Have internal PD UMA 1 1
R355 1 @ 2 SERIRQ
10K_0402_5% PCH_SPI_CLK_1 R349 1 2 0_0402_5% PCH_SPI_CLK BA2 +3VS
SPI_CLK
PCH_SPI_CS0# R352 1 2 0_0402_5% PCH_SPI_CS0#_R AV3 R354 1 2 10K_0402_5%
SPI_CS0#
3/20 Modify By Vivian
3/16 Change to 0 ohm(Follow Intel's comment) AY3 T3 SATA_LED#
SPI_CS1# SATALED# SATA_LED# 47
R358 1 UMAO@ 2 10K_0402_5% +3VS
B B
3/26 Add C855 EMI Project Port ID
PCH_SPI_MOSI_1 R357 1 2 0_0402_5% PCH_SPI_MOSI AY1 Y9 PROJECT_ID1 PROJECT_ID1 R353 1 2 10K_0402_5%
<EMI> PCH_SPI_CLK_1 SPI_MOSI SATA0GP / GPIO21 DIS@
1 2
SPI
@ PCH_SPI_MISO_1 R360 1 2 0_0402_5% PCH_SPI_MISO AV1 V1 PROJECT_ID0
22P_0402_50V8J SPI_MISO SATA1GP / GPIO19
R361 1 UMA@ 2 10K_0402_5% +3VS
IBEXPEAK-M_FCBGA1071~D
+3VALW +1.05VS PROJECT_ID0 R350 1 2 10K_0402_5%
PCH_JTAG PCH_JTAG DISO@
PCH_PIN RefDes
R363 1 @ 2 51_0402_5% 2008 Intel MOW36/MOW50
R364 1 @ 2 200_0402_5%
ES1 ES2 MP
PCH_JTAG_TMS R366 1 @ 2 100_0402_5% TDO: R369 No Install 200ohm No Install
Reserved on ES1 Sample PCH_JTAG_TDO
R368 1 @ 2 51_0402_5% R370 100ohm 3/20 Modify By Vivian
R369 1 @ Mount R369, R370 on ES2 Sample No Install No Install +3VS
2 200_0402_5%
PCH_JTAG_TDO R370 1 @ 2 100_0402_5% R364 200ohm 200ohm U20
No Install PCH_SPI_CS0#
PCH_JTAG_TMS 1 CS# VCC 8
R371 1 @ 2 51_0402_5% MP mount R363, R368, R366 100ohm 100ohm PCH_SPI_MISO_1 2 7 SPI_HOLD1#
R372 1 @
No Install SO HOLD#
2 200_0402_5% R371, R374 and remove
SPI_WP1# 3 WP# SCLK 6 PCH_SPI_CLK_1
PCH_JTAG_TDI R373 1 @ 2 100_0402_5% R372 200ohm 200ohm 4 5 PCH_SPI_MOSI_1
others No Install GND SI
PCH_JTAG_TDI
R374 1 @ 2 51_0402_5% R373 100ohm W25X16AVSSIG SOIC _8P
R376 1 @
100ohm No Install
2 20K_0402_5%
PCH_JTAG_RST# R378 1 @ 2 10K_0402_5% PCH_JTAG_TCK R380 51ohm 51ohm SPI ROM Footprint 150mil
51ohm
R376 20Kohm 20Kohm No Install 11/18 SPI ROM Change to SA00002TO00
PCH_JTAG_RST# 3/20 SPI ROM Change to SA00001KN10(Follow NIWBA)
A R378 10Kohm 10Kohm No Install A
+3VS R377 1 2 3.3K_0402_5% SPI_HOLD1#
+3VS R375 1 2 3.3K_0402_5% SPI_WP1#
PCH_SPI_MOSI R379 1 @ 2 1K_0402_5%
enable iTPM: SPI_MOSI High Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
PCH_JTAG_TCK R380 51_0402_1% PCH (1/9) SATA,HDA,SPI, LPC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRB 1.0 Change to 4.7K Need double check AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
3/16 Change R380 to 51 ohm(follow Intel's comment)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 24 of 61
5 4 3 2 1
5 4 3 2 1
U18B
REV1.0 1. Connect Directly
BG30 B9 EC_LID_OUT#
PERN1 SMBALERT# / GPIO11 EC_LID_OUT# 39 EXPRESS CARD, MINI1, MINI2
For Express Card BJ30 PERP1
BF29 PETN1 SMBCLK H14 PCH_SMBCLK
PCH_SMBCLK 23,37 2. Level Shift1, Pull-Up to +3VS
BH29 PETP1
C8 PCH_SMBDATA CLOCK GEN, DIMM1, DIMM2
SMBDATA PCH_SMBDATA 23,37
37 PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_N2 AW30
PERN2 3. Level Shift2, Pull-Up to +3VS
PCIE_PTX_C_IRX_P2 BA30
37 PCIE_PTX_C_IRX_P2
C533 2 0.1U_0402_16V7K PCIE_ITX_PRX_N2 BC30 PERP2 PCH_GPIO60 LAN
For Wireless LAN 37 PCIE_ITX_C_PRX_N2 1 PETN2 SML0ALERT# / GPIO60 J14
37 PCIE_ITX_C_PRX_P2
C534 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P2 BD30
PETP2 4. Level Shift3, Pull-Up to +3VS
D C6 PCH_SML0CLK 3/16 Add by Vivian(follow D
PCIE_PTX_C_IRX_N3 AU30
SML0CLK CPU & PCH XDP
Intel's comment)
SMBus
35 PCIE_PTX_C_IRX_N3 PERN3
PCIE_PTX_C_IRX_P3 AT30 G8 PCH_SML0DAT
35 PCIE_PTX_C_IRX_P3 PERP3 SML0DATA
For PCIE LAN C535 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N3 AU32
35 PCIE_ITX_C_PRX_N3 PETN3
C536 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P3 AV32
35 PCIE_ITX_C_PRX_P3 PETP3
M14 PCH_GPIO74
PCIE_PTX_C_IRX_N4 SML1ALERT# / GPIO74
37 PCIE_PTX_C_IRX_N4 BA32 PERN4
PCIE_PTX_C_IRX_P4 BB32 E10 PCH_SML1CLK +3VS
37 PCIE_PTX_C_IRX_P4 PERP4 SML1CLK / GPIO58
C538 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N4 BD32
37 PCIE_ITX_C_PRX_N4 PETN4
1
C537 2 0.1U_0402_16V7K PCIE_ITX_PRX_P4 PCH_SML1DAT +3VALW R381 +3VS
For 3G Card 37 PCIE_ITX_C_PRX_P4 1 BE32 PETP4 SML1DATA / GPIO75 G12
10K_0402_5%
PCI-E*
BF33 @
PERN5
1
BH33 T13 R383
PERP5 CL_CLK1
Controller
BG32 1 R740 2 10K_0402_5%
DGPU_PWR_EN 29,43,48
2 2
PETN5 R382 UMAO@ 0_0402_5%
BJ32 PETP5 CL_DATA1 T11
10K_0402_5% 2N7002_SOT23 Q8 SG@
G
Link
SG@
BA34 T9 SG@
2
PERN6 CL_RST1# R384 2
AW34 PERP6 1 3 1 PEG_CLKREQ# 14
BC34 0_0402_5%
S
PETN6
2
BD34 PETP6 SG@
H1 PEG_CLKREQ#_R R414 1 DISO@ 2 R739
PEG_A_CLKRQ# / GPIO47 2.2K_0402_5% 2.2K_0402_5%
AT34 PERN7
AU34 SG@
PERP7
AU36 AD43 CLK_PCIE_VGA# 13
1
PETN7 CLKOUT_PEG_A_N
AV36 PETP7 CLKOUT_PEG_A_P AD45 CLK_PCIE_VGA 13 +3VS
BG34 PERN8 CLKOUT_DMI_N AN4 CLK_CPU_DMI# 6
PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_CPU_DMI 6
2
G
BG36 PETN8
C BJ36 C
PETP8 PCH_SML1CLK EC_SMB_CK2
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1 CLK_CPU_DP# 6 1 3 EC_SMB_CK2 14,39
AT3
S
CLKOUT_DP_P / CLKOUT_BCLK1_P CLK_CPU_DP 6
AK48 Q13
CLKOUT_PCIE0N 2N7002_SOT23
AK47 CLKOUT_PCIE0P 2/28 Follow Module design Rev1.0
From CLK BUFFER
CLKIN_DMI_N AW24 CLK_BUF_CPU_DMI# 23
P9 BA24 +3VS
PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_CPU_DMI 23
2
R388 1 2 0_0402_5% CLK_PCIE_WLAN#_R
G
37 CLK_PCIE_WLAN# AM43 CLKOUT_PCIE1N CLKIN_BCLK_N AP3 CLK_BUF_CPU_BCLK# 23
For Wireless LAN R389 1 2 0_0402_5% CLK_PCIE_WLAN_R AM45 AP1
37 CLK_PCIE_WLAN CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_CPU_BCLK 23
PCH_SML1DAT 1 3 EC_SMB_DA2
R390 1 EC_SMB_DA2 14,39
2 0_0402_5% PCH_GPIO18 U4
S
37 WLAN_CLKREQ# PCIECLKRQ1# / GPIO18
F18 Q12
CLKIN_DOT_96N CLK_BUF_DREF_96M# 23
E18 2N7002_SOT23
CLKIN_DOT_96P CLK_BUF_DREF_96M 23
R391 1 2 0_0402_5% CLK_PCIE_LAN#_R AM47
35 CLK_PCIE_LAN# CLKOUT_PCIE2N
For PCIE LAN R392 1 2 0_0402_5% CLK_PCIE_LAN_R AM48
35 CLK_PCIE_LAN CLKOUT_PCIE2P
CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_PCIE_SATA# 23
R815 1 2 0_0402_5% PCH_GPIO20 N4 AH12
35 LAN_CLKREQ# PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_PCIE_SATA 23
R393 1 2 0_0402_5% CLK_PCIE_3G#_R AH42 P41 Buffer Mode check is need or not
37 CLK_PCIE_3G# CLKOUT_PCIE3N REFCLK14IN CLK_BUF_ICH_14M 23
For 3G Card R394 1 2 0_0402_5% CLK_PCIE_3G_R AH41
37 CLK_PCIE_3G CLKOUT_PCIE3P
37 3G_CLKREQ# A8 PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK J42 CLK_PCI_FB 28
C539
18P_0402_50V8J
AM51 AH51 XTAL25_IN 1 2
CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT
AM53 CLKOUT_PCIE4P XTAL25_OUT AH53
1
B @ B
PCH_GPIO26 M9 AF38 XCLK_RCOMP R395 1 2 90.9_0402_1% +1.05VS R396 Y7
PCIECLKRQ4# / GPIO26 XCLK_RCOMP 1M_0402_5% 25MHZ_20P
@ @
2
AJ50 T45
2
CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
AJ52 CLKOUT_PCIE5P 1 2
+3VS PCH_GPIO44 H6 P43 C540
Clock Flex
PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65 18P_0402_50V8J
3/20 Remove by Vivian @
PCH_GPIO20 R399 1 2 10K_0402_5% AK53 T42
PCH_GPIO18 R401 1 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
2 10K_0402_5% AK51 CLKOUT_PEG_B_P
PCH_GPIO56 P13 N50 CLK_CARD_48M_R 1 2 C869
+3VALW PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 CLK_SD_48M_PCH 34
PCH_SMBDATA @ 1 2 100P_0402_50V8J
R403 @
IBEXPEAK-M_FCBGA1071~D 22_0402_5% C870
EC_LID_OUT# R404 1 2 10K_0402_5% PCH_SMBCLK @ 1 2 100P_0402_50V8J
PCH_SMBCLK R405 1 2 2.2K_0402_5%
PCH_SMBDATA R406 1 2 2.2K_0402_5%
PCH_GPIO60 R407 1 2 10K_0402_5%
Project ID 2008/1/6 2009MOW01 change to 22 ohm
4/2 Add by Vivian
PCH_SML1CLK R408 1 2 2.2K_0402_5%
PCH_SML1DAT R409 1 2 2.2K_0402_5%
ID1 ID0 Project
PCH_GPIO74 R410 1 2 10K_0402_5% 3/16 Change R408/R409 to 2.2K 0 0 Future
3G_CLKREQ# R411 1
ohm(follow Intel's comment)
A 2 10K_0402_5% * 0 1 JV A
PCH_GPIO44 R412 1 2 10K_0402_5%
PCH_GPIO56 R413 1 2 10K_0402_5%
PCH_GPIO26 R415 1 2 10K_0402_5%
PCH_SML0CLK R761 1 2 2.2K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
PCH_SML0DAT R762 1 2 2.2K_0402_5% 2009/02/04 2010/02/04 Title
Issued Date Deciphered Date
3/16 Add R761/R762 to 2.2K
PCH (2/9) PCIE, SMBUS, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
ohm(follow Intel's comment) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 25 of 61
5 4 3 2 1
5 4 3 2 1
DMI_HTX_PRX_N[0..3]
5 DMI_HTX_PRX_N[0..3]
DMI_HTX_PRX_P[0..3]
5 DMI_HTX_PRX_P[0..3]
DMI_PTX_HRX_N[0..3]
5 DMI_PTX_HRX_N[0..3]
DMI_PTX_HRX_P[0..3]
5 DMI_PTX_HRX_P[0..3]
D U18C 08/20 ADD D
FDI_CTX_PRX_N0
DMI_HTX_PRX_N0 BC24
REV1.0 FDI_RXN0 BA18
BH17 FDI_CTX_PRX_N1 FDI for SG
DMI_HTX_PRX_N1 DMI0RXN FDI_RXN1 FDI_CTX_PRX_N2
BJ22 DMI1RXN FDI_RXN2 BD16
DMI_HTX_PRX_N2 AW20 BJ16 FDI_CTX_PRX_N3
DMI_HTX_PRX_N3 DMI2RXN FDI_RXN3 FDI_CTX_PRX_N4
BJ20 DMI3RXN FDI_RXN4 BA16
+3VS BE14 FDI_CTX_PRX_N5
FDI_RXN5 FDI_CTX_PRX_N[0..7] 5
DMI_HTX_PRX_P0 BD24 BA14 FDI_CTX_PRX_N6
DMI0RXP FDI_RXN6 FDI_CTX_PRX_P[0..7] 5
DMI_HTX_PRX_P1 BG22 BC12 FDI_CTX_PRX_N7
DMI_HTX_PRX_P2 DMI1RXP FDI_RXN7
BA20 DMI2RXP
1 2 PM_CLKRUN# DMI_HTX_PRX_P3 BG20 BB18 FDI_CTX_PRX_P0
R416 8.2K_0402_5% DMI3RXP FDI_RXP0 FDI_CTX_PRX_P1
FDI_RXP1 BF17
1 2 XDP_DBRESET# DMI_PTX_HRX_N0 BE22 BC16 FDI_CTX_PRX_P2
R417 @ 10K_0402_5% DMI_PTX_HRX_N1 DMI0TXN FDI_RXP2 FDI_CTX_PRX_P3
BF21 DMI1TXN FDI_RXP3 BG16
DMI_PTX_HRX_N2 BD20 AW16 FDI_CTX_PRX_P4
DMI_PTX_HRX_N3 DMI2TXN FDI_RXP4 FDI_CTX_PRX_P5
BE18 DMI3TXN FDI_RXP5 BD14
BB14 FDI_CTX_PRX_P6
DMI_PTX_HRX_P0 FDI_RXP6 FDI_CTX_PRX_P7
BD22 DMI0TXP FDI_RXP7 BD12
DMI_PTX_HRX_P1 BH21
+3VALW DMI_PTX_HRX_P2 DMI1TXP
BC20 DMI2TXP
DMI_PTX_HRX_P3 BD18 BJ14 FDI_INT
+1.05VS DMI3TXP FDI_INT FDI_INT 5
DMI
FDI
1 2 SUS_PWR_ACK BF13 FDI_FSYNC0
FDI_FSYNC0 FDI_FSYNC0 5
R419 10K_0402_5% R420 BH25
PCH_GPIO72 49.9_0402_1% DMI_ZCOMP FDI_FSYNC1
1 2 FDI_FSYNC1 BH13 FDI_FSYNC1 5
R421 8.2K_0402_5% 1 2 DMI_COMP BF25
EC_SWI# DMI_IRCOMP FDI_LSYNC0
1 2 FDI_LSYNC0 BJ12 FDI_LSYNC0 5
R422 10K_0402_5%
1 2 PCH_PCIE_WAKE# BG14 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 5
C R423 1K_0402_5% C
1 2 PM_SLP_LAN#
R425 @ 10K_0402_5%
XDP_DBRESET# T6 J12 PCH_PCIE_WAKE#
6 XDP_DBRESET# SYS_RESET# WAKE# PCH_PCIE_WAKE# 35,37
SYS_PWROK R426 2 1 0_0402_5% SYS_PWROK_R M6 Y1 PM_CLKRUN#
VGATE R427 2 @ SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# 39,47
1 0_0402_5%
System Power Management
SYS_PWROK B17 PWROK
1 R767 2 MEPWROK K5 P8 SUS_STAT#
MEPWROK SUS_STAT# / GPIO61 SUS_STAT# 47
0_0402_5%
3/24 Add
LAN_RST# A10 F3 PCH_GPIO62 @ PAD
LAN_RST# SUSCLK / GPIO62 T18
6 PM_DRAM_PWRGD D9 DRAMPWROK SLP_S5# / GPIO63 E4 PM_SLP_S5# 39
PCH_RSMRST# C16 H7
RSMRST# SLP_S4# PM_SLP_S4# 39
SUS_PWR_ACK M1 P12
B 39 SUS_PWR_ACK SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# 39 B
10/2 Intel suggestion change to 10K
PBTN_OUT# P5 K8 PM_SLP_M# @ PAD
6,39 PBTN_OUT# PWRBTN# SLP_M# T19
+3VALW 1 2 R429 2 @ 1 0_0402_5%
R428 10K_0402_5% Q15
1 2 PCH_ACIN P7 N2 PM_SLP_DSW# @ PAD MMBT3906_SOT23-3
39 EC_ACIN ACPRESENT / GPIO31 TP23 T20
D19 PCH_RSMRST# 1 3
C
EC_RSMRST# 39
CH751H-40PT_SOD323-2
E
PCH_GPIO72 A6 BJ10
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 6
B
2
R430 1 2 +3VALW
EC_SWI# F14 F6 PM_SLP_LAN# 10K_0402_5% R431 4.7K_0402_5%
39 EC_SWI# RI# SLP_LAN# / GPIO29
D20A
2
@ IBEXPEAK-M_FCBGA1071~D 1
R432 2 1 0_0402_5% @ 4/2 Add by Vivian 6
R725 2 1 0_0402_5% 2
+3VS C866
+3VS VGATE @ 1 2 100P_0402_50V8J BAV99DW-7_SOT363
5
U21 U41 C867 D20B
2 ICH_PWROK 2 H_PM_SYNC @ 1 2 100P_0402_50V8J 4
P
B ICH_PWROK 39 B VR_ON_EC 39
SYS_PWROK 4 4 3
Y 57 VR_ON Y
1 VGATE 1 C868 5
A VGATE 23,57 A PWR_GD 43
G
1
PBTN_OUT# @ 1 2 100P_0402_50V8J
NC7SZ08P5X_NL_SC70-5 NC7SZ08P5X_NL_SC70-5 BAV99DW-7_SOT363 R433
3
2.2K_0402_5%
C862
VR_ON @ 1 2 100P_0402_50V8J
2
A A
SYS_PWROK 1 2
R434 10K_0402_5%
ICH_PWROK 1 2
R435 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
LAN_RST# 1
R436
2
10K_0402_5% PCH (3/9) DMI, FDI, PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
No used Integrated LAN, Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
connecting LAN_RST# to GND DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 26 of 61
5 4 3 2 1
5 4 3 2 1
U18D
22 PCH_ENBKL T48 L_BKLTEN SDVO_TVCLKINN BJ46
22 PCH_ENVDD T47 L_VDD_EN SDVO_TVCLKINP BG46
D 22 PCH_INV_PWM Y48 L_BKLTCTL SDVO_STALLN BJ48 D
SDVO_STALLP BG48
22 PCH_LVDS_SCL AB48 L_DDC_CLK
22 PCH_LVDS_SDA Y45 L_DDC_DATA SDVO_INTN BF45
SDVO_INTP BH45
1 2 AB46 L_CTRL_CLK
PCH_ENBKL +3VS 1R1306 2 10K_0402_5% V48
R1307 10K_0402_5% L_CTRL_DATA
AP39 LVD_IBG SDVO_CTRLCLK T51
2
AP41 LVD_VBG SDVO_CTRLDATA T53
1
R356 T110 PAD
100K_0402_1% R1308 R338 1 2 0_0402_5% AT43
2.37K_0402_1% UMA@ LVD_VREFH
AT42 LVD_VREFL DDPB_AUXN BG44
BJ44
1
UMA@ DDPB_AUXP
AU38
2
DDPB_HPD
LVDS
22 PCH_LVDS_ACLK# AV53 LVDSA_CLK#
AV51 BD42 +3VS
22 PCH_LVDS_ACLK LVDSA_CLK DDPB_0N
DDPB_0P BC42
22 PCH_LVDS_A0# BB47 LVDSA_DATA#0 DDPB_1N BJ42
BA52 BG42
Digital Display Interface
22 PCH_LVDS_A1# LVDSA_DATA#1 DDPB_1P
1
AY48 BB40 UMA@ UMA@
22 PCH_LVDS_A2# LVDSA_DATA#2 DDPB_2N
AV47 BA40 R1310 R1311
LVDSA_DATA#3 DDPB_2P 2.2K_0402_5% 2.2K_0402_5%
DDPB_3N AW38
22 PCH_LVDS_A0 BB48 LVDSA_DATA0 DDPB_3P BA38
22 PCH_LVDS_A1 BA50
2
LVDSA_DATA1
22 PCH_LVDS_A2 AY49 LVDSA_DATA2
AV48 Y49 PCH_DDPCLK PCH_DDPCLK 20
LVDSA_DATA3 DDPC_CTRLCLK
DDPC_CTRLDATA AB49 PCH_DDPDAT PCH_DDPDATA 20
C AP48 C
22 PCH_LVDS_BCLK# LVDSB_CLK#
22 PCH_LVDS_BCLK AP47 LVDSB_CLK DDPC_AUXN BE44 2 R342 1UMA@
BD44 100K_0402_1%
DDPC_AUXP
22 PCH_LVDS_B0# AY53 LVDSB_DATA#0 DDPC_HPD AV40 PCH_HDMI_HPD 20
22 PCH_LVDS_B1# AT49 LVDSB_DATA#1
22 PCH_LVDS_B2# AU52 LVDSB_DATA#2 DDPC_0N BE40 PCH_HDMI_TX2- 20
AT53 LVDSB_DATA#3 DDPC_0P BD40 PCH_HDMI_TX2+ 20
DDPC_1N BF41 PCH_HDMI_TX1- 20
22 PCH_LVDS_B0 AY51 LVDSB_DATA0 DDPC_1P BH41 PCH_HDMI_TX1+ 20
22 PCH_LVDS_B1 AT48 LVDSB_DATA1 DDPC_2N BD38 PCH_HDMI_TX0- 20
22 PCH_LVDS_B2 AU50
AT51
LVDSB_DATA2
LVDSB_DATA3
DDPC_2P
DDPC_3N
BC38
BB36
PCH_HDMI_TX0+
PCH_HDMI_CLK-
HDMI
20
20
DDPC_3P BA36 PCH_HDMI_CLK+ 20
DAC_BLU AA52 U50
21 DAC_BLU CRT_BLUE DDPD_CTRLCLK
21 DAC_GRN
DAC_GRN AB53 CRT_GREEN DDPD_CTRLDATA U52 HDMI SWAP DDPC0 <-> DDPC2
DAC_RED AD53
21 DAC_RED CRT_RED
DDPD_AUXN BC46
21 CRT_DDC_CLK V51 CRT_DDC_CLK DDPD_AUXP BD46
21 CRT_DDC_DATA V53 CRT_DDC_DATA DDPD_HPD AT38
DDPD_0N BJ40
21 CRT_HSYNC Y53 CRT_HSYNC DDPD_0P BG40
21 CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DAC_BLU BG38
DDPD_1P
1
CRT
DAC_GRN
UMA@ 150_0402_1%
DDPD_2N BF37
1
DAC_RED CRT_IREF AD48
150_0402_1%
DAC_IREF DDPD_2P BH37
1
B B
UMA@
R1324
150_0402_1%
AB51 CRT_IRTN DDPD_3N BE36
R1325
REV1.0 DDPD_3P BD36
R1326
2
IBEXPEAK-M_FCBGA1071~D
2
30mial far away from
other signal
UMA@
R437
0826
1K_0402_1%
2
Clapella DG 1.1 Page 197
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
PCH (4/9) LVDS, CRT, DPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 27 of 61
5 4 3 2 1
5 4 3 2 1
1 R438 2 0_0402_5%
U18E
+3VS H40
N34
AD0 REV1.0 NV_CE#0 AY9
BD1
AD1 NV_CE#1 +3VS
C44 AD2 NV_CE#2 AP15
R439 1 2 8.2K_0402_5% PCI_PIRQA# A38 BD8
R440 8.2K_0402_5% PCI_PIRQG# AD3 NV_CE#3
1 2 C36 AD4
5
R441 1 2 8.2K_0402_5% PCI_PIRQC# J34 AV9 U22
R442 8.2K_0402_5% PCI_SERR# AD5 NV_DQS0 PLT_RST#
1 2 A40 BG8 2 B
P
AD6 NV_DQS1
D45 AD7 Y 4 PLT_RST_BUF# 6,35,37,47
E36 AD8 NV_DQ0 / NV_IO0 AP7 1 A
G
H48 AD9 NV_DQ1 / NV_IO1 AP6
1
E40 AT6 NC7SZ08P5X_NL_SC70-5
3
AD10 NV_DQ2 / NV_IO2 @ R448
D C40 AD11 NV_DQ3 / NV_IO3 AT9 D
R443 1 2 8.2K_0402_5% PCI_PLOCK# M48 BB1 100K_0402_5%
R444 8.2K_0402_5% PCI_PERR# AD12 NV_DQ4 / NV_IO4
1 2 M45 AD13 NV_DQ5 / NV_IO5 AV6
R445 1 2 8.2K_0402_5% PCI_PIRQE# F53 BB3
2
R446 8.2K_0402_5% PCI_STOP# AD14 NV_DQ6 / NV_IO6
1 2 M40 AD15 NV_DQ7 / NV_IO7 BA4 1 R564 2 0_0402_5%
NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4
J36 AD17 NV_DQ9 / NV_IO9 BB6 CheckList1.0 1.23.2
K48 BD6 +3VS
AD18 NV_DQ10 / NV_IO10 Braidwood Disable
F40 AD19 NV_DQ11 / NV_IO11 BB7
C42 AD20 NV_DQ12 / NV_IO12 BC8
5
R447 1 2 8.2K_0402_5% PCI_REQ0# K46 BJ8 U37
R449 8.2K_0402_5% PCI_PIRQB# AD21 NV_DQ13 / NV_IO13 PLT_RST#
1 2 M51 BJ6 2 B
P
R450 8.2K_0402_5% PCI_PIRQF# AD22 NV_DQ14 / NV_IO14
1 2 J52 AD23 NV_DQ15 / NV_IO15 BG6 Y 4 PLT_RST_BUF1# 39,42
R451 1 2 8.2K_0402_5% PCI_REQ3# K51 1
AD24 A
G
L34 AD25 NV_ALE BD3 NV_ALE_R @ 1 R452 2 1K_0402_5% +1.8VS
1
F42 AY6 NV_CLE_R @ 1 R453 2 1K_0402_5% +3VS NC7SZ08P5X_NL_SC70-5
3
AD26 NV_CLE @ R650
J40 AD27
G46 @ 100K_0402_5%
R454 8.2K_0402_5% PCI_IRDY# AD28
1 2 F44 AD29 NV_RCOMP AU2 NV_RCOMP_R R455 32.4_0402_1%
R456 1 2 8.2K_0402_5% PCI_PIRQD# M47 @
2
AD30
PCI
R457 1 2 8.2K_0402_5% DGPU_SELECT# H36 AV7
R458 8.2K_0402_5% PCI_DEVSEL# AD31 NV_RB#
1 2 3/16 Follow Intel's comment
J50 C/BE0# NV_WR#0_RE# AY8
2
G42 AY5 DISO@
C/BE1# NV_WR#1_RE# R840 +3VS
H47 C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11 0_0402_5%
R459 1 2 8.2K_0402_5% PCI_FRAME# BF5
NV_WE#_CK1
5
R460 1 2 8.2K_0402_5% PCI_REQ1# PCI_PIRQA# G38 U42
1
R461 8.2K_0402_5% PCI_PIRQH# PCI_PIRQB# PIRQA# PLT_RST# 2
1 2 H51
P
C R462 8.2K_0402_5% PCI_TRDY# PCI_PIRQC# PIRQB# USB20_N0 B C
1 2 B37 PIRQC# USBP0N H18 USB20_N0 42 Y 4 PLTRST_VGA# 13
PCI_PIRQD# A44 J18 USB20_P0 USB(I/0 B) 1
PIRQD# USBP0P USB20_P0 42 29 DGPU_HOLD_RST# A
G
A18 USB20_N1
USBP1N USB20_N1 47
1
PCI_REQ0# F51 C18 USB20_P1 FPR NC7SZ08P5X_NL_SC70-5
3
PCI_REQ1# REQ0# USBP1P USB20_N2 USB20_P1 47 DIS@ R839
A46 REQ1# / GPIO50 USBP2N N20 USB20_N2 22
DGPU_SELECT# B45 P20 USB20_P2 Camera DIS@ 100K_0402_5%
20,22 DGPU_SELECT# REQ2# / GPIO52 USBP2P USB20_P2 22 New add in 0824
PCI_REQ3# M53 J20 USB20_N3 EHCI 1
REQ3# / GPIO54 USBP3N USB20_P3 USB20_N3 37
L20 TV
2
PCI_GNT0# USBP3P USB20_N4 USB20_P3 37
F48 GNT0# USBP4N F20 USB20_N4 42
PCI_GNT1# USB20_P4
DIS GPU select, low active DGPU_PWMSEL#
K45
F36
GNT1# / GPIO51 USBP4P G20
A20 USB20_N5 USB20_P4 42 USB(I/0 B)
22 DGPU_PWMSEL# GNT2# / GPIO53 USBP5N USB20_N5 42
L: to VGA chip PCI_GNT3# H53 GNT3# / GPIO55 USBP5P C20 USB20_P5
USB20_P5 42 USB(I/0 B)
USBP6N M22
H: to PCH PCI_PIRQE# B41 PIRQE# / GPIO2 USBP6P N22
PCI_PIRQF# K53 B21
PCI_PIRQG# PIRQF# / GPIO3 USBP7N
A36 PIRQG# / GPIO4 USBP7P D21
PCI_PIRQH# A48 H22 USB20_N8
PIRQH# / GPIO5 USBP8N USB20_P8 USB20_N8 37
USBP8P J22 USB20_P8 37 WLAN
USB
@ TP_PCI_RST# K6 E22 USB20_N9
T21 PAD PCIRST# USBP9N USB20_N9 42
F22 USB20_P9 USB 2(IO/B)
PCI_SERR# USBP9P USB20_N10 USB20_P9 42
E44 SERR# USBP10N A22 USB20_N10 41
PCI_PERR# E50 C22 USB20_P10 BT
PERR# USBP10P USB20_N11 USB20_P10 41
USBP11N G24 USB20_N11 34
H24 USB20_P11 CardReader
PCI_IRDY# USBP11P USB20_P11 34
A42 IRDY# USBP12N L24
H44 M24 EHCI 2 Danbury Technology Enabled
PCI_DEVSEL# PAR USBP12P
F46 DEVSEL# USBP13N A24
PCI_FRAME# C46 C24
FRAME# USBP13P
B
High = Enabled B
PCI_PLOCK# D49 PLOCK#
NV_ALE
USBRBIAS# B25 USB_BIAS 1 2 Low = Disabled
PCI_STOP# D41 R463
PCI_TRDY# STOP# 22.6_0402_1%
C48 TRDY# USBRBIAS D25
modify on 08/20 PCI_PME# M7
39 PCI_PME# PME#
OC0# / GPIO59 N16 USB_OC#0
USB_OC#0 42 DMI Termination Voltage
PLT_RST# D5 J16
PLTRST# OC1# / GPIO40 USB_OC#2
OC2# / GPIO41 F16 USB_OC#2 42
N52 CLKOUT_PCI0 OC3# / GPIO42 L16 USB_OC#3 Set to Vss when LOW
47 CLK_PCI_TPM
R464 1 2 22_0402_5% CLK_PCI_TPM_R P53 CLKOUT_PCI1 OC4# / GPIO43 E14 USB_OC#4
USB_OC#4 42 NV_CLE
39 CLK_PCI_EC
R465 1 2 22_0402_5% CLK_PCI_EC_R P46 CLKOUT_PCI2 OC5# / GPIO9 G16 USB_OC#5 Set to Vcc when HIGH
R466 1 2 22_0402_5% CLK_PCI_DB_R P51 F12 USB_OC#6
42 CLK_PCI_DB CLKOUT_PCI3 OC6# / GPIO10
R467 1 2 22_0402_5% CLK_PCI_FB_R P48 T15 USB_OC#7
25 CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14
2008/1/6 2009MOW01 change to 22 ohm IBEXPEAK-M_FCBGA1071~D RP5
OC[0..3] use for EHCI 1 USB_OC#3 1 8 +3VALW
OC[4..7] use for EHCI 2 USB_OC#5 2 7
USB_OC#6 3 6
Have internal PU USB_OC#7 4 5
Boot BIOS Strap
PCI_GNT0# R468 1 2 1K_0402_5% 10K_1206_8P4R_5%
PCI_GNT#0 PCI_GNT#1 Boot BIOS Location @
PCI_GNT1# R469 1 2 1K_0402_5%
0 0 LPC Have internal PU @
0 1 Reserved (NAND)
A
PCI_GNT3# R470 1 2 1K_0402_5% A
1 0 PCI Have internal PU @
* 1 1 SPI
A16 swap override Strap/Top-Block Security Classification Compal Secret Data Compal Electronics, Inc.
Swap Override jumper Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
PCI_GNT#3 Low = A16 swap PCH (5/9) PCI, USB, VRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
High = Default AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 28 of 61
5 4 3 2 1
5 4 3 2 1
+3VS
U18F
R471 1 2 10K_0402_5% PCH_GPIO0 PCH_GPIO0 Y3 AH45
R472 1 BMBUSY# / GPIO0 CLKOUT_PCIE6N
2 10K_0402_5% DGPU_EDIDSEL# CLKOUT_PCIE6P AH46
R473 1 2 10K_0402_5% PCH_GPIO6 DGPU_EDIDSEL# C38
20,21,22 DGPU_EDIDSEL# TACH1 / GPIO1
R475 1 2 10K_0402_5% PCH_GPIO38 PCH_GPIO6 D37
R476 10K_0402_5% PCH_TEMP_ALERT TACH2 / GPIO6
D 1 2 CLKOUT_PCIE7N AF48 D
MISC
R484 1 2 10K_0402_5% CARD_RST#_R EC_SCI# J32 AF47 +3VS
39 EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
R737 1 2 10K_0402_5% DGPU_PWR_EN
R479 1 2 10K_0402_5% PCH_GPIO48 EC_SMI# F10
39 EC_SMI# GPIO8
R485 1 2 10K_0402_5% PCH_GPIO39 GATEA20 R478 1 2 10K_0402_5%
PCH_GPIO12
(GPIO8 Should not be Pull-Low) GATEA20
K9 LAN_PHY_PWR_CTRL / GPIO12 A20GATE U2 GATEA20 39
KB_RST# R486 1 2 10K_0402_5%
R487 1 2 10K_0402_5% EC_SCI# PCH_GPIO15 T7
SG@ 0_0402_5% GPIO15
28 DGPU_HOLD_RST# 1 2 R852 AA2 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLK_CPU_BCLK# 6
DGPU_PWROK_BUF F38 AM1
43 DGPU_PWROK_BUF TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK 6
+3VALW PROJECT_ID3 Y7 BG10
SCLOCK / GPIO22 PECI H_PECI 6
GPIO
R481 1 2 10K_0402_5% PCH_GPIO12 H10 T1 KB_RST#
GPIO24 RCIN# KB_RST# 39
R488 1 2 10K_0402_5% EC_SMI#
PCH_GPIO27 AB12 BE10
GPIO27 PROCPWRGD H_CPUPWRGD 6
CPU
R489 1 2 1K_0402_5% PCH_GPIO15
10/7 Not Use PCH_GPIO15 PU 1K to +3V PCH_GPIO28 V13 BD10 THRMTRIP_PCH# 2 1 H_THERMTRIP#
H_THERMTRIP# 6
GPIO28 THRMTRIP# R490 56_0402_5%
PROJECT_ID2 M11 2 1 +1.1VS_VTT
STP_PCI# / GPIO34 R491 56_0402_5%
R492 1 2 10K_0402_5% PCH_GPIO28 PCH_GPIO35 V6
R493 10K_0402_5% PCH_GPIO57 SATACLKREQ# / GPIO35
1 2
R494 1 2 10K_0402_5% PCH_GPIO45 DGPU_PWR_EN AB7 BA22
25,43,48 DGPU_PWR_EN SATA2GP / GPIO36 TP1
R495 1 2 10K_0402_5% PCH_GPIO46 WW46 Platform/Design Updates
CARD_RST#_R AB13 AW22
34 CARD_RST#_R SATA3GP / GPIO37 TP2 2008/11/17 54.9 1% ->56 5%
C PCH_GPIO38 V3 BB22 C
R496 1 SLOAD / GPIO38 TP3
2 10K_0402_5% PCH_GPIO35
PCH_GPIO39 P3 AY45
SDATAOUT0 / GPIO39 TP4
R497 1 @ 2 1K_0402_5% PCH_GPIO27 PCH_GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5
2/26 Change value and symbol to 1K ohm PCH_GPIO46 F1 AV43
PCIECLKRQ7# / GPIO46 TP6
GPIO27 (Have internal Pull-High) PCH_GPIO48 AB6 AV45
SDATAOUT1 / GPIO48 TP7
High: VCCVRM VR Enable PCH_TEMP_ALERT AA4 AF13
39 PCH_TEMP_ALERT SATA5GP / GPIO49 TP8
Low: VCCVRM VR Disable
PCH_GPIO57 F8 M18
GPIO57 TP9
TP10 N18
3/20 Modify By Vivian A4 VSS_NCTF_1 TP11 AJ24
A49
NCTF
VSS_NCTF_2
RSVD
+3VS R482 1 @ 2 10K_0402_5% A5 AK41
R765 1 VSS_NCTF_3 TP12
2 10K_0402_5% PROJECT_ID2 A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
A53 VSS_NCTF_6
B2 VSS_NCTF_7 TP14 M32
B4 VSS_NCTF_8
+3VS R483 1 @ 2 10K_0402_5% B52 N32
R766 1 VSS_NCTF_9 TP15
2 10K_0402_5% PROJECT_ID3 B53 VSS_NCTF_10
BE1 VSS_NCTF_11 TP16 M30
BE53 VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
B B
BF53 VSS_NCTF_14
BH1 VSS_NCTF_15 TP18 H12
BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
BJ49 VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39
D2 VSS_NCTF_28
D53 VSS_NCTF_29
E1 P6 INIT3_3V# @ PAD T22
VSS_NCTF_30 INIT3_3V#
E53 VSS_NCTF_31 TP24_SST @
REV1.0 TP24 C10 PAD T23
IBEXPEAK-M_FCBGA1071~D
2/28 Follow Module design Rev1.0
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
PCH (6/9) GPIO, CPU, MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 29 of 61
5 4 3 2 1
5 4 3 2 1
+1.05VS +3VS
10U_0805_10V4Z 1U_0402_6.3V4Z
U18G POWER +VCCADAC 0.01U_0402_16V7K 10U_0805_10V4Z
60mA
AB24 VCCCORE[1] VCCADAC[1] AE50 1 2
1 1 AB26 1 1 1 L54
VCCCORE[2]
1
D Intel suggest follow CRB 8/21 AB28 69mA AE52 C543 C544 MBK1608601YZF_2P D
VCCCORE[3] VCCADAC[2]
C541 C542 AD26 VCCCORE[4]1524mA
R498 C545 600 ohm bead,350mA
CRT
2 2
AD28 VCCCORE[5] VSSA_DAC[1] AF53 0_0402_5%
2
Near
2
AE50 2
AF26 @
VCCCORE[6]
VCC CORE
AF28 AF51
2
VCCCORE[7] VSSA_DAC[2]
Near AB24 Near AB24 AF30 VCCCORE[8]
0.1U_0402_16V4Z CRB 0.9 is 180 ohm @ 100MHz
Top Side AF31 VCCCORE[9] DG0.8 is 600 ohm FB (Page 290)
AH26 VCCCORE[10]
AH28 +3VS
VCCCORE[11] UMA@
AH30 VCCCORE[12] 300mA R771 1
AH31 VCCCORE[13] VCCALVDS AH38 2 0_0805_5%
All Ibex Peak-M Power rails with netnames +1.1VS and AJ30 R860
VCCCORE[14]
AJ31 AH39 1 2
+1.1V rails are actually +1.05VS and +1.05V rails VCCCORE[15] VSSA_LVDS DISO@ 0_0402_5%
UMA@ +1.8VS
+1.05VS 59mA
AP43 1 2
0.01U_0402_16V7K
VCCTX_LVDS[1] L82
AP45
22U_0805_6.3V6M
1 1 1
0.01U_0402_16V7K
VCCTX_LVDS[2]
1
+1.05VS AT46 MBK1608601YZF_2P
LVDS
VCCTX_LVDS[3] R838
AK24 VCCIO[24] VCCTX_LVDS[4] AT45
C649
C650
C759
0_0402_5%
2 2 2
UMA@
UMA@
@ 42mA DISO@
New add to enable LVDS for SG Board
UMA@
L55 1 2 +VCCAPLL_EXP BJ24
2
1UH_CBC2012T1R0M_20% VCCAPLLEXP 0826
1 VCC3_3[2] AB34
1uH inductor, 405mA C546
AN20 VCCIO[25] VCC3_3[3] AB35
10U_0805_10V4Z AN22
HVCMOS
2 @ VCCIO[26]
DG 0.8 is 1uH Inductor (Page 291) AN23 AD35 +3VS
Have Internal VRM (DG0.8 Page 293) VCCIO[27] VCC3_3[4]
AN24 VCCIO[28]
AN26 VCCIO[29] 1
C AN28 C547 C
VCCIO[30]
BJ26 VCCIO[31]
BJ28 VCCIO[32]
0.1U_0402_16V4Z
2
Near AB34
AT26 VCCIO[33]
AT28 R499 1@ 2 0_0805_5% +1.05VS
VCCIO[34]
AU26 VCCIO[35]
+1.05VS AU28 +VCCVRM R500 1@ 2 0_0805_5%
VCCIO[36] +1.5VS
AV26 VCCIO[37] 35mA
Near AN20 AV28 VCCIO[38] VCCVRM[2] AT24 R501 1 2 0.022_0805_1% +1.8VS
10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z AW26 3208mA
VCCIO[39]
1 1 1 1 1 AW28 VCCIO[40] 61mA +1.1VS_VTT
DMI
BA26 VCCIO[41] VCCDMI[1] AT16
C548 C549 C550 C551 C552 BA28 VCCIO[42] +VCC_DMI R502 1
BB26 VCCIO[43] VCCDMI[2] AU16 2 0.022_0805_1%
2 2 2 2 2
BB28 VCCIO[44] 1
Top Side BC26 +1.05VS
VCCIO[45]
PCI E*
1U_0402_6.3V4Z 1U_0402_6.3V4Z BC28 C553
VCCIO[46] 1U_0402_6.3V4Z R503 1
BD26 VCCIO[47] 2 0.022_0805_1%
2 @
BD28 VCCIO[48] 156mA
BE26 VCCIO[49] VCCPNAND[1] AM16 Near AT16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 VCCIO[52] VCCPNAND[4] AK19
Near AN35 BH27 VCCIO[53] VCCPNAND[5] AK15
+VCCQ_NAND +1.8VS
VCCPNAND[6] AK13
+3VS AN30 AM12
VCCIO[54] VCCPNAND[7]
Follow Intel suggestion 8/21
NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
AM15 R504 1 2 0.022_0805_1%
0.1U_0402_16V4Z VCCPNAND[9]
B
1 B
C554 2 1 AN35 C555
VCC3_3[1]
+1.05VS 0.1U_0402_16V4Z
2
+VCCVRM AT22 VCCVRM[1]
85mA Near AK13
L56 1 2 +VCCAPLL_FDI BJ18 6mA AM8
1UH_CBC2012T1R0M_20% VCCFDIPLL VCCME3_3[1] +3VS
1 VCCME3_3[2] AM9
FDI
1uH inductor,
@ 405mA +1.05VS AM23 AP11
C556 @ VCCIO[1] VCCME3_3[3]
VCCME3_3[4] AP9
Change to 0 ohm 10U_0805_10V4Z 1
for discrete 2 C557
REV1.0
IBEXPEAK-M_FCBGA1071~D 0.1U_0402_16V4Z
2
Near AM8
DG 0.8 is 1uH Inductor (Page 291)
Have Internal VRM (DG0.8 Page 293)
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
PCH (7/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 30 of 61
5 4 3 2 1
5 4 3 2 1
+1.05VS U18J POWER
DG 0.8 is 10uH Inductor (Page 290) L59 1 2 +1.1VS_VCCACLK AP51
52mA REV1.0 V24
VCCACLK[1] VCCIO[5] +1.05VS
Have Internal VRM (DG0.8 Page 293) 10UH_LB2012T100MR_20% 1 1 VCCIO[6] V26 1
10uH inductor, 120mA AP53 Y24 +1.05VS +VCCADPLLA
@ VCCACLK[2] VCCIO[7]
C558 C559 Y26 C570
10U_0805_10V4Z 1U_0402_6.3V4Z VCCIO[8] 1U_0402_6.3V4Z
+1.05VS 2 @ 2
344mA 2
@ AF23 VCCLAN[1] VCCSUS3_3[1] V28
+3VALW
Near BB51
Near AP51 VCCSUS3_3[2] U28 Near V24 L57 1 2
R505 1 2 +VCCLAN AF24 U26 10UH_LB2012T100MR_20%
VCCLAN[2] VCCSUS3_3[3]
0_0603_5% @ 1 VCCSUS3_3[4] U24 10uH inductor, 120mA
1 1
1
P28 1 1 R506
VCCSUS3_3[5]
1
D R507 C560 +PCH_VCCD6W Y20 P26 C561 C571 + C562 0_0402_5% D
0_0402_5% 1U_0402_6.3V4Z DCPSUSBYP VCCSUS3_3[6] C572 1U_0402_6.3V4Z @
1 VCCSUS3_3[7] N28
@ 2 C563 1998mA N26 0.1U_0402_16V4Z 0.1U_0402_16V4Z 220U_B2_2.5VM_R35 2
VCCSUS3_3[8] 2 2 2
AD38 M28
2
VCCME[1] VCCSUS3_3[9]
0.1U_0402_16V4Z M26 Near A26 Near U23
2
2 VCCSUS3_3[10] +VCCADPLLB
Near AF23 AD39 L28
USB
VCCME[2] VCCSUS3_3[11]
VCCSUS3_3[12] L26
Near Y20 AD41 VCCME[3] VCCSUS3_3[13] J28
J26 L58 1 2
+1.05VS VCCSUS3_3[14]
Follow Intel suggestion AF43 H28 10UH_LB2012T100MR_20%
VCCME[4] VCCSUS3_3[15]
H26 10uH inductor, 120mA 1 1
22U_0805_6.3V6M VCCSUS3_3[16]
AF41 VCCME[5] 163mA VCCSUS3_3[17] G28
+ C573
1 1 1 1 1 VCCSUS3_3[18] G26
AF42 F28 C564 1U_0402_6.3V4Z
C565 C566 C567 C568 C569 VCCME[6] VCCSUS3_3[19] 220U_B2_2.5VM_R35 2
VCCSUS3_3[20] F26
+3VALW 2
2 2 2
22U_0805_6.3V6M
2 2
V39 VCCME[7] VCCSUS3_3[21] E28 Near BD51
1U_0402_6.3V4Z E26
Clock and Miscellaneous
VCCSUS3_3[22] D21
V41 VCCME[8] VCCSUS3_3[23] C28
2
22U_0805_6.3V6M Near AD38 1U_0402_6.3V4Z Near V39 VCCSUS3_3[24] C26 CH751H-40PT_SOD323-2
V42 VCCME[9] VCCSUS3_3[25] B27
VCCSUS3_3[26] A28 Follow Intel
Y39 VCCME[10] VCCSUS3_3[27] A26 Suggestion 8/21
All Ibex Peak-M Power rails with netnames +1.1VS and +1.05VS
1
Y41 U23 +3VS
+1.1V rails are actually +1.05VS and +1.05V rails VCCME[11] VCCSUS3_3[28] +5VALW
Y42 VCCME[12] VCCIO[56] V23
2
R508 D22
Near V9 C574 >1mA V5REF_SUS F24 +VCC5REFSUS 1 2 100_0402_5% CH751H-40PT_SOD323-2
0.1U_0402_16V4Z Follow Intel
C 1 2 +VCCRTCEXT V9 2 1 C575 Suggestion 8/21 C
DCPRTC 1U_0402_6.3V6K R509
1
>1mA Near F24 100_0402_5%
K49 +VCC5REF 1 2 +5VS
V5REF
+VCCVRM AU24 VCCVRM[3]
Change to 1U for power
PCI/GPIO/LPC
357mA sequence issue on ICH9 2 1 C576
72mA J38 1U_0402_6.3V6K
VCC3_3[8]
+VCCADPLLA BB51 VCCADPLLA[1] Near K49
BB53 VCCADPLLA[2] VCC3_3[9] L38
+3VS
73mA VCC3_3[10] M36
+VCCADPLLB BD51 VCCADPLLB[1]
+1.05VS BD53 N36
VCCADPLLB[2] VCC3_3[11]
Near AF32 Near AH23 1
AH23 P36 C577
VCCIO[21] VCC3_3[12]
AJ35 VCCIO[22]
1 1 1 AH35 U35 0.1U_0402_16V4Z
C579 C580 VCCIO[23] VCC3_3[13] 2 +3VS
C578 AF34 VCCIO[2] Near J38
1U_0402_6.3V4Z
2 2 2
1U_0402_6.3V4Z
VCC3_3[14] AD13 Near AD13 +1.05VS
AH34 VCCIO[3]
Near AH35 1 2 C581
1U_0402_6.3V4Z AF32 32mA 0.1U_0402_16V4Z
VCCIO[4] +VCCSATAPLL L60 1 @
VCCSATAPLL[1] AK3 2
1 2 +VCCSST V12 DCPSST VCCSATAPLL[2] AK1 1 1 10UH_LB2012T100MR_20% DG 0.8 is 10uH Inductor (Page 291)
C582 Near V12 10uH inductor, 120mA Have Internal VRM (DG0.8 Page 293)
0.1U_0402_16V4Z C583 C584
+1.05VS 10U_0805_10V4Z 1U_0402_6.3V4Z
+VCCSUS @ 2 @ 2
1 2 Y22 DCPSUS
B B
+3VALW
C585 Near Y22 VCCIO[9] AH22 Near AK1
0.1U_0402_16V4Z
P18 VCCSUS3_3[29] VCCVRM[4] AT20 +VCCVRM
1
C586 U19
SATA
VCCSUS3_3[30] +1.05VS
PCI/GPIO/LPC
VCCIO[10] AH19
0.1U_0402_16V4Z U20
2 VCCSUS3_3[31]
VCCIO[11] AD20
Near P18 U22 VCCSUS3_3[32]
VCCIO[12] AF22 1
+3VS
AD19 C587
VCCIO[13] 1U_0402_6.3V4Z
V15 VCC3_3[5] VCCIO[14] AF20
2
1 VCCIO[15] AF19
C588 V16 VCC3_3[6] VCCIO[16] AH20 Near AB19
0.1U_0402_16V4Z Y16 AB19
2 VCC3_3[7] VCCIO[17]
VCCIO[18] AB20
+1.1VS_VTT Near V15 AB22 +1.05VS
VCCIO[19]
> 1mA VCCIO[20] AD22
AT18 V_CPU_IO[1]
1 1 1 AA34 PCH_VCCME13 R510 1 2 0_0603_5%
CPU
C589 C590 C591 VCCME[13] PCH_VCCME14 R511 0_0603_5%
VCCME[14] Y34 1 2
AU18 Y35 PCH_VCCME15 R512 1 2 0_0603_5%
4.7U_0805_10V4Z 0.1U_0402_16V4Z V_CPU_IO[2] VCCME[15] PCH_VCCME16 R513 0_0603_5%
VCCME[16] AA35 1 2
2 2 2
0.1U_0402_16V4Z Near AT18 2mA 6mA
RTC
A A12 VCCRTC VCCSUSHDA L30 +3VALW A
HDA
C592 1 2 1U_0402_6.3V4Z
IBEXPEAK-M_FCBGA1071~D
+RTCVCC Near L30
1 1 1
C594 C595
C593 Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2009/02/04 2010/02/04 Title
2 2 2 Issued Date Deciphered Date
1U_0402_6.3V4Z
Near A12 PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.1U_0402_16V4Z Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 31 of 61
5 4 3 2 1
5 4 3 2 1
U18I U18H
AY7 VSS[159] VSS[259] H49 AB16 VSS[0]
B11 VSS[160] VSS[260] H5
B15 VSS[161] VSS[261] J24 AA19 VSS[1] VSS[80] AK30
B19 VSS[162] VSS[262] K11 AA20 VSS[2] VSS[81] AK31
B23 VSS[163] VSS[263] K43 AA22 VSS[3] VSS[82] AK32
B31 VSS[164] VSS[264] K47 AM19 VSS[4] VSS[83] AK34
B35 VSS[165] VSS[265] K7 AA24 VSS[5] VSS[84] AK35
B39 VSS[166] VSS[266] L14 AA26 VSS[6] VSS[85] AK38
B43 VSS[167] VSS[267] L18 AA28 VSS[7] VSS[86] AK43
B47 VSS[168] VSS[268] L2 AA30 VSS[8] VSS[87] AK46
B7 VSS[169] VSS[269] L22 AA31 VSS[9] VSS[88] AK49
D BG12 VSS[170] VSS[270] L32 AA32 VSS[10] VSS[89] AK5 D
BB12 VSS[171] VSS[271] L36 AB11 VSS[11] VSS[90] AK8
BB16 VSS[172] VSS[272] L40 AB15 VSS[12] VSS[91] AL2
BB20 VSS[173] VSS[273] L52 AB23 VSS[13] VSS[92] AL52
BB24 VSS[174] VSS[274] M12 AB30 VSS[14] VSS[93] AM11
BB30 VSS[175] VSS[275] M16 AB31 VSS[15] VSS[94] BB44
BB34 VSS[176] VSS[276] M20 AB32 VSS[16] VSS[95] AD24
BB38 VSS[177] VSS[277] N38 AB39 VSS[17] VSS[96] AM20
BB42 VSS[178] VSS[278] M34 AB43 VSS[18] VSS[97] AM22
BB49 VSS[179] VSS[279] M38 AB47 VSS[19] VSS[98] AM24
BB5 VSS[180] VSS[280] M42 AB5 VSS[20] VSS[99] AM26
BC10 VSS[181] VSS[281] M46 AB8 VSS[21] VSS[100] AM28
BC14 VSS[182] VSS[282] M49 AC2 VSS[22] VSS[101] BA42
BC18 VSS[183] VSS[283] M5 AC52 VSS[23] VSS[102] AM30
BC2 VSS[184] VSS[284] M8 AD11 VSS[24] VSS[103] AM31
BC22 VSS[185] VSS[285] N24 AD12 VSS[25] VSS[104] AM32
BC32 VSS[186] VSS[286] P11 AD16 VSS[26] VSS[105] AM34
BC36 VSS[187] VSS[287] AD15 AD23 VSS[27] VSS[106] AM35
BC40 VSS[188] VSS[288] P22 AD30 VSS[28] VSS[107] AM38
BC44 VSS[189] VSS[289] P30 AD31 VSS[29] VSS[108] AM39
BC52 VSS[190] VSS[290] P32 AD32 VSS[30] VSS[109] AM42
BH9 VSS[191] VSS[291] P34 AD34 VSS[31] VSS[110] AU20
BD48 VSS[192] VSS[292] P42 AU22 VSS[32] VSS[111] AM46
BD49 VSS[193] VSS[293] P45 AD42 VSS[33] VSS[112] AV22
BD5 VSS[194] VSS[294] P47 AD46 VSS[34] VSS[113] AM49
BE12 VSS[195] VSS[295] R2 AD49 VSS[35] VSS[114] AM7
BE16 VSS[196] VSS[296] R52 AD7 VSS[36] VSS[115] AA50
BE20 VSS[197] VSS[297] T12 AE2 VSS[37] VSS[116] BB10
BE24 VSS[198] VSS[298] T41 AE4 VSS[38] VSS[117] AN32
C BE30 T46 AF12 AN50 C
VSS[199] VSS[299] VSS[39] VSS[118]
BE34 VSS[200] VSS[300] T49 Y13 VSS[40] VSS[119] AN52
BE38 VSS[201] VSS[301] T5 AH49 VSS[41] VSS[120] AP12
BE42 VSS[202] VSS[302] T8 AU4 VSS[42] VSS[121] AP42
BE46 VSS[203] VSS[303] U30 AF35 VSS[43] VSS[122] AP46
BE48 VSS[204] VSS[304] U31 AP13 VSS[44] VSS[123] AP49
BE50 VSS[205] VSS[305] U32 AN34 VSS[45] VSS[124] AP5
BE6 VSS[206] VSS[306] U34 AF45 VSS[46] VSS[125] AP8
BE8 VSS[207] VSS[307] P38 AF46 VSS[47] VSS[126] AR2
BF3 VSS[208] VSS[308] V11 AF49 VSS[48] VSS[127] AR52
BF49 VSS[209] VSS[309] P16 AF5 VSS[49] VSS[128] AT11
BF51 VSS[210] VSS[310] V19 AF8 VSS[50] VSS[129] BA12
BG18 VSS[211] VSS[311] V20 AG2 VSS[51] VSS[130] AH48
BG24 VSS[212] VSS[312] V22 AG52 VSS[52] VSS[131] AT32
BG4 VSS[213] VSS[313] V30 AH11 VSS[53] VSS[132] AT36
BG50 VSS[214] VSS[314] V31 AH15 VSS[54] VSS[133] AT41
BH11 VSS[215] VSS[315] V32 AH16 VSS[55] VSS[134] AT47
BH15 VSS[216] VSS[316] V34 AH24 VSS[56] VSS[135] AT7
BH19 VSS[217] VSS[317] V35 AH32 VSS[57] VSS[136] AV12
BH23 VSS[218] VSS[318] V38 AV18 VSS[58] VSS[137] AV16
BH31 VSS[219] VSS[319] V43 AH43 VSS[59] VSS[138] AV20
BH35 VSS[220] VSS[320] V45 AH47 VSS[60] VSS[139] AV24
BH39 VSS[221] VSS[321] V46 AH7 VSS[61] VSS[140] AV30
BH43 VSS[222] VSS[322] V47 AJ19 VSS[62] VSS[141] AV34
BH47 VSS[223] VSS[323] V49 AJ2 VSS[63] VSS[142] AV38
BH7 VSS[224] VSS[324] V5 AJ20 VSS[64] VSS[143] AV42
C12 VSS[225] VSS[325] V7 AJ22 VSS[65] VSS[144] AV46
C50 VSS[226] VSS[326] V8 AJ23 VSS[66] VSS[145] AV49
D51 VSS[227] VSS[327] W2 AJ26 VSS[67] VSS[146] AV5
B B
E12 VSS[228] VSS[328] W52 AJ28 VSS[68] VSS[147] AV8
E16 VSS[229] VSS[329] Y11 AJ32 VSS[69] VSS[148] AW14
E20 VSS[230] VSS[330] Y12 AJ34 VSS[70] VSS[149] AW18
E24 VSS[231] VSS[331] Y15 AT5 VSS[71] VSS[150] AW2
E30 VSS[232] VSS[332] Y19 AJ4 VSS[72] VSS[151] BF9
E34 VSS[233] VSS[333] Y23 AK12 VSS[73] VSS[152] AW32
E38 VSS[234] VSS[334] Y28 AM41 VSS[74] VSS[153] AW36
E42 VSS[235] VSS[335] Y30 AN19 VSS[75] VSS[154] AW40
E46 VSS[236] VSS[336] Y31 AK26 VSS[76] VSS[155] AW52
E48 VSS[237] VSS[337] Y32 AK22 VSS[77] VSS[156] AY11
E6 VSS[238] VSS[338] Y38 AK23 VSS[78] VSS[157] AY43
E8
F49
VSS[239] VSS[339] Y43
Y46
AK28 VSS[79] REV1.0 VSS[158] AY47
VSS[240] VSS[340] IBEXPEAK-M_FCBGA1071~D
F5 VSS[241] VSS[341] P49
G10 VSS[242] VSS[342] Y5
G14 VSS[243] VSS[343] Y6
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
REV1.0
IBEXPEAK-M_FCBGA1071~D Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
PCH (9/9) VSS & PCH XDP Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 32 of 61
5 4 3 2 1
A B C D E F G H
SATA HDD Conn.
SATA ODD Conn.
+5VS
+3VS
1
Copy JAL90 Symbol 0.1U_0402_16V4Z 10U_0805_10V4Z 1
1 1 1 1 1
1
C596 C597 C598 C599 C600
1000P_0402_50V7K C601
2 2 2 2 2 0.1U_0402_16V4Z
JSATA1 2 @
Update Symbol
1U_0603_10V4Z 10U_0805_10V4Z
1 SP01000G800
SATA_ITX_C_DRX_P1_C_4 GND
+5VS SATA_ITX_C_DRX_N1_C_4
2
A+ FOX_LD2122H-S43_NR
3
C1224 0.01U_0402_16V7K A-
SATA_IRX_DTX_N1_C_2 1 SATA_IRX_DTX_N1_C_1
4
GND Manually update pin number
0.1U_0402_16V4Z 2 5
SATA_IRX_DTX_P1_C_2 1 SATA_IRX_DTX_P1_C_1 B-
2 6 B+
1 1 1 C1223 0.01U_0402_16V7K 7
GND
1000P_0402_50V7K
JSATA2
C602 C603 C604 1
GND
10U_0805_10V4Z
R514 1 @ 2 1K_0402_1% 8 SATA_ITX_C_DRX_P0 2
2 2 2 DP 24 SATA_ITX_C_DRX_P0 A+
9 SATA_ITX_C_DRX_N0 3
+5VS +5V 24 SATA_ITX_C_DRX_N0 A-
10 4
+5V SATA_DTX_C_IRX_N0 GND
11 24 SATA_DTX_C_IRX_N0 1 20.01U_0402_16V7K SATA_DTX_IRX_N0 5
MD SATA_DTX_C_IRX_P0 B-
12 15 24 SATA_DTX_C_IRX_P0
C605 1 20.01U_0402_16V7K SATA_DTX_IRX_P0 6
GND GND B+
13 14 7
GND GND C606 GND
SANTA_206401-1_13P 8
+3VS V33
CONN@ 9
V33
10
V33
Change ODD connector from OCTEK_SLS-13SB1G 11 GND
12
to SANTA_206401-1_13P GND
13
2 +3VS GND 2
+5VS 14
V5
15 V5
16
V5
4.7K_0402_5% R806
4.7K_0402_5%R809 4.7K_0402_5% R807
17
GND
2
18
Reserved
19
GND
20
V12
21 25
V12 GND
22 26
1
V12 GND
ODD_B0 FOX_LD2122H-S43_NR
ODD_B1 CONN@
4.7K_0402_5%R808
2
9/4 Change symbol follow KSWXX by Vivian
@ @
(NEW)
Change Library
1
+3VS
U12 1 2
7 6
EN VCC C829 C830
10
SATA_ITX_C_DRX_P1 VCC 0.1U_0402_16V4Z
24 SATA_ITX_C_DRX_P1 1 IN0P VCC 16 0.01U_0402_16V7K
SATA_ITX_C_DRX_N1 2 1
24 SATA_ITX_C_DRX_N1 2 20
C1218 0.01U_0402_16V7K IN0M VCC
SATA_DTX_C_IRX_N1 1 2 SATA_IRX_DTX_N1_C_3 4 9 ODD_B0
24 SATA_DTX_C_IRX_N1 OUT1M B0
SATA_DTX_C_IRX_P1 1 2 SATA_IRX_DTX_P1_C_3 5 8 ODD_B1
3 24 SATA_DTX_C_IRX_P1 OUT1P B1 3
C1217 0.01U_0402_16V7K C1215 0.01U_0402_16V7K
3 15 SATA_ITX_C_DRX_P1_C_3
1 2 SATA_ITX_C_DRX_P1_C_4
GND OUT0P SATA_ITX_C_DRX_N1_C_3 SATA_ITX_C_DRX_N1_C_4
18 14 1 2
GND OUT0M C1216 0.01U_0402_16V7K
13
GND SATA_IRX_DTX_P1_C_2
17 11
GND IN1P SATA_IRX_DTX_N1_C_2
19 12
GND IN1M
21
PAD
SN75LVCP412RTJR_TQFN20_4X4
0_0402_5%
SATA_ITX_C_DRX_P1 R760 2 @1 SATA_ITX_C_DRX_P1_R R253 2 1 @ 0_0402_5% SATA_ITX_C_DRX_P1_C_4
0_0402_5%
SATA_ITX_C_DRX_N1 R768 2 @1 SATA_ITX_C_DRX_N1_R R254 2 1 @ 0_0402_5% SATA_ITX_C_DRX_N1_C_4
0_0402_5%
SATA_DTX_C_IRX_N1 R778 2 @1 SATA_DTX_C_IRX_N1_R R255 2 1 @ 0_0402_5% SATA_IRX_DTX_N1_C_2
0_0402_5%
SATA_DTX_C_IRX_P1 R769 2 @1 SATA_DTX_C_IRX_P1_R R260 2 1 @ 0_0402_5% SATA_IRX_DTX_P1_C_2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
HDD & ODD Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 33 of 61
A B C D E F G H
5 4 3 2 1
SD,MMC,MS muti-function pin define
Realtek Recommend MDIO SD Card MMC Card MS Card
PIN Name PIN Name PIN Name PIN Name
MS_CLK SD_CLK SP1
MODE_SEL
1
SP2 SDWP#
1
1 R515 R517
C609 R516 @ @ SP3 SDCD#
@ 10_0402_5% 10_0402_5%
47P_0402_50V8J 0_0402_5% SP4 SDCDAT1 MSWR
2
2
2
D 1 1 SP5 MSBS D
C610 C611
+3VS_CR_VCC @ @ SP6 MSCDAT1
10P_0402_50V8J 10P_0402_50V8J
2 2
SP7 SDCDAT0 MSCDAT0
1 1 1 0.1U_0402_16V4Z
C612 2 2 SP8 SDCDAT7 MSCDAT2
C613 C614
1U_0603_10V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z C615 C616 U23 SP9 MS_INS#
2 2 2
0.1U_0402_16V4Z AV_PLL 1 1
1 SP10 SDCDAT6 MSCDAT3
AV_PLL
3 NC
7 NC SP11 SDCCLK MSCCLK
+VCC_OUT 9 AV_PLL 20mil (+1.8V internal regulator)
CARD_3V3
11 D3V3 SP12 SDCDAT5 MSCDAT6
33 10 AV_PLL
D3V3 VREG
MS_D4 22 SP13 SDCDAT4 MSCDAT7
NC 30
+3VS_CR_VCC 1 R518 2 0_0603_5% +3V3_IN 8 3V3_IN SP14
1 2 CARD_RST# 44
29 CARD_RST#_R RST#
+3VALW 1 @ 2 R519 MODE_SEL 45 SP15 SDCDAT3
R520 0_0603_5% MODE_SEL
1 C618 @ 0_0402_5% CARD_XTLO 47 XTLO XD_CLE_SP19 43
CARD_XTLI 48 42 SP16 SDCDAT2
C617 0.1U_0402_16V4Z XTLI XD_CE#_SP18
XD_ALE_SP17 41
+3VS_CR_VCC 4.7U_0805_10V4Z USB20_N11 4 40 SDDAT2_XDRE# SP17
2 28 USB20_N11 DM SD_DAT2/XD_RE#_SP16
28 USB20_P11 USB20_P11 5 39 SDDAT3_XDWE#
DP SD_DAT3/XD_WE#_SP15
14 GPIO0 XD_RDY_SP14 38 SP18
1
@ 37
R521 SD_DAT4/XD_WP#/MS_D7_SP13 R522 0_0402_5%
SD_DAT5/XD_D0/MS_D6_SP12 35 SP19
C 100K_0402_5% 34 SDCLK_MSCLK 1 2 SD_CLK C
SD_CLK/XD_D1/MS_CLK_SP11 SDDAT6_MSD3 R523 0_0402_5%
Internal 200K pull up SD_DAT6/XD_D7/MS_D3_SP10 31
29 MS_INS# 1 2 MS_CLK
2
MS_INS#_SP9
1 R524 2 CARD_RST#
SD_DAT7/XD_D2/MS_D2_SP8 28 SDDAT7_MSD2
0_0603_5% 27 SDDAT0_MSD0
SD_DAT0/XD_D6/MS_D0_SP7
1
C619 26 SP6
SD_DAT1/XD_D3/MS_D1_SP6 MS_BS +3VS_CR_VCC
XD_D5_SP5 25
R525 23 XDD4_SDDAT1
1U_0603_10V4Z 499K_0402_1% XD_D4/SD_DAT1_SP4 SD_CD# U24
SD_CD#_SP3 21
@ 20 SD_WP 8 1 CARD_EECS
2
SD_WP_SP2 +3VS_CR_VCC VCC CS CARD_EESK
XD_CD#_SP1 19 1 7 NC SK 2
18 CARD_EEDI 6 3 CARD_EEDO
EEDI C620 NC DI CARD_EEDI
5 GND DO 4
2 13 R526 1 2 0_0402_5% @
RREF XTAL_CTR
1
24 0.1U_0402_16V4Z 2 AT93C46-10SI-2.7_SO8
R527 MS_D5 @
12 DGND
@ 32 15 CARD_EEDO
Y8 DGND EEDO
6.19K_0402_1% 16 CARD_EECS
EECS
23 CLK_SD_48M 1 R528 2 CARD_XTLI 1 2 CARD_XTLO 6 17 CARD_EESK
2
0_0402_5% AGND1 AGND EESK SD_CMD
46 AGND SD_CMD 36
12MHZ_16P_6X12000012
JREAD1
1
R531 +VCC_3IN1 6 VDD_SD
25 CLK_SD_48M_PCH 1 R529 2 @ R530 S IC RTS5159-GR LQFP 48P CARD READER SDDAT0_MSD0 9 DAT0_SD
@ 0_0402_5% 270K_0402_5% 0_0402_5% XDD4_SDDAT1 10
SDDAT2_XDRE# DAT1_SD
1 1 2 DAT2_SD
C621 C622 2/17 Change Part number of U25 from SA00001NK10 to SA00002YP00 SDDAT3_XDWE# 3
2
@ @ SD_CLK CD/DAT3_SD
7 CLK_SD
6P_0402_50V8J 6P_0402_50V8J SD_WP 11
B 2 2 SD_CMD WP_SD B
4 CMD_SD
SD_CD# 1 CD_SD
5 VSS_SD
8 VSS_SD
4/2 Add by Vivian C878
100P_0402_50V8J 2 1 @ CLK_SD_48M SP6 19 VCC_MS
13 VCC_MS
MS_CLK 14
MS_INS# SCLK_MS
16 INS_MS
SDDAT0_MSD0 18
+VCC_3IN1 MS_BS SDIO_MS
20 BS_MS
SDDAT6_MSD3
40mil SDDAT7_MSD2
15
17
RESERVED_MS
+VCC_OUT RESERVED_MS
1 R532 2 21 VSS_MS
0_0603_5% 10U_0805_10V4Z 12 VSS_MS
1 1 22 GND
23 GND
C623 C624 C625
4.7U_0805_10V4Z @ PROCO_MDR019-C0-1202
2 2 0.1U_0402_16V4Z CONN@
+3VS
W=40mils
Add C822 4.7u and reserve C808 10u
1
A 1 for cost down Michael 2008/5/30 A
C626 C627 R533
@ @
0.1U_0402_16V4Z 1U_0603_10V4Z 0_0805_5%
3
S 2
2
G
1 @ 2 2
39 CR_ON#
R534 100K_0402_5% Q17
SI2301BDS_SOT23 Security Classification Compal Secret Data Compal Electronics, Inc.
@ 2009/02/04 2010/02/04 Title
D Issued Date Deciphered Date
W=40mils RTS5159 Cardreader
1
+3VS_CR_VCC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 34 of 61
5 4 3 2 1
5 4 3 2 1
+3V_LAN
3/30 Remove CL3 when use AR8132 LL1
60mil 1 2 +1.8_VDD/LX
1 2 S INDUC_ 4.7UH +-20% SIA4012-4R7M +3V_LAN +3V_LAN
+3VALW
RL1 0_1206_5%
DL1
1 1 1 1
1
10/100_LINK_LED 2
CL3 CL4 CL1 CL2 1 1 RL3
LAN_SK# 36
10U_0805_10V4Z 0.1U_0402_16V4Z +AVDD_CEN 1000_LINK_LED 3 4.7K_0402_1%
2 2 2 2 +AVDD_CEN CL5
D
6 1 1 @
10U_0805_10V4Z 1U_0402_6.3V4Z CL6 CL7 0.1U_0402_16V4Z
S
4 5
2
CHP202UPT_SOT323-3
1
2 0.1U_0402_16V4Z 10U_0805_10V4Z @2
QL1 1 RL4
SI3445ADV-T1-E3_TSOP6 2 2 UL1 4.7K_0402_1%
G
D D
@ Place Close to Pin 2 1 8 @
3
A0 VCC
2 7
2
A1 WP TWSI_SCL
3 A2 SCL 6
4 5 TWSI_SDA
GND SDA
1 210K_0402_5% EN_WOL# 39 LL1, CL6, CL7 close to Pin1 of U25 AT24C02BN-SH-T_SO8
2 RL6 @ @
CL8
@
0.1U_0402_16V4Z
Place Close to LAN chip
1 U25
60mil True RL7 49.9_0402_1%
MDI0+ 1 2
+1.8_VDD/LX 1 30 TWSI_SDA RL9 49.9_0402_1% 1 2 CL12 0.1U_0402_16V4Z
VDDHO/VDD18O/VDD18O TWSI_DATA TWSI_SCL MDI0-
TWSI_CLK 29 1 2
48 10/100_LINK_LED
LED_LINK10_100n ACTIVITY# RL8 49.9_0402_1%
+3V_LAN 2 VDD3V LED_ACTn 47 ACTIVITY# 36
MDI1+ 1 2
27 LAN_CLKREQ# RL10 49.9_0402_1% 1 2 CL9 0.1U_0402_16V4Z
SPI_CS/LED_DUPLEXn/LED_DUPLEXn LAN_CLKREQ# 25
2 1 +AVDD_CEN 6 MDI1- 1 2
CL10 0.1U_0402_16V4Z VDD3V/VDDHO/VDDHO
26 1000_LINK_LED
+2.5V_VDDH SPI_DI/NC/LED_Link1000n RL11 49.9_0402_1%
2 1 5 VDDLO/CTR12/CTR12
CL11 0.1U_0402_16V4Z 40 MDI2+ 1 2
REFCLKN CLK_PCIE_LAN# 25
REFCLKP 41 CLK_PCIE_LAN 25
PLT_RST_BUF# 3 CL13
6,28,37,47 PLT_RST_BUF# PERSTn
14 MDI0- RL12 49.9_0402_1% 1 2 0.1U_0402_16V4Z
TXN0/TXN0/TRXN0 MDI0- 36
13 MDI0+ MDI2- 1 2
TXP0/TXP0/TRXP0 MDI0+ 36
DVT 6/17 Rual Add R561! 7 18 MDI1-
VAUX_AVL/VBG1P18/VBG1P18 RXN1/RXN1/TRXN1 MDI1- 36
17 MDI1+ 3/30 Remove
RXP1/RXP1/TRXP1 MDI1+ 36
1 R561 2 0_0402_5% PCH_PCIE_WAKE#_R 4 21 MDI2-
C 26,37 PCH_PCIE_WAKE# WAKEn NC/NC/TRXN2 MDI2- 36 RL11~RL14/CL13/CL16 when C
CL14 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 37 20 MDI2+ RL13 49.9_0402_1%
25 PCIE_PTX_C_IRX_N3 TX_N NC/NC/TRXP2 MDI2+ 36
25 PCIE_PTX_C_IRX_P3
CL15 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P3 38 24 MDI3-
MDI3- 36
MDI3+ 1 2 use AR8132
PCIE_ITX_C_PRX_N3 TX_P NC/NC/TRXN3 MDI3+
44 23
Atheros
25 PCIE_ITX_C_PRX_N3 RX_N NC/NC/TRXP3 MDI3+ 36
PCIE_ITX_C_PRX_P3 43 1 2 0.1U_0402_16V4Z
25 PCIE_ITX_C_PRX_P3 RX_P
LAN_XTALO
AR8121/8131 +AVDDVCO2 MDI3-
RL14 49.9_0402_1%
9 42 1 2 CL16
LAN_XTALI XTLO AVDDL0 +1.2_AVDDL
10 XTLI AVDDL1 39
AVDDL2 36
DVDDL/AVDDL/AVDDL 22
34 TESTMODE AVDDL3 16
35 11 +AVDDVCO1
NC AVDDL4 +1.2_AVDDL
AVDDL5 8 Place Close to Pin15、19、25
31 46 +1.2_DVDDL
CL17 close to Pin15
SMCLK DVDDL0
33 SMDATA AVDDL/DVDDL/DVDDL 45
32 CL18
DVDDL1 0.1U_0402_16V4Z
SPI_CLK/DVDDL/DVDDL 28
+2.5V_VDDH
49 GND 1 1 1
25 +2.5V_VDDH CL17 CL19
SPI_DO/AVDDH/AVDDH 1U_0402_6.3V4Z 0.1U_0402_16V4Z
AVDDH0 19
RL15 1 2 2.37K_0402_1% 12 15
RBIAS AVDDH1 2 2 2
S IC AR8131-AL1E_QFN48P_6X6
02/25 Change PN of U26 from SA000038N00 to SA000031Z00
3/30 Remove U25 when use AR8132
B B
+1.2_AVDDL
RL19 0_0603_5%
1 2 1 2 +AVDDVCO1
@ 1
RL18
0_0603_5% CL21
0.1U_0402_16V4Z
2
CL24, CL25, CL26,CL43 close to Pin16, Pin22, Pin36,Pin39 of U25respectively
CL28 close to Pin46. CL29, CL30, CL31 close to Pin28,
Pin32, Pin45 respectively CL22,CL23 close to Pin8 of U25 CL21 close to Pin11 of U25
+1.2_AVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 +AVDDVCO2
LAN_XTALI 1 1 1 1 1 1 1
+1.2_DVDDL 0.1U_0402_16V4Z LL2 0_0603_5%
LAN_XTALO 1 1 1 1 CL22 CL23 CL24 CL25 CL26 CL43 CL27
0.1U_0402_16V4Z
CL28 CL29 CL30 CL31 2 2 2 2 2 2 2
3/16 Add by Vivian
1U_0402_6.3V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 If overclocking, RL19 , LL2 stuffed and RL18 removed.
0.1U_0402_16V4Z
If not overclocking, RL18 , LL2 suffed and RL19 removed.
A YL1 AR8131:LL2=0ohm (more power saving mode) A
1 2
1 25MHZ_20P 1
CL32 CL33
27P_0402_50V8J 27P_0402_50V8J
2 2
Security Classification
2009/02/04
Compal Secret Data
2010/02/04
Compal Electronics, Inc.
Issued Date Deciphered Date Title
Atheros AR8131
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Sheet 35 of 61
5 4 3 2 1
5 4 3 2 1
D D
+AVDD_CEN
T24
CL34 1 2 0.1U_0402_16V4Z +AVDD_CEN 1 24 MCT3 RL21 2 1 75_0402_5%
MDI3- TCT1 MCT1 MDO3-
35 MDI3- 2 TD1+ MX1+ 23
MDI3+ 3 22 MDO3+
35 MDI3+ TD1- MX1-
CL35 1 2 0.1U_0402_16V4Z 4 21 MCT2 RL22 2 1 75_0402_5%
MDI2- TCT2 MCT2 MDO2-
35 MDI2- 5 TD2+ MX2+ 20
MDI2+ 6 19 MDO2+
35 MDI2+ TD2- MX2-
CL36 1 2 0.1U_0402_16V4Z 7 18 MCT1 RL23 2 1 75_0402_5%
MDI1- TCT3 MCT3 MDO1-
35 MDI1- 8 TD3+ MX3+ 17
MDI1+ 9 16 MDO1+
35 MDI1+ TD3- MX3-
CL37 1 2 0.1U_0402_16V4Z 10 15 MCT0 RL24 2 1 75_0402_5% RJ45_PR
MDI0- TCT4 MCT4 MDO0-
35 MDI0- 11 TD4+ MX4+ 14
MDI0+ 12 13 MDO0+
35 MDI0+ TD4- MX4-
GSL5009LF
C C
Place close to TCT pin
9/18 Change T84 Value from 350uH_GSL5009LF to GSL5009LF
Change T84 P/N fromSP050003T00 to SP050003T10
Lan Conn.
2 1 <EMI>
CL38 470P_0402_50V7K
JP16
ACTIVITY# 1 2 LAN_ACT#
35 ACTIVITY#
RL25 510_0402_5% 10mil
pull down circuit :
more power saving in 1 2 MDO3- 8
RL26 5.1K_0402_5% PR4-
no-overclocking mode
MDO3+ 7 PR4+
MDO1- 6 PR2-
MDO2- 5 PR3-
B MDO2+ B
4 PR3+
MDO1+ 3 PR2+
MDO0- 2 PR1-
GND 10
MDO0+ 1 PR1+
10mil GND 9
LAN_SK# 1 2 LAN_LINK#
35 LAN_SK#
RL27 300_0402_5%
+3V_LAN
2 1 <EMI>
CL39 470P_0402_50V7K FOX_JM36113-L0R7-7F
CL40
RJ45_PR 1 2 <EMI> LANGND
1 1
1000P_1206_2KV7K
CL41 CL42
0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
2009/02/04 2010/02/04 Title
Issued Date Deciphered Date
LAN CONNECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Sheet 36 of 61
5 4 3 2 1
A B C D E
Mini-Express Card for TV Tuner +3VS +1.5VS +3VS
1 1 1 1 1 1
C628 C629 C630 C631 C632 C633
@ @
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
1 JMIN1 1
PCH_PCIE_WAKE# 1 2
26,35 PCH_PCIE_WAKE# 1 2 +3VS
WLAN_ACTIVE 3 4
41 WLAN_ACTIVE 3 4
there is a pull high at +3V_ALW BT_ACTIVE 5 6
41 BT_ACTIVE 5 6 +1.5VS
+3VS 1 2 3G_CLKREQ# 7 8 LPC_FRAME#
LPC_FRAME# 24,39,42,47
05/19 25 3G_CLKREQ#
R535 10K_0402_5% 9
7
9
8
10
10 LPC_AD3
LPC_AD3 24,39,42,47
@ 11 12 LPC_AD2
25 CLK_PCIE_3G# 11 12 LPC_AD2 24,39,42,47
13 14 LPC_AD1
25 CLK_PCIE_3G 13 14 LPC_AD1 24,39,42,47
15 16 LPC_AD0 LPC_AD0 24,39,42,47
4/2 Add by Vivian EC_TX_P80_DATA 17
15 16
18
C880 39 EC_TX_P80_DATA 17 18
100P_0402_50V8J 2 1 @ EC_TX_P80_DATA 19 20 MINI2_OFF#
19 20 PLT_RST_BUF#
21 22 PLT_RST_BUF# 6,28,35,47
PCIE_PTX_C_IRX_N4 21 22
25 PCIE_PTX_C_IRX_N4 23 24 +3VS
PCIE_PTX_C_IRX_P4 23 24
25 PCIE_PTX_C_IRX_P4 25 26
25 26
27 27 28 28
29 30 PCH_SMBCLK
PCIE_ITX_C_PRX_N4 29 30 PCH_SMBDATA
25 PCIE_ITX_C_PRX_N4 31 32
PCIE_ITX_C_PRX_P4 31 32
25 PCIE_ITX_C_PRX_P4 33 34
33 34 USB20_R_N3
Vcc 3.3V +/- 8% 35
35 36
36
USB20_R_P3
37 37 38 38
Peak Icc 2750mA 39 40
39 40
with max supply droop 50mA +3VS 41 42
41 42 (WWAN_LED#)
43 44 WLAN_LED# 47
Average Icc 1000mA 43 44
45 46
R730 0_0402_5% 45 46
47 47 48 48
EC_TX_P80_DATA1 2 EC_TX_P80_DATA_R 49 50
EC_RX_P80_CLK 49 50
39 EC_RX_P80_CLK 51 52
+3VS 51 52
53 54
PVT Add R730 for different dibug card GND1 GND2
1
R536 FOX_AS0B226-S56N-7F
2 2
CONN@
10K_0402_5%
@
2
WCM2012F2SF-121T04_0805
MINI2_OFF# USB20_R_N3 4 3 USB20_N3
4 3 USB20_N3 28
1
D
Q22 2 TV_ON# USB20_R_P3 1 2 USB20_P3
TV_ON# 39 1 2 USB20_P3 28
SSM3K7002FU_SC70-3 G
S L61 <EMI> <EMI>
3
1 2 R537 0_0402_5%
1 2 R538 0_0402_5%
<EMI>
Mini-Express Card for WLAN
MINI_VCC +1.5VS +3VS
Change PCB footprint of L59 from L_0805 to R_0805
JMIN2 L62
PCH_PCIE_WAKE# 1 2 MINI_VCC 1 2
26,35 PCH_PCIE_WAKE# 1 2
WLAN_ACTIVE 3 4 KC FBM-L11-201209-221LMAT_0805
41 WLAN_ACTIVE 3 4
BT_ACTIVE 5 6
41 BT_ACTIVE 5 6
WLAN_CLKREQ# 7 8
25 WLAN_CLKREQ# 7 8
9 10
CLK_PCIE_WLAN# 9 10 +3VS
25 CLK_PCIE_WLAN# 11 12
CLK_PCIE_WLAN 11 12
25 CLK_PCIE_WLAN 13 14
3 13 14 3
15 15 16 16
EC_TX_P80_DATA 17 18
39 EC_TX_P80_DATA 17 18
1
19 20 MINI_RF_OFF#
19 20 PLT_RST_BUF# R539
21 22
21 22 MINI_VCC
25 PCIE_PTX_C_IRX_N2 23 24
23 24 10K_0402_5%
25 PCIE_PTX_C_IRX_P2 25 26
25 26
27 28
2
27 28 PCH_SMBCLK
29 30 PCH_SMBCLK 23,25
29 30 PCH_SMBDATA MINI_RF_OFF#
25 PCIE_ITX_C_PRX_N2 31 32 PCH_SMBDATA 23,25
31 32
25 PCIE_ITX_C_PRX_P2 33 34
33 34
1
USB20_R_N8 D
35 36
35 36 USB20_R_P8 Q21 RF_ON#
37 37 38 38 2 RF_ON# 39
MINI_VCC 39 40 SSM3K7002FU_SC70-3 G
39 40
41 42 S
3
41 42 WLAN_LED#
43 44 WLAN_LED# 47
43 44
45 46
45 46
47 47 48 48
EC_TX_P80_DATA_R 49 50
@ EC_RX_P80_CLK 49 50
39 EC_RX_P80_CLK 51 52
WCM2012F2SF-121T04_0805 51 52
USB20_R_P8 4 3 USB20_P8 53 54 R540
4 3 USB20_P8 28 GND1 GND2
1 2 +5VS 4/2 Add by Vivian C881
USB20_R_N8 1 2 USB20_N8 FOX_AS0B226-S56N-7F 100K_0402_5% RF_ON# @ 1 2 100P_0402_50V8J
1 2 USB20_N8 28
CONN@
L63 <EMI> <EMI> +3VS
1 2 R541 0_0402_5%
1 2 R542 0_0402_5%
<EMI>
1
C634
4 MINI_VCC +1.5VS 0.1U_0402_16V4Z 4
2
1 1 1 1 1 1
C635 C636 C637 C638 C639 C640
@ @
0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2 2 2 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
Mini-Card/Kill SWITCH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 37 of 61
A B C D E
A B C D E
1 1
2 2
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
NEW CARD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Friday, November 13, 2009 Sheet 38 of 61
A B C D E
5 4 3 2 1
+3VALW
Board ID table, in EVT and EVT2 phase, it is NA +3VALW
+3VALW +EC_DVCC
1
09-03
1
L64 R546
1 2 +EC_AVCC R545 @
+3VALW 1 2 FBM-11-160808-601-T_0603 +EC_AVCC
FBM-11-160808-601-T_0603 47K_0402_5%
L65 2 1 MB2_ID MB1_ID 100K_0402_5%
2
C651 C652 1 1 1 1 1 1 MB_ID
2
0.1U_0402_16V4Z
C653
0.1U_0402_16V4Z
C654
0.1U_0402_16V4Z
C655
0.1U_0402_16V4Z
C656
1000P_0402_50V7K
C657
1000P_0402_50V7K
C658
MB2_ID
2
0.1U_0402_16V4Z 1000P_0402_50V7K R547
DVT 0 1
0.1U_0402_16V4Z
1
2
1 2 1 ECAGND 2 C660 R548
2 2 2 2 2 2 1
L66 FBM-11-160808-601-T_0603 C659 @ 10K_0402_5%
DVT_R 0 0 @
0.1U_0402_16V4Z 10K_0402_5% 2
1
D 2 D
1
111
125
PVT 1 O @
22
33
96
67
9
U27
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
1
R549
2
0_0402_5%
MP 1 1
GATEA20 1 21 USB2_ON#
29 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F USB2_ON# 42
KB_RST# 2 1 2 23 BEEP#
29 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 44
D23 @ SERIRQ 3 26 VGA_THERM#
24,47 SERIRQ SERIRQ# FANPWM1/GPIO12 VGA_THERM# 14
CH751H-40PT_SOD323-2 LPC_FRAME# 4 27 ACOFF
24,37,42,47 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 49,51
LPC_AD3 5
24,37,42,47 LPC_AD3 LAD3
C661 LPC_AD2 7 PWM Output 1 2 ECAGND
24,37,42,47 LPC_AD2 LAD2
2 1 2 @ 1 LPC_AD1 8 63 BATT_TEMP C662 0.01U_0402_16V7K
24,37,42,47 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 50
R553 10_0402_5% LPC_AD0
@ 22P_0402_50V8J
24,37,42,47 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
PAD T16
ADP_I/AD2/GPIO3A 65 ADP_I 51
CLK_PCI_EC 12 AD Input 66 ADP_V
28 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V 51
PLT_RST_BUF1# 13 75 MB2_ID
28,42 PLT_RST_BUF1# PCIRST#/GPIO05 AD4/GPIO42 +5VS
R554 1 2 EC_RST# 37 76 MB_ID
+3VALW ECRST# SELIO2#/AD5/GPIO43
47K_0402_5% EC_SCI# 20
29 EC_SCI# SCI#/GPIO0E
1 1 @ 2 38 TP_CLK R551 1 2 4.7K_0402_5%
26,47 PM_CLKRUN# CLKRUN#/GPIO1D
C663 R550 0_0402_5% 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 22
70 EN_FAN1 TP_DATA R552 1 2 4.7K_0402_5%
+3VS EN_DFAN1/DA1/GPIO3D EN_FAN1 10
0.1U_0402_16V4Z DA Output 71 IREF
2 KSI0 IREF/DA2/GPIO3E CHGVADJ IREF 51
55 KSI0/GPIO30 DA3/GPIO3F 72 CHGVADJ 51
1 @ 2 PM_CLKRUN# KSI1 56
R558 8.2K_0402_5% KSO[0..15] KSI2 KSI1/GPIO31
40 KSO[0..15] 57 KSI2/GPIO32
KSI3 58 83 VTTP_EN
KSI[0..7] KSI3/GPIO33 PSCLK1/GPIO4A VTTP_EN 54
KSI4 59 84 EC_VGAPWRGOOD +3VALW
40 KSI[0..7] KSI4/GPIO34 PSDAT1/GPIO4B EC_VGAPWRGOOD 13
+3VALW 2 1 KSI5 60 85 TV_ON#
KSI5/GPIO35 PSCLK2/GPIO4C TV_ON# 37
R560 10K_0402_5% KSI6 61 PS2 Interface 86 POWER_USB_LED#
C KSI6/GPIO36 PSDAT2/GPIO4D POWER_USB_LED# 40 C
EC_PME# KSI7 62 87 TP_CLK KB926 SPI STRAP PIN CIR_DET# R555 2 1 10K_0402_5%
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 41
28 PCI_PME# 1 2 KSO0 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA
TP_DATA 41 No stuff when use KB926C0
R562 0_0402_5% +3VALW KSO1 40 1 2 P_USB# R556 2 1 10K_0402_5%
KSO1/GPIO21 KILL_SW# 40
KSO2 41 R563 0_0402_5%
KSO3 KSO2/GPIO22 C856 100P_0402_50V8J RCIRRX R557 1
42 KSO3/GPIO23 SDICS#/GPXOA00 97 2 10K_0402_5%
1 2 KSO1 KSO4 43 98 EN_WOL#
KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL# 35
R565 47K_0402_5% KSO5 TP_DISABLE#_LED TP_DISABLE# R559 1 2 10K_0402_5%
+5VALW KSO2 KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
1 2 45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# 42
R566 47K_0402_5% KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119 FRD#SPI_SO
KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO 41
1 2 EC_SMB_CK1 KSO10 49 120 FWR#SPI_SI
R567 4.7K_0402_5% KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK ESB_CLK_R
50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126
1 2 EC_SMB_DA1 KSO12 51 128 FSEL#SPICS#
R568 4.7K_0402_5% KSO13 KSO12/GPIO2C SPICS# ESB_DAT_R
52 KSO13/GPIO2D
KSO14 53 1
+3VS KSO15 KSO14/GPIO2E RCIRRX C664 C665
54 KSO15/GPIO2F CIR_RX/GPIO40 73 RCIRRX 42
PWRME_CTRL 81 74 @ @
24 PWRME_CTRL KSO16/GPIO48 CIR_RLC_TX/GPIO41 PCH_TEMP_ALERT 29
1 2 EC_SMB_CK2 TP_DISABLE# 82 89 FSTCHG 22P_0402_50V8J 33P_0402_50V8J
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 51
R569 2.2K_0402_5% 90 CHARGE_LED0# <EMI> 2 <EMI>
EC_SMB_DA2 BATT_CHGI_LED#/GPIO52 CAPS_LED# CHARGE_LED0# 47
1 2 CAPS_LED#/GPIO53 91 CAPS_LED# 40
R570 2.2K_0402_5% 1 1 EC_SMB_CK1 77 GPIO 92 CHARGE_LED1#
41,50 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 CHARGE_LED1# 47
C666 C667 41,50 EC_SMB_DA1 EC_SMB_DA1 78 93 PWR_LED#
SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED# 40,47
@ @ EC_SMB_CK2 79 SM Bus 95 SYSON
14,25 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 48,53
100P_0402_50V8J 100P_0402_50V8J EC_SMB_DA2 80 121 VR_ON_EC
2 2 14,25 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON_EC 26
127 ACIN
AC_IN/GPIO59 ACIN 50
2/26 Add by Vivian(for LED random turn off issue)
PM_SLP_S3# 6 100 EC_RSMRST#
26 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 26
PM_SLP_S5# 14 101 EC_LID_OUT#
26 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 25
EC_SMI# 15 102 EC_ON
29 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 42
B 33_0402_5% CR_ON# 16 103 EC_SWI# B
34 CR_ON# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# 26
ESB_CLK_R L67 1 <EMI> 2 ESB_CLK ESB_CLK 17 104 ICH_PWROK
40 ESB_CLK_R SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_PWROK 26
ESB_DAT_R L68 1 <EMI> 2 ESB_DAT ESB_DAT 18 GPO 105 BKOFF# C668
40 ESB_DAT_R PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 22
33_0402_5% 40 P_USB# P_USB# 19 GPIO 106 RF_ON# SUSP# @ 1 2 100P_0402_50V8J
EC_PME#/GPIO0D WL_OFF#/GPXO09 RF_ON# 37
INVT_PWM 25 107 BT_ON#
22 INVT_PWM EC_THERM#/GPIO11 GPXO10 BT_ON# 41
2/26 Copy KFT(avoid for LED random turn off issue) FAN_SPEED1 28 108 VGA_AC_DET
10 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 VGA_AC_DET 14
EC_ACIN 29 C857
26 EC_ACIN FANFB2/GPIO15
37 EC_TX_P80_DATA EC_TX_P80_DATA 30 BATT_TEMP @ 1 2 100P_0402_50V8J
EC_RX_P80_CLK EC_TX/GPIO16 PM_SLP_S4#
37 EC_RX_P80_CLK 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# 26
ON/OFF# 32 112 ENBKL C858
42 ON/OFF# ESB_RST# ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL 22
CIR_DET# FSTCHG
06/09 DVT ice add 40 ESB_RST#
NUM_LED#
34 PWR_LED#/GPIO19 GPXID3 114
SUS_PWR_ACK
CIR_DET# 42
@ 1 2 100P_0402_50V8J
40 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 SUS_PWR_ACK 26
116 SUSP# C859
GPXID5 SUSP# 43,48,51,53,54,55
117 PBTN_OUT# VTTP_EN @ 1 2 100P_0402_50V8J
GPXID6 PBTN_OUT# 6,26
118 EC_PME#
XCLKI GPXID7 C860
122 XCLK1 SW1
XCLKO 123 124 ENBKL @ 1 2 100P_0402_50V8J
XCLK0 V18R TP_DISABLE#
2 2 3 4
AGND
@ C861
GND
GND
GND
GND
GND
SPI_CS# 1 2 FSEL#SPICS# C669 C670 1 2 ACIN 1 2 100P_0402_50V8J
41 SPI_CS#
R571 0_0402_5% R573
SPI_CLK_R 1 2 SPI_CLK XCLKO 1 @ 2 XCLKI KB926QFD3 LQFP 128P 4.7U_0805_10V4Z 1 1 0.1U_0402_16V4Z
41 SPI_CLK_R
11
24
35
94
113
69
R572 0_0402_5% 20M_0603_5% NTC011-AA1J-A200T_4P
add this for EC suggestion
SPI_SI 1 2 FWR#SPI_SI change to SN100003F00
41 SPI_SI DVT,0625
ECAGND
R574 0_0402_5% PVT 1022
1 R575
C671 820_0402_5%
EC DEBUG PORT
4
C672 1 2 2 1 LED1 TP_DISABLE#_LED 4/2 Add by Vivian
+5VS
18P_0402_50V8J 22P_0402_50V8J 1/15 Use KB926D3
OSC
OSC
JP17 PM@ 2 HT-191NB-DT_BLUE_0603
A +3VALW 1 X2 A
EC_TX_P80_DATA 1
2 2
EC_RX_P80_CLK
NC
NC
3 3 3/26 Change color of LED1 from Blue to Amber
4 change C871 to 18p 4/1 Change color of LED1 from Amber to Blue
4
3
ACES_85205-0400
DB CONN@
32.768KHZ_12.5PF_Q13MC14610002 Security Classification Compal Secret Data Compal Electronics, Inc.
06/25 DVT ice add Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ENE-KB926
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 39 of 61
5 4 3 2 1
5 4 3 2 1
KSI[0..7]
INT_KBD Conn. KSO[0..15]
KSI[0..7] 39
KSO[0..15] 39
JP4
KSI1 1
KSI7 1
2 2
KSI6 3
KSO9 3
4 4
KSI4 5 KSI4 C673 1 2 100P_0402_50V8J KSO6 C674 1 2 100P_0402_50V8J
KSI5 5 KSI5 C675 100P_0402_50V8J KSO3 C676 100P_0402_50V8J
6 6 1 2 1 2
D KSO0 7 KSO0 C677 1 2 100P_0402_50V8J KSO12 C678 1 2 100P_0402_50V8J D
KSI2 7 KSI2 C679 100P_0402_50V8J KSO13 C680 100P_0402_50V8J
8 8 1 2 1 2
KSI3 9
KSO5 9
10 10
KSO1 11
KSI0 11
12 12
KSO2 13 KSI1 C681 1 2 100P_0402_50V8J KSI3 C682 1 2 100P_0402_50V8J
KSO4 13 KSI7 C683 100P_0402_50V8J KSO5 C684 100P_0402_50V8J
14 14 1 2 1 2
KSO7 15 KSI6 C685 1 2 100P_0402_50V8J KSO1 C686 1 2 100P_0402_50V8J
KSO8 15 KSO9 C687 100P_0402_50V8J KSI0 C688 100P_0402_50V8J
16 16 1 2 1 2
KSO6 17
KSO3 17
18 18
KSO12 19
KSO13 19
20 20
KSO14 21 KSO2 C689 1 2 100P_0402_50V8J KSO14 C690 1 2 100P_0402_50V8J
KSO11 21 KSO4 C691 100P_0402_50V8J KSO11 C692 100P_0402_50V8J
22 22 1 2 1 2
KSO10 23 KSO7 C693 1 2 100P_0402_50V8J KSO10 C694 1 2 100P_0402_50V8J
KSO15 23 KSO8 C695 100P_0402_50V8J KSO15 C696 100P_0402_50V8J
24 24 1 2 1 2
25 25
GND 27
GND 26
ACES_88502-2501
CONN@
C C
Power USB Board Conn Conductive board conn Kill SWITCH
+FUN_VCC
@ W=40mils
+3VALW R576 0_0603_5%
+3VALW R578 2 1 0_0603_5% +FUN_VCC JP6
+5VALW R577 0_0603_5% W=40milsJP5 +3VS R579 2 1 0_0603_5% 1
@ ESB_CLK_R_L 1
2 2
+PWR_VCC 1 ESB_DAT_R_L 3
ON/OFFBTN# 1 3
42 ON/OFFBTN# 2 2 +5VALW 4 4
D_P_USB# 3 5
3 39 ESB_RST# 5
PWR_LED# 4 6
39,47 PWR_LED# 4 6
POWER_USB_LED# 5 7
39 POWER_USB_LED# 5 7
6 6 8 8
7 9 +3VALW
GND GND
8 GND 10 GND
ACES_85201-06051 ACES_85201-08051
CONN@
2
3/20 Add D52 for SC300000O00 D24 +3VALW
DAN217_SC59
D52
2
B @ B
+3VALW 6 3 ESB_CLK_R_L R580
CH3 CH2
1
100K_0402_5%
1
1
R581 +3VALW 5 2 KILL_SW#
Vp Vn KILL_SW# 39
10K_0402_5%
2
D25 ESB_DAT_R_L 4 1
P_USB# CH4 CH1
2 P_USB# 39
3
D_P_USB# 1
51_ON# CM1293A-04SO SOT23-6
3
3
51_ON# 42,49
<EMI> EMI Request
DAN202UT106_SC70-3
SW2
1BS003-1211L_3P
FBMA-11-100505-301T_0402
L69 1 <EMI> 2 ESB_CLK_R_L
39 ESB_CLK_R
L70 1 <EMI> 2 ESB_DAT_R_L
LED Board Conn 39 ESB_DAT_R
FBMA-11-100505-301T_0402
C697
@ <EMI>
+3VS R582 0_0603_5% 33P_0402_50V8J
+5VS R583 0_0603_5% W=40mils
A A
JP10 EMI recommend
+LED_VCC 1 5
CAPS_LED# 15
39 CAPS_LED# 2 26 6
NUM_LED# 3
39 NUM_LED# 3
4 4
ACES_85201-0405 Security Classification Compal Secret Data Compal Electronics, Inc.
CONN@ 2009/02/04 2010/02/04 Title
4/2 Add by Vivian Issued Date Deciphered Date
100P_0402_50V8J 2
C882
1 @ NUM_LED#
KB/SW/PW/Fun Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 40 of 61
5 4 3 2 1
+3VALW +5VALW
16M SPI ROM
2 @ 1 EEPROM_VCC
For EC+BIOS+VBIOS
R584 0_0603_5%
2 @ 1
R585 0_0603_5%
+3VALW
1 20mils
EEPROM_VCC EEPROM_VCC EEPROM_VCC C698 U28
8 4
@ 0.1U_0402_16V4Z VCC VSS
1
C699 1 2 0.1U_0402_16V4Z 2 3
W
1 @ 2 EC_SMB_CK1 R587
R586 4.7K_0402_5% @ 7 HOLD
1 @ 2 EC_SMB_DA1 100K_0402_5%
R588 4.7K_0402_5% U29 @ SPI_CS# 1
2
39 SPI_CS# S
8 1
VCC A0 SPI_CLK_R
7 2 39 SPI_CLK_R 6
WP A1 C
12/28 Add 39,50 EC_SMB_CK1 6 SCL A2 3
SPI_SI SPI_SO 2
39,50 EC_SMB_DA1 5 4 39 SPI_SI 5 2 1 FRD#SPI_SO 39
SDA GND D Q R589 0_0402_5%
AT24C16AN-10SU-2-7_SO8 MX25L1605AM2C-12G SO8
10/20 Change value of U32 to MX25L1605AM2C-12G SO8
1
R590 12/15 change from 15 to 0 ohm'
@
100K_0402_5%
2
0206 => change PN to SA00001N800
12/19 change pn to SA00001MP00 ( original part EOL ) SPI_CLK_R 1 2 1 2 C777
12/25 change back to SA024160140 ( Samples can not on time ) R729 0_0402_5% 22P_0402_50V8J
@ @
DVTFor EMI add 6/23
Bluetooth Conn. To TP/B Conn.
Need to check BT pin definition again!
9/20 modified this block
JP7
1
+5VS TP_CLK 1
39 TP_CLK 2 2
TP_DATA 3
+5VS 39 TP_DATA 3
SWL# 4
SWR# 4
5
5
6
@ 6
7
GND
1
WCM2012F2SF-121T04_0805 8
R591 GND
4 3
4 3 ACES_85201-06051
10K_0402_5% +BT_VCC
1 2
2
1 2 JP8
BT_LED# L71 <EMI> 1
47 BT_LED# 1 +5VS
BT_ACTIVE 2
37 BT_ACTIVE 2
28 USB20_P10 USB20_P10 1 <EMI> 2 USB20_R_P6 3 SWR# TP_DATA
3
1
D R592 1
28 USB20_N10
USB20_N10 2 0_0402_5% USB20_R_N6 4
Q23 BTON_LED R593 <EMI> 0_0402_5% 4 SWL# TP_CLK C700
2 5
G WLAN_ACTIVE 5
SSM3K7002FU_SC70-3 37 WLAN_ACTIVE 6
6
3
S 7 0.1U_0402_16V4Z
3
7
1
8 8
9 D26 D27
R594 GND1 @ @
10
10K_0402_5% GND2 PSOT24C_SOT23 PSOT24C_SOT23
MOLEX_53780-0870
2
1
CONN@
4/2 Add by Vivian
C701 Update Footprint
C874
2 1 +BT_VCC TP_CLK @ 1 2 100P_0402_50V8J
<EMI> @ 0.1U_0402_16V4Z
SW3 C875
6
5
TP_DATA @ 1 2 100P_0402_50V8J
SWL# 2 4
C876
Left Switch 1 3 SWL# @ 1 2 100P_0402_50V8J
SMT1-05_4P C877
SWR# @ 1 2 100P_0402_50V8J
+3VALW
1
C702 C703 SW4
6
5
0.1U_0402_16V4Z 1U_0603_10V4Z SWR# change PN to SN100002Y00
S 2 4
3
2 PVT 0810
G
39 BT_ON# 1 2 2 Right Switch 1 3
R595 100K_0402_5% Q18
SI2301BDS_SOT23 SMT1-05_4P
D
W=40mils
1
+BT_VCC
1
C704 C705
@
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
BIOS, TP & BT Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 41 of 61
A B C D E
+USB_VCCA
ON/OFF switch USB IO 2 Conn.
TOP Side
2 1
FOR LPC DEBUG PORT DVT 6/24 Rual Add C480 for EMI! DVT
2
J3 @ JOPEN C480
2 1 0.01U_0402_25V7K
J4 @ JOPEN +3VALW @ 1 JP18
Bottom Side 1 1
28 USB20_N9 2
2
28 USB20_P9 3 5
3 G1
2
4 6
R596 4 G2
ACES_88266-04001
100K_0402_5% +3VS CONN@
1 +USB_VCCA 1
W=40mils
1
D28
2 ON/OFF# +USB_VCCA
ON/OFF# 39
ON/OFFBTN# 1
40 ON/OFFBTN#
3 51_ON# 51_ON# 40,49 1 1
JP9 C706 C707
DAN202UT106_SC70-3 1
1 CLK_PCI_DB 470P_0402_50V7K 10U_0805_10V4Z
2
Power Button 2
3 3
4 LPC_AD0
CLK_PCI_DB 28 2 2
4 LPC_AD0 24,37,39,47
SMT1-05_4P 5 LPC_AD1 10/27 Remove C1640 by Vivian
5 LPC_AD1 24,37,39,47
1
SW5 2 6 LPC_AD2
6 LPC_AD3 LPC_AD2 24,37,39,47
C708 D29 7 DVT 6/25 Add C778 for EMI! DVT ice
7 LPC_AD3 24,37,39,47
1 3 ON/OFFBTN# 8 LPC_FRAME#
LPC_FRAME# 24,37,39,47
1000P_0402_50V7K RLZ20A_LL34 8 +5VALW +USB_VCCA +3VALW
9 9
1 PLT_RST_BUF1#
2 4 10
2
10 PLT_RST_BUF1# 28,39
0.01U_0402_25V7K
11 C778 1
GND
12 1
6
5
GND
2
C709
10/09 add for debug ACES_85201-1005N @ U30 R597
DB CONN@ 0.1U_0402_16V4Z 2 10K_0402_5%
1 8
2 @ GND OUT
2 7
SMT1-05_4P IN OUT R598
3 6
1
IN OUT
1
D
SW6 1 4 5 2 1 USB_OC#4 28
EC_ON EN# FLG
39 EC_ON 2
1 3 ON/OFFBTN# G C710 G528P1UF_SOP8 0_0402_5%
2
S 4.7U_0805_10V4Z 1
3
2 4 Q24 2 C711
R599 SSM3K7002FU_SC70-3 @
10K_0402_5% 0.1U_0402_16V4Z
6
5
2
1
39 USB2_ON#
2
3/3 Add 2
11/03 Modify symbol to SCR00000H00 by Vivian USB2_ON# C712 2 1 100P_0402_50V8J
CIR +USB_VCCC
3/30 Change part number of IR1 from SCR00000H00 to SCR00000E00 USB IO Conn. JP11
1
2
USB20_N0 3
28 USB20_N0 4
IR1 W=20mils R600 28 USB20_P0 USB20_P0
RCIRRX +CIR_VCC 5
39 RCIRRX 1 2 +3VALW
C713 Vout Vcc 100_0402_5% CIR@ 6
3 4
GND1GND2 7
2 1
FM-2136SC-5CN(REV)_4P C714 USB20_N5 8
28 USB20_N5 9
1000P_0402_50V7K CIR@ 4.7U_0603_6.3V6K USB20_P5
28 USB20_P5 10
@ CIR@
11
12
13
150u 14
USB20_N4
ESR 0.9 ohm 28 USB20_N4
USB20_P4 15
28 USB20_P4 16
Package(L*W*H)7.3*4.3*2.9
17
Rating 6.3V 18
R601 0_0402_5% 19
3 20 3
39 CIR_DET# 2 1
ACES_85201-20051
CIR@
+USB_VCCC
W=80mils
1
1 C715
C716
10U_0805_10V4Z
Lid Switch 2
470P_0402_50V7K 2
11/29 change this symbol's footprint as
ADT7421ARMZ-REEL_MSOP8
+5VALW +USB_VCCC +3VALW
copy LM75CIMMX-3_MSOP8
footprint
2
1 2 +VCC_LID R603 1 2 100K_0402_5% R604
+3VALW
R602 0_0402_5% U31
1 8 10K_0402_5%
GND OUT
2
2 7 R605 0_0402_5%
1
IN OUT
3 6 2 1
VDD
IN NC USB_OC#0 28
1 4 EN# OC 5 USB_OC#2 28
1 C718
C717 3 G545A2P8U MSOP 8P
OUTPUT LID_SW# 39
4.7U_0805_10V4Z 1
0.1U_0402_16V4Z 2 C720
2
GND
4 2 C719 4
0.1U_0402_16V4Z USB2_ON# C721 2 1 100P_0402_50V8J
U32 10P_0402_50V8J 2 @
1
1 39 USB2_ON#
A3212ELHLT-T_SOT23W-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
Power OK/Lid/Front,IO,DB Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 42 of 61
A B C D E
5 4 3 2 1
+3VS
1
R720
10K_0402_5%
DVT, add power good signal, 0619
2
D40
D 1 2 PWR_GD_R 1 2 R351 D
53,55,56 PCIE_OK PWR_GD 26
0_0402_5%
RB751V_SOD323
+3VALW
1
R681
6
10K_0402_5% 3/3 Add
@
2
DGPU_PWR_EN 1 2 R741 VGA_ON Q49A
0_0402_5% 2 2N7002DW-T/R7_SOT363-6
R675 SW7
1
1
6
5
1K_0402_5% C @
+1.1VS_VTT 2 1 2 Q42 2 4 +RTCVCC
+3VS_DELAY B MMBT3904_SOT23
+3VALW +3VALW E 1 3
3
1
DISO@ SMT1-05_4P
SN74LVC14APWR_TSSOP14
R841 +3VALW
14
14
10K_0402_5% U55A U55B
P
P
2
1 2 3 4 +5VS
56 DGPU_PWROK I O I O DGPU_PWROK_BUF 29
1
1U_0402_6.3V6K
G
C 1 DIS@ DIS@ C
@ SN74LVC14APWR_TSSOP14 R721
7
3
10K_0402_5%
1
C758
2
2 Q49B SMT1-05_4P
R680
5 2N7002DW-T/R7_SOT363-6 SW8
180K_0402_5% @
1 3 +RTCVCC
4
D
1
2 Q44 2 4
G
14
14
SSM3K7002FU_SC70-3
U55C U55D S
6
5
P
1
5 I O 6 9 I O 8
@ R722 <BOM Structure>
G
560K_0402_5%
DIS@ SN74LVC14APWR_TSSOP14 SN74LVC14APWR_TSSOP14
7
DIS@
2
+3VALW
+3VS_DELAY
VGA_ON 14,48,56,58
1
1
need change to 31.6K, follow NCQD0 R719
2
6
10K_0402_5%
R854 R738
2
B 10K_0402_5% DIS@ Q50A B
14
14
0_0402_5%
U55E DIS@ U55F @ 2 2N7002DW-T/R7_SOT363-6
2
R855 SG@
P
1 2 11 10 13 12 R723
25,29,48 DGPU_PWR_EN
1
I O I O
1
DISO@ 1K_0402_5% C
G
10K_0402_5% +1.5VS 2 1 2 Q47
SN74LVC14APWR_TSSOP14 SN74LVC14APWR_TSSOP14 B MMBT3904_SOT23 +3VALW
7
D
1
SG@ E
3
2 Q46 to enable 1.1V, 3VS_DELAY,1.5V,1.8V.VGA_CORE,VDDCI
48 DGPU_PWR_EN#
1
G C760
SSM3K7002FU_SC70-3 S 2 1@
3
R728
1U_0402_6.3V6K 10K_0402_5%
2
DISO@
D
1
2 Q45
48,55 SUSP
G SSM3K7002FU_SC70-3 R724
1
S 1K_0402_5% C
3
3
+1.05VS 2 1 2 Q51
B MMBT3904_SOT23
E
3 Q50B
5 2N7002DW-T/R7_SOT363-6
4
DGPU_PWR_EN 1 2 R480 VGA_ON
0_0402_5%
A A
SUSP# 1 2 R736 VGA_ON
39,48,51,53,54,55 SUSP#
0_0402_5%
DISO@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 43 of 61
5 4 3 2 1
A B C D E F G H
1 2
R606 0_0805_5%
Copy KFTOO
+5VAMP
U33
+5VS L72 1 2 0.1U_0402_16V4Z 60mil 1 40mil
IN
C722 1 2 0.1U_0402_16V4Z FBMA-L11-201209-221LMA30T_0805
OUT
5 +VDDA 4.75V
2
EC Beep L73 1 2
1
C723
1
C724 GND
FBMA-L11-201209-221LMA30T_0805 3 4 1 2
1 0.1U_0402_16V4Z SHDN BYP C725 1
R607 1 2 10K_0402_5% MONO_IN_1 1 2 MONO_IN 2 2 G9191-475T1U_SOT23-5 0.01U_0402_25V7K
39 BEEP#
C726 0.1U_0402_16V4Z @ @
R608 1 2 10K_0402_5% 2/18 Change from GNDA to DGND of
(output = 300 mA)
24 PCH_SPKR
vendor suggest
1
R609
PCI Beep
10K_0402_5%
2
HD Audio Codec
+AVDD_HDA
2/20 Change value and symbol of L74 1 2 0.1U_0402_16V4Z
40mil 10mil 0.1U_0402_16V4Z +3VS_DVDD L75 1 2
+VDDA +3VS
R1107 and R1111 from 2.2K ohmto 4.7K FBMA-L11-160808-800LMT_0603 1 1 1 MBK1608121YZF_0603
C728 C729 1 1 1
ohm(of Vendor suggest) C727 C730 C731 C732
10U_0805_10V4Z 10U_0805_10V4Z
2 2 2
2 R610 0.1U_0402_16V4Z 2 2 2
25
38
1
9
2 0_0402_5% U34 2
@ 0.1U_0402_16V4Z
DVDD_IO
AVDD1
AVDD2
DVDD
D30
MIC2_VREFO 2 1 1 R613 2 DUAL@
4.7K_0402_5%
RLS4148_LL34-2 14 35 AMP_LEFT
LINE2_L LOUT1_L AMP_LEFT 45
DUAL@ 2/11 Modify Schematic
15 36 AMP_RIGHT
LINE2_R LOUT_R AMP_RIGHT 45
C733
MIC2_L R611 2 1 1K_0402_1% MIC2_R_L 1 2 MIC2_C_L 16 39
45 MIC2_L MIC2_L LOUT2_L
4.7U_0805_6.3V6K
MIC2_R R612 2 1 1K_0402_1% MIC2_R_R C734 1 2 MIC2_C_R 17 41
45 MIC2_R MIC2_R LOUT2_R
4.7U_0805_6.3V6K
23 LINE1_L SPDIFO2 45
R614 0_0402_5%
2 1 2/11 Remove LINE-IN Schematic 24
LINE1_R DMIC_CLK1/2
46 2/11 Remove Digital MIC Schematic
SINGLE@
18 43
D31 LINE1_VREFO NC
MIC2_VREFO 2 1 1 R615 2 20 44 1 2 1 2 C735
4.7K_0402_5% LINE2_VREFO DMIC_CLK3/4 R616 33_0402_5% 33P_0402_50V8J DVT For EMI add 6/23
RLS4148_LL34-2 19
MIC2_VREFO MIC2_VREFO
DUAL@ 6
BITCLK HDA_BITCLK_AUDIO 24
MIC1_L 1 2 MIC1_C_L 21
45 MIC1_L MIC1_L
C736 4.7U_0805_6.3V6K
MIC1_R 1 2 MIC1_C_R 22 8 HDA_SDIN0_AUDIO 1 2
45 MIC1_R MIC1_R SDATA_IN HDA_SDIN0 24
C737 4.7U_0805_6.3V6K R617 33_0402_5%
1 2 MONO_IN 12 37
C738 @ 100P_0402_50V8J PCBEEP_IN MONO_OUT
2/11 Remove SUB WOOFER Schematic
29
CBP 2.2U_0402_6.3VM
24 HDA_RST_AUDIO# 11
RESET# C739 1
31 2
3 CPVEE 3
24 HDA_SYNC_AUDIO 10 SYNC 10mil 1
28 MIC1_VREFO
MIC1_VREFO C740
24 HDA_SDOUT_AUDIO 5
SDATA_OUT HP_R
32 HP_R 45 2.2U_0402_6.3VM
HPOUT_R 2
2/11 Remove Digital MIC Schematic 2
GPIO0/DMIC_DATA1/2
3 30
R618 2 SENSE_A GPIO1/DMIC_DATA3/4 CBN
45 MIC_PLUG# 1 20K_0402_1% 13 10mil
R619 5.1K_0402_1% SENSE_B SENSE A CODEC_VREF C741 1
45 HP_PLUG# 34 27 2 0.1U_0402_16V4Z
SENSE B VREF C742 1 2 10U_0805_10V4Z
1 2 47 40 R621 1 2 20K_0402_1%
45 MUTE# EAPD JDREF
R620 0_0402_5%
48 33 HP_L
SPDIFO1 HPOUT_L HP_L 45
3/3 Follow HW2 schematic(NSKAA) 2/11 Remove SPDIF Schematic
4 26
DVSS1 AVSS1
7 42
DVSS2 AVSS2
ALC272-VA2-GR LQFP_48P
1 2 1 2
R622 0_0805_5% R623 0_0805_5%
ESD 3/20 Copy KHLBX DGND GNDA
+3VS +5VS 1 2 1 2
2/26 Change PN of U61 from SA00002CI20 to SA00002CI10 R624 0_0805_5% R625 0_0805_5%
1
R763 R764 1 2 1 2
4.7K_0402_5% 4.7K_0402_5% R626 0_0805_5% R627 0_0805_5%
@ @
2
HDA_RST_AUDIO#
4
1 GND GNDA GND GNDA 4
C854
0.01U_0402_16V7K
@ 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
HD Audio Codec ALC272
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 44 of 61
A B C D E F G H
A B C D E
GAIN0 GAIN1 AV(inv) Ri +5VAMP
0 0 6dB 90k
0 1 10dB 70k 0.1U_0402_16V4Z
1 1
+5VAMP
1 0 15.6dB 45k C743 C744 10 dB
1 1 21.6dB 25k 10U_0805_10V4Z
2 2
1
16
15
6
U35
R628 R629
PVDD1
PVDD2
VDD
@
1 1
2
100K_0402_5% 100K_0402_5%
C745 1 2 0.47U_0603_10V7K 7 2 GAIN0
RIN+ GAIN0
3 GAIN1
GAIN1
HP JACK
1
1 2 1 2 AMP_C_RIGHT 17
44 AMP_RIGHT RIN- SPKR+
C746 0.47U_0603_10V7K R630 0_0603_5% 18 @ R631 R632
ROUT+ 100K_0402_5% 100K_0402_5%
JP12
14 SPKR- HP_PLUG# 5
2
ROUT- 44 HP_PLUG#
C747 1 2 0.47U_0603_10V7K 9
LIN+ R633 FBMA-L11-160808-700LMT_2P 4 10
4 SPKL+ 56.2_0603_1% L76 9
LOUT+ HP_R_1 1 HP_R_R
44 HP_R 1 2 2 3 8
1 2 1 2 AMP_C_LEFT 5 L77 6 7
44 AMP_LEFT LIN- SPKL- HP_L_1 1 HP_L_R
C748 0.47U_0603_10V7K R634 0_0603_5% 8 1 2 2 2
LOUT- 44 HP_L
FBMA-L11-160808-700LMT_2P 1
R635
3
56.2_0603_1% 1 1 SINGA_2SJ-B351-S02
CONN@
3/3 Follow HW2 schematic(NSKAA) 12 C749 C750
NC 330P_0402_50V7K 330P_0402_50V7K BLUE
2 2
MUTE# BYPASS
10 Keep 10 mil width (Use KHLBX PCB Footprint)
19 @
1
44 MUTE# SHUTDOWN
2 D51
3/20 Add PSOT05C-LF-T7 SOT-23-3
GND5
GND1
GND2
GND3
GND4
C751 <EMI>
0.47U_0603_10V7K
1
21
20
13
11
1
2 TPATPA6017A2PWP_TSSOP20 2
3/20 Change footprint of U35 to TPA6017A2PWP_TSSOP20
MIC1_VREFO MIC1_VREFO
2
D32 D33
CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2
1
MIC JACK
1
JP13
R636 R637 5
44 MIC_PLUG#
4.7K_0402_5%
4.7K_0402_5% 4 10
2
9
R638 1 2 MIC1_R_1 L78 1 2 MIC1_R_R 3 8
44 MIC1_R
1K_0603_1% FBMA-L11-160808-700LMT_2P 6 7
R639 1 2 MIC1_L_1 L79 1 2 MIC1_L_R 2
44 MIC1_L
1K_0603_1% FBMA-L11-160808-700LMT_2P 1
1 1
SINGA_2SJ-B351-S01
3
C752 C753 CONN@
220P_0402_50V7K 220P_0402_50V7K
JMIC1 2 2 RED
MIC2_L_OUT 2 <EMI> MIC2_L
1
1
2 2 1
1
R640 0_0402_5%
MIC2_L 44 (Use KHLBX PCB Footprint)
2 C754 220P_0402_50V7K @
1
3 <EMI> DUAL@ D34 3/20 Copy KHLBX
3 GND PSOT05C-LF-T7 SOT-23-3 3
GND 4
<EMI>
1
ACES_88231-02001 MIC_GND D35
CONN@ R641 3 3/20 Change D35 to SCA00000G00(EMI suggest)
0_0402_5% 1
SINGLE@ 2
2
<EMI>
PACDN042Y3R_SOT23-3
JMIC2
1
1
2 2 1
MIC2_R_OUT 1
R642
2 <EMI>
0_0402_5%
MIC2_R
MIC2_R 44 Int. Speaker Conn.
2 C755 220P_0402_50V7K
3 <EMI>
GND JSPK1
GND 4
SPKL- R643 1 2 <EMI> 0_0603_5% SPK_L1- 1
ACES_88231-02001 SPKL+ R644 <EMI> 0_0603_5% SPK_L1+ 1
MIC_GND SPKR-
1 2
SPK_R1-
2
2
CONN@ R645 1 2 <EMI> 0_0603_5% 3 5
SPKR+ R646 <EMI> 0_0603_5% SPK_R1+ 3 G1
1 2 4 6
4 G2
20mil ACES_88266-04001
Speaker Conn. CONN@
3
D36 D37
PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3
<EMI> <EMI>
1
4 4
Copy KHLBX schematic
Copy KFT00(2/20 add)
3/20 Change D36/D37 to SCA00000G00(EMI suggest)
@
R647 0_0603_5%
R648 0_0603_5%
MIC_GND
Security Classification Compal Secret Data Compal Electronics, Inc.
GNDA Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
MIC & Amplifier & Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 45 of 61
A B C D E
A B C D E
11/27 Add screw for layout request
1 1
H1 H2 H3 H4 H9 H10 H11 H12 H13 H14 H15 H16
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
H_3P0
1
1
@ @ @ @ @ @ @ @ @ @ @ @
9/7 Change H9 from GND to AGND
H19 H20
HOLEA HOLEA
H_3P2
1
Del modem holea (H17 and H18) H34,H35
2009/09/02
H21 H22 H23
HOLEA HOLEA HOLEA
H_4P0
1
@ @ @
2 H24 H26 H27 H33 2
HOLEA HOLEA HOLEA HOLEA
H_4P2
1
FD1 FD2 FD3 FD4 FD5 FD6
@ @ @ @
@ @ @ @ @ @
1
H28
HOLEA
H_5P0
change to 5.5, PVT 1104
1
H29 H30 H36 H37
H_2P3 HOLEA HOLEA HOLEA HOLEA
1
@ @ @ @
change from 2.3 to 2.4, PVT 1104 9/7 Change H36 from GND to AGND
3 3
M1 M2 M3
HOLEA HOLEA HOLEA
1
H_2P8N H_3P0N H_3P0N
@ @ @
M4 M5
HOLEA HOLEA
1
H_4P8X2P8N H_3P8X2P8N
@ @
4 4
11/27 Add screw for layout request
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
Screw
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB1 M/B LA-5411P Schematic
Date: Friday, November 13, 2009 Sheet 46 of 61
A B C D E
Camera Conn
3/20 Change D39 from SC300000100 to SC300000O00
6
D39
3 USB20_R_P1
Finger Print board
CH3 CH2
+3VS 5 2
Vp Vn
+5VS
L81 @ WCM2012F2SF-121T04_0805
USB20_R_N1 4 1 4 3
CH4 CH1 4 3
CM1293A-04SO SOT23-6 EMI Request
1 2
<EMI> 1 2 JP15
0_0402_5% 1
USB20_P1 R656 2 USB20_R_P1 1
28 USB20_P1 1 2
USB20_N1 USB20_R_N1 2
28 USB20_N1 1 2 3
R657 0_0402_5% 3
4
4
5 5
+3VS 6
6
7
TPM X76 Information 8
GND
GND
1 1 ACES_85201-06051
X76 P/N Vendor Location Bom Structure C762 C763 FPCONN@
4.7U_0805_10V4Z 0.1U_0402_16V4Z
C761
X7611630L07 Infineon C717,C718,R698,R702,R703,U32,X3 IN_TPM@ @ 2 2
2 1 +5VS
<EMI> @ 0.1U_0402_16V4Z
X7611630L08 Winbond C724,U32 WB_TPM@
Let C1206 close pin 24 Let C1207close pin 10
TPM 1.2 +3VS Copy IFT
Base I/O Address
LED +3VALW
C764
1 1
C765 0 = 02Eh
+3VS
0.1U_0402_16V4Z
WB_TPM@
1U_0402_6.3V4Z
* 1 = 04Eh
R658 TPM@ 2 2
820_0402_5%
1 2 2 1 LED2
DVT, for debug, 0617
+5VS SATA_LED# 24
R727
HT-191NB_BLUE_0603 @ 10K_0402_5%
24
19
10
5
U36 1 2 +3VS
R660
VSB
VDD
VDD
VDD
820_0402_5%
+5VALW 1 2 2 1 LED3 PWR_LED# 39,40 R659
LPC_AD0 26 28 SUS_STAT#_R R726 1 0_0402_5%
2
24,37,39,42 LPC_AD0 LAD0 LPCPD# SUS_STAT# 26
HT-191NB_BLUE_0603 24,37,39,42 LPC_AD1 LPC_AD1 23 9 IN_TPM@ 1 2 +3VS
LPC_AD2 LAD1 TESTB1/BADD TPM_TEST1 R661 1 0_0402_5%
24,37,39,42 LPC_AD2 20 8 2
LAD2 TEST1
1
LPC_AD3 17 IN_TPM@ 4.7K_0402_5%
24,37,39,42 LPC_AD3 LAD3
14 TPM_XTALO R662
XTALO TPM@
4.7K_0402_5%
R663 HT-191UD_AMBER_0603 13 TPM_XTALI
820_0402_5% TPM XTALI @
Amber
+5VALW 1 2 2 1 LED4 CLK_PCI_TPM 21 SLB 9635 TT 1.1
2
CHARGE_LED0# 39 28 CLK_PCI_TPM LPC_FRAME# LCLK
24,37,39,42 LPC_FRAME# 22 2
R664 PLT_RST_BUF# LFRAME# GPIO2
Blue 6,28,35,37 PLT_RST_BUF# SERIRQ
16
LRESET# GPIO
6
+5VALW 1 2 2 1 LED5 CHARGE_LED1# 39 24,39 SERIRQ 27
820_0402_5% PM_CLKRUN# SERIRQ
26,39 PM_CLKRUN# 15
CLKRUN#
+3VS 1 2 7 PP NC 1
HT-191NB_BLUE_0603 R665 4.7K_0402_5% 3
IN_TPM@ NC C766 IN_TPM@
12
GND
GND
GND
GND
R666 NC 15P_0402_50V8J
HT-191UD_AMBER_0603
820_0402_5% Amber TPM_XTALI
2
+5VS 1 2 2 1 LED6 DVT, for debug, 0622 SLB-9635-TT-1.2_TSSOP28
4
11
18
25
WLAN_LED# 37
10M_0402_5%
R772 IN_TPM@ X3
1
R667 Blue @ 0_0402_5% 1 2
IN NC
IN_TPM@
1 2 2 1 LED7 CLK_PCI_TPM
+5VS BT_LED# 41
820_0402_5% 4 3
1
OUT NC
2
R668
HT-191NB_BLUE_0603 R669 32.768KHZ_12.5P_1TJS125BJ2A251
2
@ 10_0402_5% U36 6/17 Rual Add R772! IN_TPM@
TPM_XTALO
1
2 C767 IN_TPM@
15P_0402_50V8J
C768
@ 15P_0402_50V8J S IC WPCT200AA0WG TSSOP 28P TPM
1 WB_TPM@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
MDC/LED/Camera/FP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 47 of 61
A B C D E
+1.5V TO +1.5VS
+5VALW TO +5VS
+5VALW +5VS +3VALW TO +3VS
U38 +3VALW +3VS
8 1 +1.5V +1.5VS
D S
7 2 U39
D S
2
6 D S 3 1 8 D S 1
5 4 C769 R670 7 2
D G D S
2
6 3 1 U40
1 AO4468_SO8 470_0603_5% D S C770 R671 1
5 4 8 1 1 1
2
1U_0603_10V4Z D G 470_0603_5% D S C772 1U_0603_10V4Z
7 2
1
AO4468_SO8 D S C771
6 D S 3
2
1U_0603_10V4Z @
5 4
1
D G 2 2
1
Q31
D S TR SI4856ADY
1
R672 2 SUSP Q35
5VS_GATE G D
+VSB 1 2
S SSM3K7002FU_SC70-3 2 SUSP 10U_0805_10V4Z
3
47K_0402_5% R345 1 +VSB 1 2 G
D
1
200K_0402_5%
C773 R673 S SSM3K7002FU_SC70-3 +VSB 1 2
200K_0402_5%
3
SUSP 2 47K_0402_5% R344 1 R674
1
G 0.1U_0603_25V7K D C774 47K_0402_5% R346 1
1
Q25 2 SUSP D C775
S 2 6/17 Rual Add R346!
3
200K_0402_5%
SSM3K7002FU_SC70-3 G 0.1U_0603_25V7K SUSP 2
Q27 S 2 G 0.1U_0603_25V7K
3
SSM3K7002FU_SC70-3 Q26 S 2
3
DVT change R672.R673/R674 to 47K,R344,R345,R346 to 200k SSM3K7002FU_SC70-3
6/17 Rual Add R345! 3/12 Add by Vivian
J8
+1.5VS 2 1 +1.5VS_VRAM
+5VALW 2 1
@ JUMP_43X118
+5VALW
2
+1.5VS_VRAM J9 @
R677 +1.5V 2 1
2 1
2
100K_0402_5%
JUMP_43X118
R676
1
2 100K_0402_5% SUSP 2
SUSP 43,55 U44
8 1 need pop
1
D S
7 2
D D S
1
SYSON# 6 3
Q29 D S
39,43,51,53,54,55 SUSP# 2 5 4
D G
1
D G SSM3K7002FU_SC70-3
1
SYSON 2 Q28 S S TR SI4856ADY
3
39,53 SYSON
1
G SSM3K7002FU_SC70-3 C776 SG@
S R679 100P_0402_50V8J
3
1
2
10/31 Remove R1367
R678 10K_0402_5% SG@
+VSB 1 2
2
10K_0402_5% R858
47K_0402_5% R474 1
2
1
D SG@ C828
SG@
200K_0402_5%
VGA_ON# 2
G 0.1U_0603_25V7K
Q43 S 2
3
SSM3K7002FU_SC70-3
SG@
+5VALW
+5VALW
2
2
R864
R857 100K_0402_5% +1.8VS
100K_0402_5%
1
SG@ need pop
1
43 DGPU_PWR_EN#
VGA_ON# J12
1
3 D PAD-OPEN 3x3m +1.8VSDGPU 3
D
1
2 Q52 1 2
VGA_ON 25,29,43 DGPU_PWR_EN
2 Q41 G SSM3K7002FU_SC70-3
14,43,56,58 VGA_ON
G SSM3K7002FU_SC70-3 S @
3
1
SG@ S 10/31 Remove R1367 U60
3
1
10/31 Remove R1367 R863 8 1 1 1
R856 D S
7 2
10K_0402_5% D S C833 C831
6 3
10K_0402_5% D S SG@ SG@
5 4
2
SG@ D G 2 2
2
S TR SI4856ADY
SG@
10U_0805_10V4Z 1U_0603_10V4Z
+VSB 1 2
R859
47K_0402_5% R477 1 SG@
1
D C832
SG@
200K_0402_5%
VGA_ON# 2
G 0.1U_0603_25V7K
Q48 2
4/1 Modify by Vivian S
3
SSM3K7002FU_SC70-3 SYSON
+1.8VS +1.5VS +1.1VS_VTT +0.75VS +1.05VS
1
SG@ @
2
SG@ C780
R682 R683 R684 R685 R686 100P_0402_50V8J
470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 2
1
4 4
Q37 Q34 Q32 Q33 Q36
1
D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SUSP
G G G G G
S SSM3K7002FU_SC70-3
S SSM3K7002FU_SC70-3 S SSM3K7002FU_SC70-3 S SSM3K7002FU_SC70-3 S SSM3K7002FU_SC70-3
3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
DC Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NBLB2 M/B LA-5412P Schematic
Date: Tuesday, November 17, 2009 Sheet 48 of 61
A B C D E
A B C D
VIN
2
PD2
DC301001Y00 RLS4148_LL34-2
PL1 VIN
1
PJP1 ADPIN HCB4532KF-800T90_1812 PD3 51ON-1
4 4 1 2 BATT+ 2 1
1
3 3
2 RLS4148_LL34-2 PR9 PR10
2 PQ1 68_1206_5% 68_1206_5%
1 1
TP0610K-T1-E3_SOT23
0.01U_0402_50V7K
0.01U_0402_50V7K
0.01U_0402_50V7K
0.01U_0402_50V7K
1 1
@ SINGA_2DW-0268-B16 PR11
2
1
1
200_0603_5%
PC2
PC3
PC4
PC5
CHGRTCP 1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
2
1
PC8
PR12 PC9
100K_0402_1% 0.1U_0603_25V7K
2
PR13
2
22K_0402_1%
1 2 51ON-3
40,42 51_ON#
RTCVREF
1
Change BATT1 P/N : SP093PA0200 (Panasonic) PR14
RTC Battery SP093MX0000 (MAXELL)
+CHGRTC
PR15 PR16
PU2
G920AT24U_SOT89-3
200_0603_5%
560_0603_5% 560_0603_5% 3.3V
2
9/29 modified to follow ISKAA 1 2 RTCVREF-1
1 2 3 OUT IN 2CHGRTCIN
PD8
1
+RTC_BATT GND PC11
- BATT1 + PR247
2 +CHGRTC
PC10
10U_0805_10V4Z 1
1U_0805_25V4Z
2
2 1 +RTCBATT 1 2 1
511_0603_1% 3 +RTCVCC 1 2
PQ12
2
ML1220T13RE PR220 TP0610K-T1-E3_SOT23 2
1
@ BAS40-04_SOT23 PD10 1K_1206_5%
PC181 2 1 N3 1 2 3 1
0.1U_0402_16V4Z VIN B+
2
RLS4148_LL34-2 PR221
9/29 Checked. Same as HEL80's 1K_1206_5%
1 2
100K_0402_5%
100K_0402_5%
1
1
1K_1206_5% PR222
PR38
PR36
2
Reserve another location <BOM Structure>
<BOM Structure>
1
BOM structure comment
100K_0402_5%
1
PR156
PR37
@ ==>unpop 499K_0402_1%
1
06/24 Rual remove BATT2!
2
<BOM Structure>
NV@==>Nvidia sku only
1 2
2
M97@==>ATI sku only 39,51 ACOFF
SP093MX0000 PJ15
2 1 PQ52 2
+VGFX_COREP +VGFX_CORE
3
2 1 DTC115EUA_SC70
@ JUMP_43X118 DTC115EUA_SC70
PJ21 @ PQ11
3
PJ1 2 1 PR166 PR217
3
2 1 100K_0402_1% 2.2M_0402_5%
3
+3VALWP 2 2 1 1 +3VALW JUMP_43X118 1 2 2 1
@ JUMP_43X118 VL
PJ16 @ VS
PJ2
0.01U_0402_25V7K
+1.8VSP 2 2 1 1 +1.8VS
+5VALWP 2 2 1 1 +5VALW JUMP_43X118
PC21
@ JUMP_43X118
PJ20 @
PJ9
2
2 1 PD11
+1.8VSP_LDO 2 1
8
+1.0VSP 2 1 +1.1VS RB715F_SOT323-3
2 1 JUMP_43X118 2 5
P
50,52 MAINPWON +
1 7 O
JUMP_43X79 PJ19 @
51 ACON 3 - 6 2 1 VL
1
G
@ +VDDCIP 2 1 +VDDCI PU5B
2 1
1
PJ4 PC157 LM393DG_SO8 PR223 PR218 PR118 PC26
1
2 1 JUMP_43X118 1000P_0402_50V7K 34K_0402_1% 191K_0402_1%499K_0402_1% 1000P_0402_50V7K
+1.5VP +1.5V
2
2 1
1
@ PJ10
2
@ JUMP_43X118 2 2 PC158 PR219
+VGA_COREP 1 1 +VGA_CORE
2
1000P_0402_50V7K 66.5K_0402_1%
2
PJ5 @ JUMP_43X118 PR224
1
D 47K_0402_1%
2 2 1 1
@ PJ12 2 2 1 PACIN 50,51
JUMP_43X118 2 2 1 G
1 PQ10
S
1
PJ7 JUMP_43X118 SSM3K7002FU_SC70-3
+0.75VSP 2 2 1 1 +0.75VS PJ13
@ JUMP_43X79 2 1
Precharge detector
2 1
4
@ JUMP_43X118 15.97V/14.84V FOR 2 +5VALWP 4
2
PJ11 @
1 2 2
PJ6
ADAPTOR PQ9
+1.5VS_VRAMP 2 1 +1.5VS_VRAM +1.1VS_VTTP 1 1 +1.1VS_VTT DTC115EUA_SC70
3
JUMP_43X118 @ JUMP_43X118
1
PJ14 For Arrandale use
PJ8 @ PJ22
1
+VSBP 2 1 +VSB 2 1 JUMP_43X118
2 1 2 1
@
Security Classification Compal Secret Data Compal Electronics, Inc.
2
JUMP_43X118 2009/02/04 2010/02/04 Title
Issued Date Deciphered Date
@ JUMP_43X79
DCIN & DETECTOR
2
PJ3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2 1 Size Document Number Rev
+1.05VSP 2 1 +1.05VS AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
@ JUMP_43X118
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Tuesday, November 17, 2009 Sheet 49 of 61
A B C D
A B C D
BATT++
DC040003600
PL24
HCB4532KF-800T90_1812
PH1 under CPU botten side :
BATT+
1 2 CPU thermal protection at 92 degree C
PJP2
1
1 BATT++ 1 2
Recovery at 70 degree C 1
1 +3VALW
2 VS
2
1000P_0402_50V7K
1000P_0402_50V7K
3 CNT1 PR18 @ PR17
3 CNT2
0.01U_0402_50V7K
4 1 2 100K_0402_1%
4 +3VALW
1
EC_SMCA VL
0.1U_0603_25V7K
5 5
1
VL
PC13
PC14
PC15
6 EC_SMDA @ 100K_0402_1%
6
PC12
7 TS_A
2
7
2
1K_0402_1%
150K_0402_1%
8 GND
2
8
2
10K_0402_1%
PR22
9
2
9
PR19
G1 10
PR23
11 PR21 PR20
G2 1K_0402_1% 1 442K_0603_1%
2
1
SUYIN_200275MR009G180ZR
1
<BOM Structure>
2
PR24
8
88.7K_0603_1%
5
P
+
100_0402_1%
O 7 MAINPWON 49,52
1
1
100_0402_1%
TM_REF1 6 -
G
PR25
PR26
PU1B
100K +-1% NCP15WF104F03RC 0402
1
LM393DG_SO8
4
PH1
2
1000P_0402_50V7K
1U_0603_6.3V6M
2
1
PC16
PC17
PR27
EC_SMB_CK1 39,41
2 150K_0402_1%
1 VL
2
EC_SMB_DA1 39,41
150K_0402_1%
2 2
1
1 2 +3VALW
PR28
PR29
1K_0402_1%
6.49K_0402_1%
1
2
PR30
<BOM Structure>
2
BATT_TEMP 39
PQ2
TP0610K-T1-E3_SOT23-3
B+ 3 1 +VSBP
PR1
Vin Detector
0.22U_1206_25V7K
0.1U_0603_25V7K
1M_0402_1%
1
100K_0402_1%
1 2
1
1
VIN
PR31
PC18
PC19 VINDE-2
VS
VIN
High 18.384 17.901 17.430
2
Low 17.728 17.257 16.976
0.01U_0402_25V7K
PR32
2
10K_0805_5%
22K_0402_1%
1
VL 1 2
PC1
PR3
10K_0402_1%
3
PR2 PR4 3
2
84.5K_0402_1% 10K_0402_1%
2
PR33
1 2 ACIN 39
2
PR5
8
22K_0402_1%
PR34 VINDE-1 1 2 3
P
1
+
1
0_0402_5% D PACIN
0.068U_0603_16V7K
O 1 PACIN 49,51
1 2 2 PQ3 VINDE-3 2
52 SPOK -
G
20K_0402_1%
10K_0402_1%
SSM3K7002F_SC59-3 PU1A
0.1U_0402_16V7K
RLZ4.3B_LL34
G
1
0.1U_0402_16V7K
S LM393DG_SO8
3
4
1
PC6
PR6
PC7
PR7
PC20
PD1
2
2
2
2
PR8
2
10K_0402_1%
2 1 RTCVREF 3.3V
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Tuesday, November 17, 2009 Sheet 50 of 61
A B C D
5 4 3 2 1
B+
PQ4 P2 PQ5 P3
PR35
0.015_1206_1%
B+ CHG_B+ PQ6
PL2
AO4407_SO8 AO4407_SO8 AO4407_SO8
VIN 8 1 1 8 1 4 1 2 1 8
7 2 2 7 2 7
6 3 3 6 2 3 HCB4532KF-800T90_1812 CSIN 3 6
5 5 5
4.7U_1206_25V6K
4.7U_1206_25V6K
4.7U_1206_25V6K
CSIP
4
1
D D
1
PQ60 TP0610K-T1-E3_SOT23-3 PR262 1 PR228 2 VIN
PC22
PC23
PC24
PQ58 PR243 10_0603_5%
2
DTA144EUA_SC70-3 200K_0402_1% 3 1 2 1 DCIN 47K_0402_1%
P3
2
PC206 PR268 PD14
2
1
1
2 5600P_0402_25V7K 10K_0402_1% 1 2 ACOFF
1
PC202 PR230 PQ61
1
PR244 0.1U_0603_25V7K 100K_0402_1% DTC115EUA_SC70-3 1SS355_SOD323-2
1
47K_0402_1% PR251
PR272 PD15 200K_0402_1%
2
1
100K_0402_1% 2 FSTCHG 1 2 VIN
1
2
1
PD16 2 1 2 1
1SS355_SOD323-2 3 SUSP# 39,43,48,53,54,55
1 2 6251VDD PQ62 PD17
2.2U_0603_6.3V6K
RB715F_SOT323-3 DTC115EUA_SC70-3 2 1 2
PC207
2 PR261
3
1
PQ59 10K_0402_1% 1SS355_SOD323-2
DTC115EUA_SC70-3 2 1 PU3 PC211
39 FSTCHG
0.1U_0603_25V7K
3
1
1
D D
100K_0402_1%
1 2 1 24 DCIN 2 1
3
VDD DCIN
1
1
2 PQ64 PC209 2 PACIN
PR253
G SSM3K7002FU_SC70-3 PC208 0.1U_0603_25V7K G
S PR229 0.1U_0402_16V7K 2 23 S PQ57
3
3
150K_0402_1% ACSET ACPRN PR258 SSM3K7002FU_SC70-3
20_0603_5%
2
2
6251_EN 3 22 1 2 CSON
EN CSON
2
PC210 PC212
5
6
7
8
@ 680P_0402_50V7K 0.047U_0603_16V7K
CSON 1 2 4 21 1 2 CSOP
1
CELLS CSOP PR270 PQ7
PC213 6800P_0402_25V7K 20_0603_5% AO4466_SO8
1 2 5 20 2 1
ICOMP CSIN
1
2
C D PR254 C
4
2 PQ55 PC214 PR255 6.81K_0402_1% PC215 20_0603_5%
G SSM3K7002FU_SC70-3 1 2 1 2 6 19 0.1U_0603_25V7K1 2
1
PR257 VCOMP CSIP PL3 PR42
S
3
0.01U_0402_25V7K 1 2 47K_0402_1% PR256 10U_LF919AS-100M-P3_4.5A_20% BATT+
3
2
1
PR252 PC165 1 2 7 18 LX_CHG 2.2_0603_5% 1 2 CHG
1 4
22K_0402_5% @ 100P_0402_50V8J ICM PHASE
5
6
7
8
PACIN 1 2 1 2 2 3
49,50 PACIN
10U_1206_25V6M
10U_1206_25V6M
6251VREF 8 17 DH_CHG
PC159 0.1U_0402_16V7K VREF UGATE PR259 PC160
49 ACON 39 ADP_I
2.2_0603_5% 0.1U_0603_25V7K PR83 0.02_1206_1%
1
PC35
PC36
2 PR269 1 BST_CHG 1 BST_CHGA 2 @ 4.7_1206_5%
1 5V_SNB
39 IREF 9 16 2 1
CHLIM BOOT
1
1
PQ63 80.6K_0402_1% pr263 4 PQ8
2
0.01U_0402_25V7K
DTC115EUA_SC70-3 59K_0402_1% PD18 AO4466_SO8
2
6251VREF 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1
1
PC169
ACOFF 2 PR260 1 2 6251VDD
3
2
1
39,49 ACOFF
100K_0402_1% PR264 11 14 DL_CHG PC176
2
VADJ LGATE
2
20K_0402_1% PR271 @ 680P_0603_50V7K
2
4.7_0603_5%
2
12 13 PC161
3
1
GND PGND 4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
PR274 <BOM Structure>
15.4K_0402_1% VIN
39 CHGVADJ 1 2
1
PR266
1
31.6K_0402_1%
B PR226 B
309K_0402_1% IREF Current
2
PR225
2
10K_0402_1% 2.968V 3A
1 2 ADP_V 39
1
Iada=0~4.74A(90W) CP= 92%*Iada; CP=4.312A PR265
PC175
47K_0402_1%
0.1U_0402_16V7K
2
2
CP mode
Vaclim=2.39*(20K//152K/(20K//152K+24K//152K))=1.09986V
Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)
where Vaclm=1.09986V, Iinput=3.65A
8
3
P
+
O 1
CC=0.25A~3A CHGVADJ=(Vcell-4)*9.445 2
-
G
PU5A
IREF=1.016*Icharge Vcell CHGVADJ LM393DG_SO8
4
IREF=0.254V~3.048V 4V 0V
VCHLIM need over 95mV 4.2V 1.898V CHGVADJ Pre Cell
4.35V 3.315V
A
3.3V 4.35V A
0V 4V
CELLS VDD GND Float
"CHGVADJ" connect to EC DA pin
CELL number 4 3 - 2
Title
LI-3S :13.5V----BATT-OVP=1.5V <Title>
BATT-OVP=0.1112*BATT+ Size Document Number
Custom<Doc>
Rev
<RevCode>
Date: Tuesday, November 17, 2009 Sheet 51 of 61
5 4 3 2 1
5 4 3 2 1
Iocp=Iv+I/2; Iv=(5uA*301K)/(10*18m)=8.36A
I=(19-3.3)3.3/19*4.7UH*300K=1.93AIocp=8.36+1.93/2=9.32A
ISL6237_B+ Iocp=(Iv+I/2)/1.3;
ISL6237_B+ Iv=(5uA*301K)/(10*18m)=8.36A ;
B+
I=(19-5)5/19*4.7UH*400K=1.96A;
PL4
PR67 Iocp=(8.36+1.96/2)=9.34A
0_0402_5%
1 2 1 2
2200P_0402_50V7K
10U_1206_25VAK
HCB4532KF-800T90_1812
2200P_0402_50V7K
10U_1206_25VAK
D D
5
6
7
8
1
PC53
PC54
PC56
8
7
6
5
PC55
1U_0603_10V6K
VL
2
2
2
PC58
PQ13 PC57
AO4466_SO8 0.1U_0603_25V7K
4.7U_0805_6.3V6K
4
3/5V_VCC
1
1
3/5V_VIN
4
PC59
PQ16 +5VALWP
2
AO4466_SO8
3
2
1
PL5
1
2
3
PL6 4.7UH_SIL104R-4R7PF_5.7A_30%
7
4.7UH_SIL104R-4R7PF_5.7A_30% PU6 PC60 2 1
1 2 1U_0603_10V6K
LDO
V5FILT
VIN
+3VALWP 33 19 1 2
TP V5DRV
5
6
7
8
1
PQ15
8
7
6
5
UG3 26 15 HG5 AO4712_SO8
PR68 DRVH2 DRVH1 PR69
0_0402_5%
4.7_1206_5% PQ14 BST3A-1 1 2 BST3A 24 17 BST5A1 2 BST5A-1 4.7_1206_5% 1
VBST2 VBST1
2
1 AO4712_SO8 2.2_0603_5% PR70 2.2_0603_5% PR71
2
2
2
+
PR72
61.9K_0402_1%
4
1 3V_SNB
2
+ 4 PC62
2
0.1U_0603_25V7K PC64
1
2 220U_6.3VM_R15
@ PR73
SW3 25 16 SW5
1
PC61 2 PC66 LL2 LL1 PC63 <BOM Structure>
3
2
1
220U_6.3VM_R15 680P_0603_50V7K 0.1U_0603_25V7K PC65
1
2
3
2
<BOM Structure> 2 LG3 23 18 LG5 680P_0603_50V7K
1
DRVL2 DRVL1
@ 10K_0402_1%
2
PGND 22
2
C C
PR74
FB3 30 VOUT2
0_0402_5%
PR75
VOUT1 10
32
VL
1
REFIN2
1
11 FB5
2VREF_ISL6237 FB1
1 2 1 VREF2
PC67
0.22U_0603_25V7K 9
@ VSW
8 LDOREFIN
PD5
RB751V-40TE17_SOD323-2 29 5V_SKIP 2 1
SKIPSEL PR76
VL
1 2
@ 0_0402_5%
1 2
20 28 PR77
PD6 PR78 NC PGOOD2 0_0402_5%
VS RLZ5.1B_LL34 100K_0402_1%
EN_LDO-1 EN_LDO SPOK 50
1 2 1 2 4 EN_LDO PGOOD1 13
2
200K_0402_5%
2
PR79
PC68 3/5V_EN1 14 12 ILM1 2 1
0.22U_0603_25V7K EN1 TRIP1 PR80
VS 301K_0402_1%
TONSE
VREF3
1
27 31 ILIM2 2 1
GND
1
EN2 TRIP2
PR81
2
2
RT8206BGQW QFN 32P 301K_0402_1%
21
1
B @ PR277 B
1 3/5V_NC
PD7 0_0402_5%
RB751V-40TE17_SOD323-2 PR82
13/5V_TON
0_0402_5%
1
1
@
PR85 1U_0603_10V6K
2
PC69
2VREF_ISL6237
47K_0402_5%
PR84
49,50 MAINPWON 2 1 1 2
2
0.1U_0402_16V7K
0_0402_5% PR86
@ 0.047U_0402_16V7K
0_0402_5%
2
080414:PQ23 ,Del @
2
PC70
PC71
PQ42
3
2VREF_ISL6237
2
TP0610K-T1-E3_SOT23-3
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Tuesday, November 17, 2009 Sheet 52 of 61
5 4 3 2 1
5 4 3 2 1
D D
PL7
VCCP_IN 1 2 B+
FBMA-L11-321611-121LMA_2
5
6
7
8
10U_1206_25VAK
<BOM Structure>
1
PC72
PR88
2
300K_0402_5% 4
VCCP_TON 1 2 PQ17
PR89 PR90 AO4466_SO8
PC73
61.9K_0402_1% 2.2_0603_5%
1 2 VCCP_EN BST_VCCP1 2BST_VCCP-1
1 2 Ipeak=6.6A
3
2
1
39,43,48,51,54,55 SUSP#
0.1U_0603_25V7K
1
PL8
15
14
1
PC74 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
0.1U_0402_16V7K 1 2
VBST
EN_PSV
TP
+1.05VSP
4.7_1206_5%
2 13 UG_VCCP
TON DRVH
PR91
PR92 SW_VCCP
220U_D2_4VY_R15M
3 VOUT LL 12
5
6
7
8
10U_0805_6.3V6M
100_0603_1% 1
+5VALW 1 2 VCCP_V5FILT 4 11 VCCP_TRIP
1 2 +5VALW
1 VCCP_SNB2
V5FILT TRIP
1
+
PC76
PC77
PR93
AO4712_SO8
VCCP_FB 5 10 16.5K_0402_1%
VFB V5DRV
2
1
6 9 LG_VCCP 4 2
PGOOD DRVL
PGND
C C
PQ18
PC78
GND
1
4.7U_0603_6.3V6M PC80
2
680P_0603_50V7K
@ 47P_0402_50V8J PC79
PC81
1 2 4.7U_0805_10V6K
3
2
1
PU7
2
TPS51117RGYR_QFN14_3.5x3.5
PR94
12.7K_0402_1%
1 2
1
PR95
VFB=0.75V
31.6K_0402_1%
PR276 @
2
1 2 +3VS PL9
3.4K_0402_1% 1.5V_IN 1 2 B+
2 PR278 1 PCIE_OK 43,55,56 FBMA-L11-321611-121LMA_2
5
6
7
8
10U_1206_25VAK
0_0402_5% @ PQ20
1
AO4474_SO8
PC82
PR96
2
300K_0402_5% 4
1.5V_TON 1 2
PR97 PR98
PC83
0_0402_5% 2.2_0603_5%
1 2 1.5V_EN BST_1.5V 1 2 BST_1.5V-1
1 2
39,48 SYSON
3
2
1
B B
0.1U_0603_25V7K
1
PL10 Ipeak=22A
15
14
1
PC84 1UH_PCMB103E-1R0MS_20A_20%
0.1U_0402_16V7K 1 2
VBST
EN_PSV
TP
+1.5VP
2
4.7_1206_5%
2 13 UG_1.5V
TON DRVH
PR99
PR100 SW_1.5V
560U_6.3VM_R15
<BOM Structure>
3 VOUT LL 12
5
6
7
8
10U_0805_6.3V6M
100_0603_1% 1
1 2 1.5V_V5FILT 4 11 1.5V_TRIP
1 2 +5VALW PQ21
+5VALW
1.5V_SNB 2
V5FILT TRIP
1
+
PC85
PC86
PR101
1.5V_FB 5 10 11K_0402_1% AO4456_SO8
VFB V5DRV
1
2
PC87 6 9 LG_1.5V 4 2
PGOOD DRVL
PGND
4.7U_0603_6.3V6M
GND
2
PC88
1
680P_0603_50V7K
@ 47P_0402_50V8J PR102
PC90
1 2 100K_0402_1% PC89
7
3
2
1
1 2 PU8 4.7U_0805_10V6K
+1.5VP
2
2
TPS51117RGYR_QFN14_3.5x3.5
PR103
1.5V_PGOOD
22.1K_0402_1%
1 2
1
VFB=0.75V
PR104
21K_0402_1%
2
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5V/VCCP/0.75V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Tuesday, November 17, 2009 Sheet 53 of 61
5 4 3 2 1
5 4 3 2 1
PL12
FBMA-L11-321611-121LMA_2
1 2 VTT_B+
B+
PR116 +5VS
0_0402_5%
10U_1206_25VAK
10U_1206_25VAK
1 2
6 H_VTTPWRGD LX_VTT
3.4K_0402_1%
PC105
PC106
Layout Note: DH_VTT
PR117
PR119
Place near high-side MOS Drain
2
BST_VTT 1 2 1 2
and low-side MOS Source PR120 2.2_0603_5%
2
D 1K_0402_1% PC107 D
1 2 +5VS 0.1U_0603_25V7K
5
PR121
0_0603_5%
PR122
16
15
8
1
PU500 4.7_0603_5%
2
1 2 6268_VTT 4
UG
BOOT
PHASE
GND
PGOOD
Layout Note: PQ25
3 VIN PVCC 14 1 2
Close IC DCR=2.7mΩ Ipeak=18A
TPCA8030-H_SOP-ADV8-5
3
2
1
PC108
2.2U_0603_6.3V6K PL13
@ PR208 6268_VTT 4 13 DL_VTT
0_0402_5% VCC LG 0.47UH_FDV0630-R47M-P3_18A_20%
39 VTTP_EN 1 2 1 2 +1.1VS_VTTP
1
APW7138NITRL_SSOP16
1
PC109 12
2.2U_0603_6.3V6K PGND PR123
2
PR124
510K_0402_1% 4.7_1206_5%
1 2 5 11 ISEN_VTT
1 2
39,43,48,51,53,55 SUSP#
1 2
EN ISEN
4 4 1
1
PR125
FSET
1
6.19K_0402_1% PC111 + PC112
NC
VO
FB
@ PR126 PC110 560U_6.3VM_R15
Rds=4.0mΩ
2
10K_0402_5% 0.1U_0402_16V7K 680P_0603_50V7K
10
3
2
1
3
2
1
C PQ26 2 C
2
TPCA8028-H_SOP-ADVANCE8-5
@ PQ27
TPCA8028-H_SOP-ADVANCE8-5
49.9K_0402_1%
1
57.6K_0402_1%
Material Note:
1
22P_0402_50V8J
Layout Note: 330uF/6 mΩ, number
1
PR127
Close IC PC113 are 3, Power 1, HW 2
PR128
6800P_0402_25V7K
@PC500
@ PC500
0.01U_0402_25V7K
2
2
2
PR250
1
PC115
1 2
VTT_SENSE 8
Imax=18.0A
2
10_0402_1%
Ipeak=21.0A
PR249 Iocp=25.2A
1 2 2 1 +1.1VS_VTTP
VFB=0.6V PR130 0_0402_5%
12.4K_0402_1%
B +3VS B
180K_0402_1%
2
PR132
PR131
2
162K_0402_1%
1
+3VS
1
100K_0402_1%
PR134
1
1
D 4.7K_0402_5%
PR133 2 2 1
PR135
15.8K_0402_1% G
S
2
1
PQ28
0.1U_0402_16V7K
2N7002W-T/R7_SOT323-3
PC116
1
2
1
2 2 1 H_VTTVID1 8
0.01U_0402_25V7K
PR136
3
PMBT2222A_SOT23-3
PQ29 10K_0402_5% Voltage Select
100K_0402_1%
2
VID Vout
PC117
PR137
High 1.05 V
2
Low 1.1 V
A 1 A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.1VS_VTT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Tuesday, November 17, 2009 Sheet 54 of 61
5 4 3 2 1
5 4 3 2 1
Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=13k*9u/15m+1/2*2.7=9.15A
PL21@
VRAM_IN 1 2 B+
FBMA-L11-321611-121LMA_2
10U_1206_25VAK
1
@
PC91
@ PR105 PQ22
2
300K_0402_5% 4
VRAM_TON 1 2 AON7408L_DFN8-5
PR106 @ @ PR107 @
200K_0402_1% 2.2_0603_5%
D D
1 2 VRAM_EN BST_VRAM1 2 BST_VRAM-1
1 2
3
2
1
39,43,48,51,53,54 SUSP#
@ PC93 Ipeak=8A
0.1U_0603_25V7K
15
14
1
1
@ PL11
PC92 @ 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
VBST
EN_PSV
TP
0.1U_0402_16V7K 1 2 +1.5VS_VRAMP
2
2 13 UG_VRAM
TON DRVH
4.7_1206_5%
3 12 SW_VRAM
VOUT LL
PR108
PR110 @ @
10U_0805_6.3V6M
100_0603_1% VRAM_V5FILT VRAM_TRIP
220U_6.3VM_R15
4 V5FILT TRIP 11 1 2 1
+5VALW 1 2 PR109 +5VALW
VRAM_SNB2
1
+
PC94
PC95
VRAM_FB 5 10 16.5K_0402_1% @
VFB V5DRV
6 9 LG_VRAM
2
PGOOD DRVL
1
2 @
PGND
4 @
GND
680P_0603_50V7K
@ PC96
4.7U_0603_6.3V6M @ PC97
1
47P_0402_50V8J
PC99
1 2 PU9 @ @ PC98
3
2
1
TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K
2
@
@ PR111
21.5K_0402_1% @ PQ23
1 2 AON7702L_DFN8-5
1 PR165 @
VFB=0.75V
PR112 @ 1 2 +3VS
21K_0402_1%
C 3.4K_0402_1% C
2
2 PR129 1 PCIE_OK 43,53,56
0_0402_5% @
PR234
200K_0402_1%
1 2 SUSP# 39,43,48,51,53,54
2
1
316K_0402_1% PC182
PR227 0.22U_0402_10V4Z
2
PR233
402K_0402_1% PU12
1
+1.8VSP 2 1 1 FB EN/SYNC 10
PC156 2 9 PL22
0.1U_0402_16V7K GND GND 2.2UH_MMD-06AH-2R2M-X2A_6A_20%
@ 1 2 3 8 1 2 +1.8VSP
PJ28 SW SW
+5VALW
1 1 2 2 4 IN IN 7
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0402_25V6
10U_0805_10V4Z
10U_0805_10V4Z
1 2 5 BS POK 6
JUMP_43X79
B340A_SMA2
PR232 PR231
1
1
PC185
PC184
PC179
PD19
PC183
PC177
0_0402_5% 11 4.7_1206_5%
TP
2
MP2121DQ-LF-Z_QFN10_3X3
2
2
2 @
1
B B
PC178
680P_0603_50V7K
2
+3VS
PR281
1 2 +3VS
1
3.4K_0402_1%
PJ609
1
2 PR282 1 PCIE_OK 43,53,56
JUMP_43X79
+1.5V
2
0_0402_5%
PU604
2
LDO_1.8V_IN 1 6
VIN VCNTL +5VALW
1
2 GND NC 5
1
PJ17 PC623
1
1
@ JUMP_43X79 4.7U_0805_6.3V6K 3 7 PC624
PR623 VREF NC 1U_0603_6.3V6M
2
2
1K_0402_1% 4 8
PU10 VOUT NC
2
1 6 +3VALW 9
2
VIN VCNTL TP
2 5 LDO_1.8V_REF APL5331KAC-TRL_SO8
GND NC
1
PC100
1
1
4.7U_0805_6.3V6K 3 7 PC101 PR626 +1.8VSP_LDO
VREF NC
1
PR113 1U_0603_6.3V6M 330K_0402_1% D PR628
2
PR114 1K_0402_1% 4 VOUT NC 8 43,48 SUSP 1 2LDO_1.8V_EN 2 1.24K_0402_1% PC627
1
1 2 G 0.1U_0402_16V7K
43,48 SUSP
2
1
A 9 S PC629 A
2
2
330K_0402_1% TP PC631 10U_0805_6.3V6M
2
APL5331KAC-TRL_SO8 0.1U_0402_16V7K PQ609
2
1
+0.75VSP
1
D PR115
2 1K_0402_1% PC102 2N7002W-T/R7_SOT323-3
1
G 0.1U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
2
1
S PC103
3
PC104 10U_0805_6.3V6M 2009/02/04 2010/02/04 Title
Issued Date Deciphered Date
2
0.1U_0402_16V7K
VGA_CORE/1.8V/1.1V
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
PQ24 Custom 0.1
2N7002W-T/R7_SOT323-3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Tuesday, November 17, 2009 Sheet 55 of 61
5 4 3 2 1
5 4 3 2 1
PL14
1 2
B+
HCB4532KF-800T90_1812 Iocp=(Iv+I/2)/1.3; Iv=(19uA*5.1K)/(1.3*1.75m)=42.59A ;
@ PR279
D
2 1
I=(19-0.9)0.9/19*1UH*231K=3.71A; Iocp=(42.59+3.71/2)=44.44A D
+3VS
LX_VCORE
10U_1206_25VAK
10U_1206_25VAK
3.4K_0402_1%
10U_1206_25VAK
DH_VCORE
1
1 PR280 2 PR138
43 DGPU_PWROK
PC118
PC119
PC120
BST_VCORE
1 2 1 2
@ 0_0402_5% 0_0603_5%
2
PC121 0.1U_0603_25V7K
+5VS
5
PR139
0_0603_5% PQ30 Ipeak=28A
16
15
8
1
PU600
2
1 PR1402 6268_VCORE
UG
BOOT
PHASE
GND
PGOOD
4
4.7_0603_5%
3 14 1 2 PC122 DCR=1.1m OHM
VIN PVCC
2.2U_0603_6.3V6K TPCA8030-H_SOP-ADV8-5
3
2
1
6268_VCORE 4 13 DL_VCORE PL15
VCC LG S COIL 0.36UH +-20% SF-I104-R36 23A
1
PC123 1 2 +VGA_COREP
2.2U_0603_6.3V6K APW7138NITRL_SSOP16
1
12
2
PGND PR142
330U_D2E_2.5VM_R9M
330U_D2E_2.5VM_R9M
4.7_1206_5% 1 1
PR141
0_0402_5%
PR143
+ +
PR144
1 2 5 11 ISEN_VCORE
1 2
1 2
14,43,48,58 VGA_ON EN ISEN
PC124
PC125
4 4
C 47K_0402_1% C
FSET
9.09K_0402_1% PC126
1
2 2
NC
VO
FB
1
680P_0603_50V7K
2
6
10
3
2
1
3
2
1
PC127
2
PR146
0.1U_0402_16V7K
PQ31 PR145 1 2 +VGASENSE 15
TPCA8028-H_SOP-ADVANCE8-5 @ PQ32 9.76K_0402_1%
TPCA8028-H_SOP-ADVANCE8-5
10_0402_1%
1
22P_0402_50V8J
VFB=0.6V Rds=3.2mOHM
1
1
PR147
2200P_0402_25V7K
PC128
PR148
49.9K_0402_1% @ PC600
0.01U_0402_25V7K
2
2
+3VS
PC130
2
1
PR149
1
44.2K_0402_1% 90.9K_0402_1%
PQ33 PR150
2
2N7002W-T/R7_SOT323-3 10K_0402_5%
PR152
1
PR151 D 10K_0402_5%
2
20K_0402_1% 2 1 2
G PR153
1
D 10K_0402_5%
S
3
PR213
1
@ 2 1 2 GPU_VID1 14
GPU_VID1 GPU_VID0 VGA_CORE 16 +VGAVSSSENSE 1 2 PC131 G
2
S
3
0 0 1.05V 10_0402_1% 0.22U_0402_10V4Z PR154
10K_0402_5%
B 1 0 1.0V B
PQ34
1
0 1 0.95V PR155 2N7002W-T/R7_SOT323-3
39K_0402_1%
0 0 0.9V
+3VS
1
+1.5VS_VRAM PR157
10K_0402_1%
1
1
D PR158
2
PJ18 2 1 2
1
JUMP_43X79 +5VS PQ35 G 10K_0402_5% PR161
1
2N7002W-T/R7_SOT323-3 D 10K_0402_5%
S
1
2
2 1 2 GPU_VID0 14
G
2
PC132 S
3
1U_0603_6.3V6M
2
2
1
PR163
PC133 PU13 10K_0402_5%
4.7U_0805_6.3V6K 6 +1.0VSP PQ36
2
VCNTL PC136 2N7002W-T/R7_SOT323-3
5 3
1
VIN VOUT
1
PR159 9 4 0.22U_0402_10V4Z
VIN VOUT
1
22U_0805_6.3V6M
330K_0402_1%
PC135
1 2 8 PR160 PC134
2
14,43,48,58 VGA_ON EN
7 2
GND
POK FB 1.07K_0402_1%
1
PC137 APL5912-KAC-TRL_SO8 0.01U_0402_25V7K
1
A 0.1U_0402_16V7K +3VS A
2
PR164
1 2 PR162
3.92K_0402_1%
@ 4.7K_0402_5%
2
PR273
2 1
@ 0_0402_5%
PCIE_OK 43,53,55 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
VFB=0.8V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE/1.1VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Tuesday, November 17, 2009 Sheet 56 of 61
5 4 3 2 1
8 7 6 5 4 3 2 1
HFM_VID HFM_Icc LL Icc_TDC Icc_Dyn
H PH0 PH1 # of PH Auburndale 45W 1.075 50 1.9m 37 35 H
0 1 2 Auburndale 35W 0.975 38 1.9m 29 27
1 1 3 Clarksfield SV 0.95 51 1.9m 38 39
+5VS Clarksfield XE 0.95 65 TBD 48 TBD
8
H_DPRSLPVR
8
8
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
8
H_PSI#
1
+CPU_B+ PL16
PR173 FBMA-L18-453215-900LMA90T_1812
10_0603_5%
26
VR_ON
2 1 B+
2
G G
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
2200P_0402_50V7K
0.1U_0603_25V7K
220U_25V_M
499_0402_1%
1
PC142
PC141
PC138
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1
1
PC172 +
PC139
PC143
2
2
2
+3VS +5VS 1U_0603_16V6K
PC140
5
2
+3VS PR185 @ 2
1
0_0603_5%
2
2
PR52
PR49
PR202
PR204
PR203
PR211
PR210
PR209
PR197
2 1
PR179
2
3K_0402_5% 3212_DRVH1 4
3K_0402_5%
0_0402_5% PL17
1 PGND PQ40
PR178
PU14
1
PR188 0_0402_5% 0.36UH_SF-I104-R36_23A_20%
AGND
48
47
46
45
44
43
42
41
40
39
38
37
TPCA8030-H_SOP-ADV8-5
1
3
2
1
1 2 CLK_EN# 3212_SW1 1 4
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PH0
PH1
PSI
VCC
DPRSLP
23 CLK_ENABLE# +CPU_CORE
PR172 0_0402_5%
2
+1.05VS PR196 PC153
PR189
2 3
5
1 2 0_0603_5% 0.1U_0603_25V7K DCR=1.1m OHM
1
F 23,26 VGATE F
1 36 2 1 2 1
EN BST1
1
1
PR630
4.7_1206_5% PR170
@ PR214 2 35 3212_DRVH1 @ 10_0402_5%
0_0402_5% PWRGD DRVH1 3212_DRVL1 3212_DRVL1
4 4
1 2
2
2
IMVP_IMON 3 34 3212_SW1
2
8 IMVP_IMON IMON SW1 PC632
PR212
1
680P_0603_50V7K
3
2
1
3
2
1
3212_CS_PH1
4.53K_1% PR55 PC174 CLK_EN# 4 33 1 2 3212_CS_PH1 @
4.53K_0402_1% CLKEN SWFB1
0.1U_0402_16V7K
2
CSREF
PQ38
1
3212_FBRTN 1K_0402_1% @ PQ39
1 2 5 32 +5VS
FBRTN PVCC TPCA8028-H_SOP-ADVANCE8-5
PC46 PC145 150P_0402_50V8J 12P_0402_50V8J TPCA8028-H_SOP-ADVANCE8-5
1
1000P_0402_50V7K 1 2 3212_FB PC154 6 31 3212_DRVL1 +CPU_B+
FB DRVL1 PC146
ADP3212MNR2G_QFN48_7X7
1
PC152 4.7U_0603_6.3V6M
2
150P_0402_50V8J PR175 7 30
E PR171 COMP PGND E
1.65K_0402_1% 39.2K_0402_1%
10U_1206_25VAK
10U_1206_25VAK
2
1 2 1 2 1 2
10U_1206_25VAK
0.1U_0603_25V7K
1
1
2 1 8 29 3212_DRVL2
5
PR191 5.11K_0402_1% TRDET DRVL2
PC144
PC166
PC167
PC168
PQ43
2
+5VS 9 28 1 PR194 2 3212_CS_PH2 TPCA8030-H_SOP-ADV8-5 @
VARFR SWFB2 1K_0402_1%
3212_VRTT 10 27 3212_SW2 3212_DRVH2 4
VRTT SW2 PL19
2
+3VS
PR187 PR186 TTSense 11 26 3212_DRVH2 0.36UH_SF-I104-R36_23A_20%
0_0402_5% 0_0402_5% TTSNS DRVH2 PC171
PR168
3
2
1
0.1U_0603_25V7K 3212_SW2 4 1
2
12 25 2 1 2 1
1
PR216 GND BST2
3 2
CSCOMP
5
@ 499_0402_1%
CSSUM
SWFB3
CSREF
PWM3
0_0603_5%
1
RAMP
LLINE
PR215 0_0402_5% 49
IREF
RPM
OD3
ILIM
AGND PR631
RT
D D
1
2
1 2 4.7_1206_5%
6 H_PROCHOT# PR190
@
13
14
15
16
17
18
19
20
21
22
23
24
3212_DRVL2 4 3212_DRVL2 4 10_0402_5%
1 2
2N7002W-T/R7_SOT323-3
D
PQ51
162K_0402_1%
1
1
2 3212_VRTT PC633
3212_CSCOMP
3212_CSCOMP
680P_0603_50V7K
3212_CS_PH2
PR53
PR58
3
2
1
3
2
1
2
S 80.6K_0402_1% @
3
Avoid high dV/dt @
CSREF
+5VS 2.05K PQ44 PQ45
2
TPCA8028-H_SOP-ADVANCE8-5
1
TPCA8028-H_SOP-ADVANCE8-5
1
PR174 PR181 PR183
2
PR176 47.5K_0402_1% 649K_0402_1% 2.05K_0402_1% Place PH1 close to
7.32K_0402_1% Connect to input caps PHASE 1 inductor on
2
the same layer
2
C TTSense +CPU_B+ 2 PR169 1 C
1200P_0402_50V7K
1
1K_0402_1%
73.2K_0402_1%
270P_0402_50V7K
PC48 1200P
1
390P PH2
PR206
0.01U_0402_50V7K
2
PR193 PC170
PC162
PC164
0_0402_5% 1000P_0402_50V7K 100K +-1% NCP15WF104F03RC 0402
2
PR207
2
165K_0402_1%
2
CSREF 1 2
2
2
PC173 PR180 130K_0603_1%
PH3 1U_0603_16V6K 2 1 3212_CS_PH1
1
100K +-1% NCP15WF104F03RC 0402
2 1 3212_CS_PH2
1
B PR182 130K_0603_1% B
0603 package
@
PR167 100_0402_1% at least
2 1 +CPU_CORE
Shortest the
VCCSense net trace
VCCSENSE 8
VSSSense
VSSSENSE 8
2 1
PR177 100_0402_1%
A @ A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Tuesday, November 17, 2009 Sheet 57 of 61
8 7 6 5 4 3 2 1
5 4 3 2 1
D D
Iocp=RTEIP*ITRIP/RDS(ON)+1/2 I=16.5K*9u/15m+1.64/2= 10.72A
PL20
1 2 B+
FBMA-L11-201209-121LMA50T_0805
10U_1206_25VAK
PQ41
PC151
AON7408L_DFN8-5
PR201
2
300K_0402_5% 4
VDDCI_TON 1 2
PR205 PR195
47K_0402_1% 2.2_0603_5%
1 2 VDDCI_EN BST_VDDCI
1 2 BST_VDDCI-11 2
14,43,48,56 VGA_ON
3
2
1
PC155
1 0.1U_0603_25V7K
PL18
15
14
1
PC75 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
0.1U_0402_16V7K 1 2
VBST
EN_PSV
TP
+VDDCIP
2
4.7_1206_5%
2 13 UG_VDDCI
TON DRVH
PR198
PR200 SW_VDDCI
220U_6.3VM_R15
3 VOUT LL 12
10U_0805_6.3V6M
422_0603_1% 1
+5VALW 1 2 VDDCI_V5FILT 4 11 VDDCI_TRIP
1 2 +5VALW Ipeak=4A
2
V5FILT TRIP
1
+
PC149
PC129
PR199
VDDCI_FB 5 10 16.5K_0402_1%
VFB V5DRV
2
1
C
6 9 LG_VDDCI 4 2 C
PGOOD DRVL
PGND
PC148
GND
1
1U_0603_10V6K PC147
2
680P_0603_50V7K
47P_0402_50V8J PC150
PC114
1 2 4.7U_0805_10V6K
3
2
1
PU11
2
VFB=0.75V TPS51117RGYR_QFN14_3.5x3.5
PQ19
PR192
12.7K_0402_1% AON7702L_DFN8-5
1 2
1
PR239
1
34.8K_0402_1% +3VS
PR245
PR184 25.5K_0402_1%
2
31.6K_0402_1%
2
2
PR242
1
D PR246 10K_0402_1%
2 1 2 VDDC_VID0 14
PQ50 G 10K_0402_1%
1
1
2N7002W-T/R7_SOT323-3 D PR240
S
3
2 1 2
2
PQ48 G 10K_0402_1%
B PR241 2N7002W-T/R7_SOT323-3 S B
2
1
10K_0402_1%
2
PR235
1
2
10K_0402_1%
PC180
1
0.22U_0402_10V4Z
PC163
0.22U_0402_10V4Z
VID1 VID0(GPIO6) VDDC
0 0 1.12V
0 1 1.07V
1 0 1.05V
1 1 0.95V
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
ATI VDDC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Tuesday, November 17, 2009 Sheet 58 of 61
5 4 3 2 1
5 4 3 2 1
B+ @ PJP19
1 2 GFX_B+ GFX_CORE
Freq.=300KHz
2
PAD-OPEN 4x4m
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
UMA@ PR651 Imax=15.40A
@ PC240 0_0603_5% VSS_AXG_SENSE
UMA@ PC237
UMA@ PC238
UMA@ PC239
Ipeak=22.00A
0.22U_0603_25V7K
1
1
0.1U_0402_25V6 UMA@ PR652
UMA@ PC242
2 1 Iocp=24.5A
+5VALW
1 1
2
1_0603_5% LL=7m ohm
2
UMA@ PC241
1U_0603_6.3V6M UMA@ PR653 UMA@ PC243
Cesr=6 mOHM
22.6K_0402_1% 0.22U_0402_6.3V6K
1
1
UMA@ PR654
D GFXVR_IMON D
2 1 ISUM+
5
10_0402_5% UMA@ PC244
1000P_0402_50V7K ISUM-
1 2 BST_GFX 1 2 1 2
VSS_AXG_SENSE
1
UMA@ PR655 UMA@ PC245 UMA@ PQ91
UMA@ PC246 0_0603_5% 0.22U_0603_25V7K 4 SI7686DP-T1-E3_SO8
VCC_AXG_SENSE 330P_0402_50V7K
29
10
11
12
13
14
1 2
9
+VGFX_COREP UMA@ PR656 UMA@ PC247
AGND
RTN
ISUM+
VDD
VIN
IMON
BOOT
ISUM
2 1 330P_0402_50V7K UMA@ PR657 DCR=1.1 mOHM
3
2
1
10_0402_5% 0_0603_5%
7 15 DH_GFX 1 2 DH_GFX1 UMA@ PL25 +VGFX_COREP
VSEN UGATE 0.45UH_PCMB104T-R45MN_25A_20%
6 UMA@ PU25 16 LX_GFX 4 1
FB ISL62881HRZ-T_QFN28_4X4 PHASE
5
6
7
8
5
6
7
8
5 17 3 2
1
COMP VSSP
4 18 DL_GFX UMA@ PQ92 UMA@ PR658 1
1
UMA@ PR659 VW LGATE AO4456_SO8 2.2_1206_5% UMA@
UMA@ PR663 2 1 3 19 UMA@ UMA@ PR660 PR661 + PC248 UMA@
UMA@ PR662 825K_0402_1% UMA@ PC250 RBIAS VCCP PQ93 3.65K_0805_1% 330U_D2E_2VM_R6M
47K_0402_1% 4 4 0_0402_5%
2
8.66K_0402_1% 1000P_0402_50V7K 2 20 UMA@ PR664 AO4456_SO8
PGOOD VID0 2
2 1 1 2 1 2 2 1 1 2 +5VALW
2
147K for CPU 1 21 UMA@ PR665 UMA@ PH4
DPRSLPVR
0_0603_5%
2
UMA@ PC249 CLK_EN# VID1
1 2 1 2
47K for GPU
3
2
1
3
2
1
1
100P_0402_50V8J UMA@ PC251
VR_ON
470P_0603_50V8J 2.61K_0402_1% 10KB_0603_5%_ERTJ1VR103J
VID6
VID5
VID4
VID3
VID2
1
UMA@ PC254 +VGFX_COREP UMA@ PC252
2
22P_0402_50V8J 2.2U_0603_6.3V6K
2 1 2 1 1 2 2 1
28
27
26
25
24
23
22
1 2
UMA@ PR667 Rds=4.5mOHM(typ) UMA@ PR668
1
UMA@ PC253 UMA@ PR666 8.06K_0402_1% 11K_0402_1% Material Note:
150P_0402_50V8J 17.8K_0402_1% Rds=5.6mOHM(max)
Layout Note: 330uF/6 mΩ, number are 3,
@ PR669
C 10K_0402_1% Place near Choke 1 2 PW C
2
UMA@ PC255 1, HW 1, 1 of HW is backup
.1U_0402_16V7K
1 2
2
0_0402_5% 2 UMA@
1 PR670 UMA@ PC256
0_0402_5% UMA@ PR671 GFXVR_VID_0 .1U_0402_16V7K @ PR674
2 1
0_0402_5% UMA@ PR672 GFXVR_VID_1 UMA@ PR673
2 1 100_0402_1%
0_0402_5% UMA@ PR675 GFXVR_VID_2 UMA@ PR677 1.69K_0402_1%
2 1
0_0402_5% UMA@ PR678 GFXVR_VID_3 82.5_0402_1%
2 1
1
0_0402_5% UMA@ PR676 GFXVR_VID_4
2 1 1 2 1 2
0_0402_5% UMA@ PR679 GFXVR_VID_5
2 1
GFXVR_VID_6
2
0_0402_5% 2 UMA@
1 PR680 UMA@ PC257
0_0402_5% UMA@ PR681 GFXVR_EN 0.01U_0402_16V7K @ PC258
2 1
GFXVR_DPRSLPVR
180P 50V J NPO 0402
1
ISUM+
ISUM-
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Tuesday, November 17, 2009 Sheet 59 of 61
5 4 3 2 1
5 4 3 2 1
Page 1 of 2
Version change list (P.I.R. List) for HW
Item Category Modify List Requestor PG# Date Comment Phase
D 1 Change VGA chip from M97 to M96 as sourcer request sourcer 2009/05/6 EVT2 D
2 connect EC RST to PLT_RST Add U37,R564,R560 and connect the BUF_RST1# ice 2009/05/11 EVT2
3 change the footprint of C381~C386 Change from C_D2 to C_D2T power 2009/05/12 EVT2
4 Remove R768 R769 from BOM we do not use the Camer connector(JP14) so remove it. ice_liu 2009/05/19 EVT2
5 3VS leakage issue(0.1V) Remove R535 from BOM TPE 2009/05/19 EVT2
6 Confirm the DDR_VREF schematic TPE 2009/05/19 EVT2
7 Add soft start for +3vs_delay add C201, R343 ice_liu P14 2009/06/09 DVT
8 Add RST# for Cap board add net of ESB_RST# ice_liu P39 2009/06/09 DVT
C 9 Add PCH CMOS clear change J5,J6 to PCH_RST# ice_liu P24 2009/06/09 DVT C
10 Add +1.1VS option power for M96 Add J11 ice_liu 2009/06/09 DVT
11 2009/06/09
change HDMI_DET for ATI suggestion add R770,R771,Q40,Del R287,R285,R286,L38,C480 ice_liu P20 DVT
12 add option R for TPM PP pin add R772 ice_liu P47 2009/06/17 DVT
13 Add option R for PCIE_WAKE#for debug Add R561 ice_liu P35 2009/06/17 DVT
14 add division R for DC/DC MOS gate change R672.R673/R674 to 47K,R344,R345,R346 to 200k ice_liu P48 2009/06/19 DVT
15 Add HAD_BITCLK_AUDIO termination Add R616(33ohm)C735 (33pf) in BOM EMI P44 2009/06/19 DVT
16 Add option R on SUS_STAT# for debug Add R727,R726 ice_liu P47 2009/06/22 DVT
B 17 Add R720,R351,R681,R721,R722,R719,R728,R723,R724,R680,R770,R675, ice_liu P43 B
Add power good schematic D40,Q42,Q44,(need modify to sot23 FP)Q47,Q51,Q48,Q50,u41 2009/06/23 DVT
18 Add PCH_SPI_R termination Add R729, C777 EMI P41 2009/06/23 DVT
19 Add 0.01 uf C for EMI request Add C480 SE068103K80 S CER CAP 0.01UF 25V K X7R 0402 EMI P42 2009/06/24 DVT
20 Add C861 as EC sugesstion add C861 in to BOM EC P39 2009/06/25 DVT
21 Add C778 close to U30.2 for EMI Add C788 EMI P42 2009/06/25 DVT
22 Change Crystal C for vendor suggestion change C671 C672 from 15pf to 22 pf Vendor P39 2009/06/25 DVT
23 Board ID Add R547 R547, Board ID is 01 ice_liu P39 2009/06/26 DVT
24 CPU_CORE Remove C377，C365，C366，C367 from BOM and change C381,C382,C383,C384 to SGA00001Q80
power P39 2009/06/27 DVT
25 add discharge in BOM Add R682,R683,R684,R685,R686,Q37,Q34,Q32,Q33,Q36 in BOM ice_liu P8 2009/07/03 DVT
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Friday, November 13, 2009 Sheet 60 of 61
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 2
for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D D
C 8 C
10
11
12
13
14
15
B B
16
17
18
19
20
21
22
A A
23
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MB Schematic
Date: Friday, November 13, 2009 Sheet 61 of 61
5 4 3 2 1
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