ECE-342 Lab 5: BJT Amplifier

This sample report from

Sample Lab Report the 2007 ECE-342 Lab
5 assignment is meant to
serve as a guide for lab
Don Hummels, Someone Else reports for ECE-342 and
ECE-343
September 9, 2011

Abstract
Required Section: Very
The design and test of a common-emitter BJT amplifier is described. The amplifier short description of what is
uses two NPN transistors to form a current-source bias network, and a single 2N2222A in this report. Enough in-
NPN transistor as the common-emitter amplifier. The amplifier requires +10 V and formation so that a reader
−5 V supplies, and achieved a measured 46.5 dB gain with 7.8 kΩ input impedance at can assess whether this re-
1 kHz, and 1.2 MHz 3-dB Bandwidth. Component selection and test procedures are port is one that they should
described. check out.

1
Contents
1 Introduction 3

2 Circuit Development and Analysis 3

2.1 CE Amplifier: Selection of RL and IC3 . . . . . . . . . . . . . . . . . . . . 4
2.2 Design of the Current Source: Selection of R1 . . . . . . . . . . . . . . . . 4
2.3 Low-Frequency Performance: Selection of C . . . . . . . . . . . . . . . . 5

3 Simulated Performance 6

4 Experimental Implementation 7
4.1 Generation of the input signal . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Measurement of the output signal . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Discussion 9

6 Conclusion 11

A Lab 5 Assignment 12

B Time Management and Documentation 13

C General Notes for ECE-342/3 Lab Reports 14

2
 +10 v

IC3 RL
vout Design Requirements:
vin
Q3 Amplifier Gain: 46 dB
IR
i in 1 kΩ ≤ RL ≤ 10 kΩ
R1 IC2 47.1 µF ≤ C ≤ 100 µF

Q1 Q2 C

−5 v

Figure 1: Circuit schematic for the common-emitter BJT amplifier.

1 Introduction
Required Section: Give an
This report describes the design, implementation and test of a common-emitter amplifier overview of the lab, and a
using 2N2222A NPN BJT transistors.1 A two-transistor current source is used to provide short outline of the report
the required bias current for the single-transistor common-emitter amplifier. The amplifier that will follow. Generally
requires +10 V and −5 V supplies, and is designed to achieve a nominal “mid-band” gain avoid equations. (Leave
the details to later sec-
of 46 dB. Specific Lab 5 requirements are summarized in the Lab 5 Assignment sheet,
tions.) Do give a pre-
included as Appendix A. The amplifier was constructed using a solderless breadboard, and view of the results. Your
lab measurements verify that the amplifier achieved a peak gain of 46.5 dB at 5 kHz, with report should stand on its
3-dB band ranging from 73 Hz to 1.2 MHz. own. Do not assume that
Section 2 describes the development of the amplifier, including the selection of com- the reader has assignment
sheet.
ponents and the prediction of the lower cutoff frequency. Circuit simulation results are
presented in Section 3, and experimental measurements and procedures are presented in
Section 4. Section 5 gives a summary and comparison of the simulated and measured
results, and addresses specific questions associated with the lab assignment.

2 Circuit Development and Analysis

A schematic of the amplifier is shown in Figure 1. In the schematic, resistor R1 and tran- Most of your labs will in-
clude some design choices,
sistors Q1 and Q2 form a current source used to determine the bias current IC3 . Q3 and RL so a section similar to this
form the common-emitter amplifier, and the capacitor C is used to essentially ground the should be included in the
emitter of Q3 as the signal frequency increases. report.
The circuit design proceeds as follows: First, the required bias current IC3 and resistor
value RL are determined by assuming that the capacitor acts as a short at signal frequencies.
Second, the current source components are determined to provide the required bias current
IC3 . Finally, the effect of the capacitor C is examined by including its finite impedance
in the small-signal analysis. These design steps are presented in Sections 2.1, 2.2, and 2.3
respectively.
1
The Lab 5 assignment actually specified 2N3904 NPN transistors. The 2N2222A device was substituted
for this lab because the 2N3904 devices were out of stock.

3
2.1 CE Amplifier: Selection of RL and IC3
Figure 2 shows the common-emitter amplifier with an ideal current source replacing the
bias network of the original schematic. The corresponding small-signal model of the circuit
is also shown. The model is based on an assumptions that the capacitor impedance is small
at the input signal frequencies (and may be considered a short), and the transistor output
resistance ro is large compared to RL , and may be neglected. The small signal parameters
are
IC3
gm = (1)
VT
rπ = β/gm , (2)

where VT ≈ 25.8 mV is the thermal voltage, and β is the current gain of Q3 . Circuit
analysis of the small signal model yields the amplifier gain
vout
Avo = = −gm RL . (3)
vin
To achieve the desired gain of 46 dB, set gm RL = 200. Substituting (1) into this gives the
required relationship between RL and the bias current IC3 :
200VT 5.16
IC3 = ≈ (4)
RL RL
There are many valid choices for RL and IC3 . This report describes the minimum power
choice, in which the value of RL is made to be as large as possible.

RL = 10 kΩ IC3 = 0.516 mA (5)

Regardless of the selection of RL , setting IC3 = 5.16/RL implies that the DC drop
across RL will be 5.16 V. So the DC component of vOU T will be Vout = 10−5.16 = 4.84 V.
The selection of RL does not change the output dynamic range.
The input resistance of the amplifier is

Rin = rπ = β/gm = β(RL /200). (6)

Selecting a large value of RL has increased the input resistance. The actual value is difficult
to predict, since the 2N2222A transistor only specifies β > 50 (at Ic = 1 mA). Using
RL = 10 kΩ gives
Rin ≥ 2.5 kΩ (7)

2.2 Design of the Current Source: Selection of R1

Referring back to Figure 1, the value of R1 is determined to provide the desired value of
IC3 = 0.516 mA. Since the actual value of β cannot be anticipated, the design here is based
on a large-β approximation. All base currents are assumed to be negligible. In this case,
the design goal is
IC2 = IC3 = 0.516 mA. (8)

4
 +10 v

IC3 RL B C vout
vin
vout
v be rπ g mv be RL
vin Q3

IC2 C

Figure 2: The common-emitter amplifier with bias network replaced by an ideal current
source, and the corresponding small-signal model.

B C vout
vin

v be rπ g mv be RL

v be E
rπ
1
Cs

Figure 3: The small-signal model of the amplifier including the capacitor impedance.

The base-emitter voltages of Q1 and Q2 are tied together. If the transistors are matched
to each other, the currents IC2 and IR must also agree. The resistor R1 determines IR , and
the transistor Q2 reproduces this current as IC2 = IR .
If Q1 and Q2 are both forward active,

vBEQ1 = vBEQ2 ≈ 0.7 V. (9)

The voltage drop across R1 is approximately 4.3 V, so R1 is determined by

4.3 V
IR = 0.516 mA = (10)
R1

R1 = 8.33 kΩ. (11)

2.3 Low-Frequency Performance: Selection of C

The low-frequency behavior of the amplifier is predicted by including the impedance of
the capacitor in the small-signal analysis. The resulting small-signal model is shown in
Figure 3.
The transfer function of the amplifier is determined by observing that the input current
is given by vbe /rπ . vin and vbe are related by adding the voltages across rπ and across the

5
capacitor.
1
vin = vbe + (vbe /rπ + gm vbe ) (12)
Cs
Solving for vbe gives
   
1 1
vbe = vin ≈ vin . (13)
1 + gm /Cs + 1/(rπ Cs) 1 + gm /Cs
The approximation is justified by rπ = β/gm , so the third term of the denominator is a
factor of β smaller than the second term. The output voltage is then
−gm RL
 
vout = −gm RL vbe = vin . (14)
1 + gm /Cs
The system transfer function is a high pass characteristic
 
vout s
= (−gm RL ) . (15)
vin s + gm /C
The capacitor C determines the lower 3-dB cutoff frequency ω3 = gm /C. For this lab, the
lower band edge was not specified, and a value of C = 47.1 µF was selected based upon
available components. Using IC3 from (5) gives
0.516 mA
gm = = 0.02 Ω−1 (16)
25.8 mV
0.02 Ω−1
ω3 = = 424 rad/s (17)
47.1 µF
f3 = ω3 /(2π) = 67.6 Hz. (18)

3 Simulated Performance
Clearly distinguish
Circuit simulations were performed using the Micro-Cap circuit simulator. Simulations between simulated an
using the component values derived in Section 2 (RL = 10 kΩ, R1 = 8.33 kΩ, C = measured results. One
47.1 µF) showed an amplifier gain of 45.7 dB, 0.3 dB lower than the desired gain of 46 dB. way to accomplish this
This 3% error in vout /vin is in part a result of neglecting the transistor output impedance ro is to separate the results
into two sections, as in
in Section 2. For the collector current of 0.516 mA, the ro of transistor Q3 is approximately
this report. In any case,
200 kΩ (based upon VA = 100 V taken from the SPICE model for the 2N2222). Including the grader should never
this value in the small-signal analysis gives a 5% reduction in the calculated gain. Also, the wonder whether a result
approximate 0.7 V base emitter voltage of Q1 was slightly high relative to the simulation, comes from a simulation,
causing the gain to be underestimated by approximately 2%. or a lab measurement.
The gain of the circuit can be increased by increasing RL (not allowed in this lab beyond
10 kΩ), or by decreasing R1 . By decreasing R1 , the bias currents are increased, and the
transconductance gm of Q3 increases. Trial and error indicated that using R1 = 8.0 kΩ
results in a gain of 46 dB.
Based on the simulation results, hardware components were selected with values close
to the desired values of R1 = 8 kΩ, RL = 10 kΩ, and C = 47.1 µF. The actual component
values for the implementation are listed in Table 1. The corresponding simulated gain
and 3-dB corner frequencies are also indicated in the table. More detailed plots of the
simulated performance are given in Section 4, where the simulated curves (using these
measured component values) are presented with the hardware measurements.

6
Table 1: Measured component values used in the hardware implementation, and the corre-
sponding (simulated) amplifier gain, 3-dB corner frequencies, and input impedance.

R1 = 7.915 kΩ RL = 9.996 kΩ C = 47.1 µF

peak gain (at 8.28 kHz) = 46.06 dB
Lower 3-dB corner frequency = 70.1 Hz
Upper 3-dB corner frequency = 719.7 kHz
Input Impedance |vin /iin | = 4.6 kΩ at 1 kHz

All Transistors: 2N2222

Amplifier +10 v Output
Buffer
RL
9.996k +10 v
vout
vin
Q3 vout
R1 i in
vout2 Scope Probe
7.915k
(13 pF)
9.993k
Q1 Q2 C
47.1u
−5 v
−5 v

Figure 4: Final schematic diagram of the amplifier showing measured component values.

4 Experimental Implementation
Figure 4 shows the final schematic of the amplifier indicating the measured values of all Required Section: Show
your final schematic with
components. all component values, and
The capacitor “C” was actually implemented as two capacitors in parallel: a 47 µF tell about how you made
electrolytic capacitor, and a 0.1 µF ceramic capacitor. The ceramic capacitor was included the measurements. Present
to improve the performance of the system at high frequencies, where the electrolytic capac- the results of the measure-
itor fails. Additional circuitry used to create the input signal vin and to measure the output ments
signal vout are discussed in Sections 4.1 and 4.2 respectively.

4.1 Generation of the input signal

An Agilent 33120A function generator was used to provide the amplifier input signal for
test. The generator has a 50 Ω output impedance, and can produce a sinusoidal output
at amplitudes down to 50 mV peak-to-peak to a matched load (50 mV peak to a high
impedance load). To test this amplifier with 46 dB of gain, much smaller input signals are
required. A resistor voltage divider was used to produce a low-level signal at at a much
lower output impedance. Resistors with nominal values of 150 Ω and 1 Ω were used to
give an output amplitude which was ≈ 1/200th of the function generator setting with an
output impedance of approximately 1 Ω. Figure 5 gives the schematic showing the actual

7
 Input Signal Source
Function
Generator
Thevenin
Equivalent
1.033 vin
50 152.8 To Amplifier
(Rin )
vin
1.038 V
V 1.038 203.838

Figure 5: Generation of small input signals using a resistor voltage divider. The actual
schematic with measured component values is shown on the left, and the Thevenin equiva-
lent of the network is on the right.

resistor values used. For all tests, the function generator amplitude was set to provide a
5 mV peak-to-peak sinusoidal input (vin ) to the amplifier.
Simulations predict that the amplifier input impedance will remain above 80 Ω over the
entire range of test frequencies. Since the source impedance for this input configuration
is low (≈ 1 Ω), the amplifier input amplitude should remain at a nearly constant level as
the input frequency is adjusted. For test, the amplifier input level was verified at 1 kHz
using an oscilloscope, and the scope was disconnected from the input at high frequencies.
This ensures that the amplifier would not be effected by the capacitive loading of the scope
probe.

4.2 Measurement of the output signal

An HP 54603B oscilloscope was used to measure output signal levels. However, the scope
input presents a capacitive load to the circuit of approximately 13 pF. Including this load
in the simulation significantly changed the bandwidth of the amplifier. (Without the scope
probes, the simulated upper 3-dB frequency of the amplifier was 720 kHz. With the probe
connected directly to the output, the upper 3-dB bandwidth dropped to 468 kHz.)
To avoid problems associated with loading the amplifier with the scope probe, an
emitter-follower was used to buffer the output signal to the oscilloscope. Figure 4 shows
the schematic of the output signal buffer. Simulations were used to verify that probing the
buffer output vout2 did not significantly change the amplifier performance, and that signal
gains calculated based on vout2 were virtually indistinguishable from those calculated from
vout .

4.3 Measurement results

Figure 6 shows a plot of the amplifier gain for frequencies ranging from 10 Hz to 10 MHz.
Hardware measurements are indicated by the plot symbols, while the plotted curve shows
the results of the Micro-Cap simulation. Measured results are all for a 5 mV peak-to-peak

8
 50

45

40
Gain (dB)

35

30

25

20 1 2 3 4 5 6 7
10 10 10 10 10 10 10
Frequency (Hz)

Figure 6: Amplifier gain. The solid curve shows the results of the Micro-Cap simulation,
while the plot symbols indicate measured data.

input signal (vin ). At each frequency, the peak-to-peak amplitude of vout2 was measured
using the oscilloscope, and used to calculate the gain.
Figure 7 shows a plot of the amplifier input impedance over the same band of fre-
quencies. Again, the measurements are indicated by plot symbols, while the plotted curve
represents the results of the simulation. To measure the input impedance of the amplifier,
a 10 kΩ resistor was inserted between the signal source and the amplifier input. The peak-
to-peak amplitude of vout2 was then measured (V10k ), and compared to the value obtained
without the 10 kΩ resistor (V0 ). The attenuation indicates the signal loss at the amplifier
input. If Rin is the amplifier input, then
V10k Rin
= . (19)
V0 R + 10 kΩ
 in 
V10k /V0
Rin = (10 kΩ). (20)
1 − V10k /V0

5 Discussion
Required Section: Discuss
In general, the experimental results agree reasonably well with the simulation predictions. how your measured results
Table 2 summarizes specific amplifier specifications. agree (or not) with the ex-
The gain of the hardware implementation was 0.5 dB higher than the predicted value pected results.
of 46 dB. This 0.5 dB deviation corresponds to a 6% error in the value of vout /vin . The
error could be caused by mis-matches between transistors Q1 and Q2 (changing the bias
current), or by an imperfect SPICE model for transistor Q3 . The error is larger than would
be expected from measurement error for the test equipment used.

9
 5
10

4
10
Input Impedance Magnitude(Ω)

3
10

2
10

1
10 1 2 3 4 5 6 7
10 10 10 10 10 10 10
Frequency (Hz)

Figure 7: Amplifier input impedance. The solid curve shows the results of the Micro-Cap
simulation, while the plot symbols indicate measured data.

Table 2: Amplifier performance summary, including design goals, simulated performance,

and measured performance.

Design Simulation Measured

Peak Gain: 46.0 dB 46.06 dB 46.5 dB
Lower 3-dB Corner: 70.1 Hz 73 Hz
Upper 3-dB Corner: 719.7 kHz 1.2 MHz
Input Resistance (@ 1 kHz): 4.6 kΩ 7.82 kΩ

10
 While the lower 3-dB frequency of the implementation agreed closely with the simula-
tion result, the upper cutoff frequency of 1.2 MHz was significantly larger than the value
predicted by the simulation. The upper cutoff frequency is determined by the parasitic ca-
pacitance of transistor Q3 . Apparently the values incorporated in SPICE model were larger
that those of the device that was used in the implementation.
Since the amplifier input impedance Rin depends upon the β of Q3 , it is not surprising
that the simulated and measured results differ from each other. Both results (at 1 kHz)
satisfy the prediction of (7), and are reasonable for the transistors used. Some care should
be taken in interpreting Figure 7 at other frequencies. Simulation results show that the
impedance is resistive only for frequencies in the range 300 Hz ≤ f ≤ 3 kHz. At frequen-
cies below or above this band, the amplifier input impedance is primarily capacitive. At
high frequencies in particular, the impedance magnitude is much smaller than that predicted
by (7).

6 Conclusion
Required Section: Wrap
The design and implementation of a 46 dB, 1.2 MHz bandwidth amplifier has been pre- everything up. What was
sented. Hardware tests verified the performance of the amplifier. While the amplifier per- accomplished?
formed largely as predicted, some care is needed in interfacing to the amplifier. The am-
plifier bandwidth is seen to be sensitive to small capacitive loads at the output (e.g. 13 pF
scope probe). Also, the amplifier input impedance varies with frequency over several or-
ders of magnitude. The measured 1.2 MHz bandwidth was achieved only after buffering
the output signal and creating a low-impedance input source.

11
A Lab 5 Assignment
Use appendices for any-
thing that does not fit
into the normal writeup
format. If there are
ECE-342 Fall 2006, Lab 5: BJT amplifier specific questions in the
Due Wed. 12/6, 5:00 PM lab assignment that are
not easily addressed in the
1 Overview normal write-up, then this
The amplifier shown below utilizes a current source from lab 4 to appropriately bias the transistor Q3. In designing is a good place to address
the circuit, assume that the signal vs does not contain any DC offset.
The capacitor C will ultimately determine the low-frequency behavior of the amplifier. It is selected so that at
them.
“typical” signal frequencies, the impedance of the capacitor is small, and the emitter of Q3 is essentially grounded.
The amplifier voltage gain is assumed to be measured at these “mid-band” frequencies (frequencies above those where
the impedance of the capacitor is significant, but below those where the parasitic capacitors of the BJTs become
significant). For this sample report,
the assignment sheet is
+10 v attached here to provide
some frame of reference.
RL IT IS NOT REQUIRED for
your lab reports. (We have
vs vout lots of copies of the lab as-
signment.)
Q3

R1

Q1 Q2 C

−5 v
2 Tasks
Use 2N3904 transistors for Q1 , Q2 , and Q3 .

1. Complete the design of the amplifier to give a voltage gain of 46 dB. Provide the maximum possible output
dynamic range. You should specify all component values, but your selections must meet the constraints:

1 kΩ ≤ RL ≤ 10 kΩ 10 µF ≤ C ≤ 100 µF

Simulate your design, noting the actual (mid-band) gain and dynamic range. Construct and verify the perfor-
mance of the amplifier.
2. Determine the input resistance of your final design. Discuss how your choice of biasing influences the input
resistance.

3. Use a small-signal equivalent circuit to predict the lower cutoff frequency of the amplifier. Verify by simulation
and experimentally.

12
B Time Management and Documentation
Every ECE342 Lab will
include a form similar to
the one shown here, with
signatures indicating that
Time Management and Lab Notebook Documentation
tasks were completed on
ECE342, Fall 2011, Lab 1
time, and lab notebooks
have been reviewed. Turn
Group # Names:
in this (completed) form
with your report.

Please use this form to collect signatures from your assigned TA for each lab as you complete the tasks indicated
below. Signatures must be collected on or before the indicated date. Include this completed form with your lab
notebooks and final lab report.
In unusual circumstances, you may request a If a change in schedule is approved, have the instructor/TA change and
change of one or more of the deadlines listed initial the dates listed below, and sign in this block.
below. This request must be approved either
Monday or Tuesday of the week in which the
lab is assigned.

Tues/Wed, Sep 6,7 Attend the lab briefing and review the deadlines given below. Any modifications must
be approved by Wednesday, 4:00 p.m.
Mon, Sep 12: 4:00 p.m. (10 pts) Circuit design and simulation results completed All designs must be entered
into lab notebooks.
TA’s: Rate from 1 (worst) to 5 (best)...
Clarity of Design Process: 1 2 3 4 5
Lab Notebook Procedures: 1 2 3 4 5
Simulations Completed: 1 2 3 4 5
Clarity of Simulation Results: 1 2 3 4 5
Successful Design Complete: 1 2 3 4 5
Early Check-off: 1 2 3 4 5

Signature: Date:
Fri, Sep 16: 3:30 p.m. (10 pts) Experimental measurements completed and entered into lab notebooks.
Rate from 1 (worst) to 5 (best)...
Experimental Procedures Clearly Described: 12345
Lab Notebook Procedures: 12345
Preliminary Analysis of Results: 12345
Clarity of Results Presentation: 12345
Successful Design Demonstrated: 12345
Early Check-off: 12345

Signature: Date:
Mon, Sep 19: 4:00 p.m. (10 pts) Rough draft of report completed by 4:00 p.m. OR before scheduled demon-
stration (whichever is earlier). Text should be complete, requiring editing primarily for
grammar, consistency, or presentation.

Signature: Date:
As Scheduled (30 pts) Demonstration: Reproduce a measurement from your report for a grader. Ex-
pect to show the grader where the requested measurement and measurement technique was
recorded in your notebook.
Fri, Sep 23: 4:00 p.m. (60 pts) Final Report Due in Room 219, 4:00 p.m. Turn in your final report with this
form. Reports are not accepted late.

13
C General Notes for ECE-342/3 Lab Reports
Checklist
• Typesetting Requirements:
– Use a 12 point font.
– Single space the text.
– Use a 6 inch line length: 0.5 inch left margin, and 2 inch right margin (for
grader comments).
– Number the pages, and include table of contents.
– Figure captions should be placed below the figure. Table captions should be
placed above the tables.
– All Figures/Tables should be discussed within the text of the report. Try to place
the Figures/Tables near the discussion.
• Complete all of the tasks associated with the lab. Is it easy for the grader to find each
task?
• Be concise and clear. Don’t over-explain the theory behind the devices or equations.
Stay on task with the lab assignment.
• Summarize your results! Make sure the reader understands the main points of what
you’ve presented.
• Be technically accurate. If you have questions, ask.
• Clearly distinguish between simulated and experimental results.
• Use good grammar.
• Use good lab technique. Consider the effect of the instrumentation (scope capabili-
ties, function generator output impedance, etc.) on your measurements.
• If your results are not as expected, then follow up if possible. For example, if you
expect that the scope probe changes the performance, then (at least!) include the
probe in a simulation and see if it reproduces your observations.
• Include units on any numerical values. Use symbols instead of spelling out words.
(Use “10 kΩ” instead of “10 kohm”.)
• Use subscripts where appropriate. (Use “R2 ” instead of “R2”).
• Avoid large tables of numerical data. Present a chart or graph of the data instead. If
you need to have a record of the numerical data for some reason, put it in an appendix.
• There’s no need to include data-sheets or other reference information in the report.
• Make your graphs clear. Axes should be labeled, and units should be indicated.
• Make sure that your notation is consistent. Don’t change notation from section to sec-
tion, or between the text and graphs/tables. Be especially careful about graphs/tables
for which axis labels are automatically generated.

14
First Person/Third Person
There will always be exceptions, but unless it’s your diary (or a lab notebook), there will
rarely be a reason to use the first-person presentation in a lab report. In general, stick to the
third-person presentation (unless there really is some reason that you personally should be
the subject of an idea). Instead of “We considered five options:...”, use “Five options are
considered:...”. Think about what the subject of the sentence should be. (In this case, is the
subject “We”, or should it be the “options”?)

Active/Passive Voice
In the active voice, the subject of the sentence is performing the action of the verb. In
contrast, for the passive voice the subject receives the action of the verb. Both are common
in technical writing.
In general, active sentences are shorter and more powerful than passive sentences. They
use stronger verbs, and tend to make written material more engaging (less boring). Given
a choice, use the active voice.
Writers often choose the passive voice deliberately when they want to focus on the
object, or obscure the person performing the action. In technical documents, the passive
voice is often selected as a means of avoiding a first-person presentation.
Consider these three variations:

1. “The data were analyzed to show that...” (Not bad, Third person, but passive)

2. “We analyzed the data to show that...” (Avoid. Active, but first person.)

3. “Data analysis shows that...” (Best. Active, third person.)

Only option 3 really gets the subject (“Data analysis”) correct. It seems that the subject in
option 2 (“We”) is not central to the ideas being presented, and does not really belong.

15