Imperial Journal of Interdisciplinary Research (IJIR)

Vol-3, Issue-7, 2017

ISSN: 2454-1362, http://www.onlinejournal.in

TCAD Simulation Analysis of Tri-Gate

SOI FINFET and Its Application
Isha Padiyar1 & Mr. D.S Gangwar2
1
M.Tech Student, Dept. of VLSI Design, F.O.T, Uttarakhand Technical University,Dehradun.
2
Asst. Prof., Dept. of VLSI Design, F.O.T, Uttarakhand Technical University, Dehradun.

Abstract: This work presents the performance technology scaling new techniques/ methods are
analysis of Tri-Gate (TG) silicon-on-insulator required Some of these are SOI structure, multi-
(SOI) FinFET using TCAD simulation. Various gate transistor, high-k dielectric and metal gate
simulations is performed on the process technology. SOI technology is introduced for the
parameters like Fin width, Fin height and fabrication of advanced MOS structure because of
Underlap to determine the behavior of proposed low supply voltage and minimum power
structure in terms of leakage current, drive current consumption features. Multi-Gate transistor like
and DIBL. Impact of different metal gate work FinFET and Tri-gate FET are used to reduce the
function on drive current and threshold voltage is short channel effects such as DIBL, threshold
analyzed. Also the impact of different spacer voltage roll off, velocity saturation and to get the
material on drain current is analyzed. All the precise control over channel current. Thus FinFET
simulations are done through a 3D numeric is considered as one of the best possible candidates
simulator COGENDA VISUAL TCAD. The results for future generation transistor technologies due to
show for HFin/Lg=0.8 and WFin/Lg=0.6 have its better channel control, improved short channel
higher Ion and lower Ioff and lower DIBL which is effects (SCEs), low leakage current. The tri-gate
more suitable for low power circuit applications. FINFET provides a symmetric device architecture
Resistive load inverter and CMOS inverter using where the channel is controlled by gate from three
simulated Tri-gate FinFET structure is also sides of the Silicon film. Since the gate control is
implemented in this paper. increased, the scaling of Silicon film thickness in
Tri-gate FINFET is better implemented as
Keywords-Tri-Gate, SOI-FinFET, high K compared to DG FINFET and have higher drive
dielectric, short channel effects (SCE), drain current. The structural difference between DG
induced barrier lowering, Process parameters FINFET and Tri-gate FINFET is that in double-
variability. gate FinFET the gate oxide layer is thicker at the
top portion of fin so that only two gate remains
effective for the channel control while in Tri-gate
I INTRODUCTION FinFET the channel is formed at top surface as well
as side surfaces and this will increase the areal
Technology scaling has given us improved circuit density of on-state current. With ease of
performance and reduced cost per function over fabrication, Tri-gate FinFETs have emerged as the
several years. But with the continuous scaling, the dominant structure for future technology. . In Tri-
conventional MOS transistor suffer from various Gate SOI FinFET buried oxide layer provides full
undesirable effects such as gate oxide tunneling, dielectric isolation to active silicon layer from the
increased leakage current and SCEs(Short- main substrate. This allows the selection of
Channel-effects) such as DIBL, sub threshold relatively high resistivity main substrate .And the
leakage, velocity saturation. . In order to reduce off high resistivity main substrate provides significant
state leakage current channel depletion width must reduction in parasitic [6] and leakage current in
reduce with the channel length which results in substrate.
higher doping, that reduces the charge carrier
mobility. The thickness of gate oxide must scale II FINFET DESIGN
along with channel length to maintain proper
threshold voltage, gate control and performance. Table I shows the design considerations of a 3-D n-
Thinner the gate dielectric material higher the gate channel TG-SOI-FinFET with Si3N4 as spacer in
tunneling leakage, which degrades the circuit the underlap regions for simulation. The circuit
performance, noise margin and power. For schematic of a Tri-gate (TG) silicon-on-insulator
reducing these problems and for extending (SOI) FinFET in TCAD software is as shown in the
Fig.1.

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-7, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

TABLE I. TYPICAL CASES OF 3D SOI FINEET FOR SIMULATION

Lg in nm HFin/Lg WFin/Lg Lun/Lg
20 0.25, 0.6, 0.8 0.5 0.25
20 1 0.25, 0.6, 0.8 0.25
20 1 0.5 0.125, 0.2, 0.5

Fig.1: 3D schematic diagram of a tri-gate (TG) silicon-on-insulator (SOI) FinFET

The modeling of Tri-gate FinFET has been done in III. FINFET PERFORMANCE
TCAD.TCAD is a software tool that models
semiconductor fabrications and also semiconductor A. Effect of HFin and WFin
device operation. FinFET has been fabricated on
SOI (silicon on insulator) wafer. The gate length of Fig.2 and Fig.3 shows the variation in enhancement
the FinFET has been chosen to be 20nm. The work current and off current with respect to the different
function of the gate electrode is 4.5eV. fin height and fin width for Vds=0.7V and gate
Source/Drain length (LS/LD) is 40 nm. The source voltage vary from 0V to1V. From both the figures,
and drain doping is uniform with ND at a density as the height and thickness of the fin increases both
of 10^20 cm-3 and channel is lightly doped 10^15 the on current and off current increases. Ion
cm-3) which maximizes the effective mobility and increases because of the increased channel
hence on current density from the source [10]. The inversion area with the fin height and fin width. Off
Equivalent Oxide Thickness (EOT) is 0.9 nm current increases with the increasing fin height and
[4][5][10] and supply voltage VDD = 0.7 V. The fin width because of the reduction in gate
VDD is taken as 0.7V. The work functions of the supremacy on the channel. Also with rise in fin
metal gates are adjusted to achieve the desired height parasitic resistance decreases. Sub-threshold
threshold voltage value. leakage current furthermore increases with
increasing fin width because the off state current
occur in center of fin (volume inversion), which is
far away from gate. But with decreasing fin width,
center part of the fin getting more grips from gate,
that’s why off state current reduced. There is
always a trade-off between Ion and Ioff for device
design. So, the device engineers can choose the
optimum parameter dimensions as per their
requirement.

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-7, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

(a)

(b)
Fig.2: Drain current (ID) variability of process parameter (a) HFin (b) WFin in linear as a function of gate to source
voltage (VGS).

(a)

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-7, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

(b)
Fig.3: Ioff variability of process parameter (a) HFin (b) WFin

Table II: Extracted values of Ion/Ioff and DIBL for different HFin/Lg ratio
Parameters Hfin/Lg=0.25 Hfin/Lg=0.6 Hfin/Lg=0.8 Hfin/Lg=1
Hfin=5nm Hfin=12nm Hfin=16nm Hfin=20nm
Ion/Ioff 1.885*10^5 6.866*10^4 5.350*10^4 4.5969*10^4
DIBL 21mv/v 42mv/v 21mv/v 42mv/v

Table III: Extracted values of Ion/Ioff and DIBL for different WFin/Lg ratio

Parameters Wfin/Lg=0.25 Wfin/Lg=0.6 Wfin/Lg=0.8 Wfin/Lg=1

Wfin=5nm Wfin=10nm Wfin=12nm Wfin=16nm
Ion/Ioff 2.8902*10^5 6.866*10^4 1.9439*10^5 3.3992*10^3
DIBL Less<1mv/v 42mv/v 42mv/v 105mv/v

From the above figures and tables, a wider fin width (WFin = 1*Lg) give unacceptable SCEs, whereas a
narrower fin width (WFin = 0.2*Lg) is more difficult to fabricate. By comparing the Ion and Ioff and DIBL for
all HFin/Lg and WFin/Lg cases, we can say that HFin = 0.6*Lg and WFin = 0.6*Lg are the optimum one as
they gives a moderate value for both Ion and Ioff.

B. Effect of Lun height charge carrier faces problems in tunneling

from source to drain. Thus drain influence on the
Fig.4 and Fig.5 shows the variation in DIBL and channel region decreases [9].
off current w.r.t the different underlap length for Also for small increase in underlap there is not
Vds=0.7V and gate voltage vary from 0V to1V. much difference in DIBL but for underlap
From the both figures it is clear that both DIBL and length=10nm there is noticeable reduction in DIBL.
Ioff decreases with the increased underlap length. From the figure, as the Lun/Lg decreases, there is a
Around 60% to gate capacitances contributed due decrement in the device performance due to higher
to fringing electric field emerging from gate values of leakage current. So, from the above
electrode to source and drain region [9]. Gate discussion, one can clear that by increasing the
capacitances reduced due to under lapping but there underlap length, the device performance may be
is an increment in the resistance between source enhanced.
and drain. Now because of the increased barrier

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-7, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

Fig.4: Variation of off state current with respect to underlap length

Fig.5: Variation in DIBL with respect to underlap length

C. Variation in Work function increase in metal gate work-function increases the

corresponding threshold voltage, which in turn
Fig.6 shows the variation of drain current Ids reduces the off-state leakage current and results in
versus gate voltage Vgs characteristics of FinFET the improvement in the device performance.
for different values of gate work-function. From Increased threshold voltage at higher value of work
Fig. 6 and Fig. 7 it is clear that with the increase in function provides reduce Ioff current, but device
gate work function leakage current decreases but at on-current is sacrificed for increased threshold
the same time it will cause increase in the threshold voltage with increase in metal gate work-function
voltage (Vth). It is because of the fact that as the of FinFET structure.

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-7, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

Fig.6: Drain current (ID) of the device in log scale as a function of gate to source voltage (VGS) for different work
function for VDS=0.7V

Fig.7: Variation of threshold voltage with respect to the different work function

D. Variation of Spacer The fringing field increases with use of high-k

dielectric material for spacer. Increased fringing
Ion current is plotted for different k (dielectric field cause the barrier lowering in the underlap
constant) values of spacer at supply voltage regions allows more carriers from the source to
(Vds)=0.7Vand gate voltage vary from 0V TO 1V. enter into the channel region, resulting in higher
From Fig. 8, Ion increases with the increasing K Ion.
(dielectric constant) of the spacer. The proposed
spacer k values are 3.9, 15 and 25. These k values With use of underlap both Ion and Ioff decreases
correspond to the dielectric constants of SiO2, but with use of high-k dielectric spacer in the
Si3N4, Al2O3, and HfO2 respectively. underlap region Ion increases without increasing
Ioff of the device.

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-7, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

Fig.8 Variation of Ion with respect to the different Spacer dielectric constant

E. Comparison of Tri-gate SOI FinFET carriers. The Off current in Tri-Gate transistor is
with other structure less as compared to the planar transistor and
double-gate FinFET. The reason for is that in case
of planar transistor and double gate FinFET the
Fig.9, illustrates the logarithmic value of channel
channel is surrounded by only one and two sides of
current in a Tri- Gate transistor vs. a planar MOS
gate respectively while in case of tri-gate FinFET
transistor and a double-gate FinFET as a function
three sides are responsible for channel formation.
of gate voltage. It is measured at the supply voltage
And this will increase the channel inversion area in
0.7Vand gate voltage vary from 0V to 1V. Work
Tri-gate FinFET. Thus the Tri-gate structure
function of the gate electrode is 4.5ev, source and
provides better gate control on the channel region
drain doping is 10^20cm-3 and channel doping is
as compared to the planar MOSFET transistor and
10^15cm-3. When the gate voltage is at 0 V, lower
double gate FinFET and effectively minimizes the
amount of leakage current flows through the
leakage current.
channel due to the diffusion of minority charge

Fig. 9: Off current in Tri-Gate FinFET and Double-Gate FinFET and Planar MOSFET

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-7, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

IV APPLICATIONS OF TRI-GATE a) Resistive Load Inverter

SOI FINFET The resistive load inverter circuit is shown in
Fig.10 and its D.C characteristic is shown in Fig.11
Tri-gate SOI FinFET structure which is studied The drain terminal of the n-type FinFET is
throughout the paper is used to implement the connected to the supply voltage of 0.85V by a
inverter circuit. The inverter circuit is the one of linear resistance of 100KΩ. The gate terminal of
the most useful and basic circuit in the digital logic the FinFET is connected to the D.C source and
design. It produces an output which is whose value vary from 0V to 1.2V. And the source
complementary to the input signal. of the FinFET is grounded. Here the output voltage
is measure across the voltage probe.

Fig. 10: Circuit of the resistive-load inverter circuit

Fig.11: Voltage transfer characteristic of Resistive load inverter

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-7, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

complementary mode. The circuit topology is

B) CMOS Inverter
complementary push-pull in the sense that for high
Fig.12 and Fig.13 shows the simulated structure of input, the n-type FinFET drives (pulls down) the
CMOS inverter and its D.C. characteristics output node while the p-type FinFET acts as a
respectively The CMOS inverter circuit consists of load, and for low input the p-type FinFET drives
an n-type Tri-gate SOI FinFET transistor and a p- (pulls up) the output node while the n-type FinFET
type Tri-gate SOI FinFET transistor, operating in a acts as the load.

Fig.12: Simulated structure of CMOS inverter

Fig.13: Voltage transfer characteristic of CMOS inverter

V CONCLUSION load inverter and the CMOS inverter are

implemented using Tri-gate SOI FinFET. The
The impact of process parameters variation (like Voltage transfer characteristic of both inverters has
Hfin and Wfin and Lun) and metal gate work been analyzed and discussed .Various parameters
function on Tri-gate FinFET performance which such as threshold voltage, drive current, leakage
are obtained from simulation has been current, DIBL are evaluated for different process
systematically investigated and discussed. Resistive parameters. The result depict that the increase in
metal gate work-function increases the

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-7, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

corresponding threshold voltage, which in turn [8] Bhole, A. Kurude, S. Pawar,“ 3D Tri-Gate
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ISSN: 2454-1362, http://www.onlinejournal.in

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