International Journal of Research in Electronics ISSN : 2348 - 9065 (Online)

and Communication Technology (IJRECT 2016) Vol. 3, Issue 3 July - Sept. 2016 ISSN : 2349 - 3143 (Print)

Logic Design for Single On-Chip Test Clock Generation for N

Clock Domain - Impact on SOC Area and Test Quality
Ramkumar Balasubramanian
Altran Technologies, Bangalore, India

Abstract
This paper proposes a design technique for single On-Chip test Clock (OCC) generation logic to use multiple clock domain, to
reduce significant area overhead of using multiple OCC. It reduces test vector count and increases test quality that is discussed
with ATPG results. The area comparison data reported in this work shows that almost 50% to 70% area overhead reduced by the
proposed OCC than using regular OCC for N clock domains. The proposed design techniques are easy to implement with any kind
of existing OCC structure.

Keywords
DFT-Design For Testability, OCC, SOC-System On Chip, Area Reduction, ATPG (Automatic Test Pattern Generation)

I. Introduction II. Logic Design of OCC Structure for Single Clock

Structural fault testing of digital integrated circuits is a major Domain
tradition in the semiconductor industry. Adding testability The basic OCC design was discussed by M.Beck et al in 2005 with
features in the hardware design, which makes easier to perform ATPG experimental results [12]. Fig.1 shows the regular OCC
manufacturing tests for the designed hardware. Adding the basic structure, which is slightly modified from the M.Beck’s design.
testability feature starts with creating scan chains in the design The behaviour of this OCC is shown in Fig.2 (a) and Fig.2 (b)
to capture the faults [1-2]. The combination of scan test with for transition test and stuck-at test respectively. In many cases,
Automatic test pattern generation (ATPG) for transition and stuck- the OCC is not used for stuck-at test. In this work, the OCC is
at test have been the industry standard for many years [3-5]. designed to support both Transition Fault Test (TFT=1) and stuck-
To perform transition test, OCC is a core logic used in the design to at fault test (TFT=0).
generate launch and capture pulse. There are different algorithms It consists of n-bit shift register, which decides the delay between
like Launch-On-Shift (LOS) and Launch-On-Capture (LOC) scan_en asserts low to launch pulse of transition test (capture
performed using OCC for transition test [6-8]. Modern SOC’s pulse in stuck-at test). During the scan_en high, the clk_out Mux
contain many blocks with multiple clock domains, and to target is connecting scan_clk to the clk_out. When scan_en asserts low,
transition test for each clock domain they requires one OCC per the shift register starts shifting ‘1’ and pll_clk_en makes ‘1’ to
clock domain. This makes additional area overhead in the actual the Clock Gater (CG) to allow single pulse or double pulse from
SOC design. Let’s consider, a SOC contain 20 blocks and each PLL depending on TFT.
block has 5 different clock domains. If the OCC implemented at
each block level, it requires 100 OCC to perform transition test Since the OCC structure is smaller, the area required to implement
excluding top level test for SOC. The area consumption for 100 OCC is manually calculated in terms of number of instances that
OCC is huge in the SOC. This paper proposes an OCC structure are listed in Table 1. The shift-register size determines the delay
which can be used for N different clock domains, which means between each clock domain capture pulse. In this paper, 6-bit
one OCC for multiple clock domains. In the above example (20 shift-register is used for experiments. The total area count of
blocks SOC) with the proposed OCC, there are only 20 OCC’s one OCC is negligible when compare to entire SOC area. The
required to perform transition test by having one OCC per block. actual problem starts, when this negligible area increased to N
So it saves area overhead of 80 OCC’s in the SOC. Clock shaper times, where N is number of clock domain. The next section
is used in many designs to generate test clock for multiple clock illustrates the same OCC structure is slightly modified and used
domains. This paper proposes the design technique for how to for N clock domain to reduce the area overhead of N-OCC’s
use the single OCC structure for multiple clock domains with
shift register
simple modifications. scan_en

Test clock staggering approach reduces the test pattern count which scan_clk Q0 Qn-2 Qn-1
Q3 Qn
Q4
sync_flop
increases the test quality [9-11]. The proposed OCC generates
0
the test clock in staggered manner for transition and stuck-at test,
which are discussed in the upcoming sections.
1
The paper is structured as follows; the next section discusses TFT
the logic design of OCC used for per clock domain and the area pll_clk_en
consumption. Section three addresses implementation details of pll_clk CG 0
PLL
the OCC for N clock domain and area comparison. Three pulse cg_out
clk_out

generation OCC structure is given in section four. The fifth section 1

discusses the transition test and stuck-at test generation with ATPG
results. Finally, the work is concluded in sixth section.
Fig. 1: Regular OCC structure

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ISSN : 2348 - 9065 (Online) International Journal of Research in Electronics
ISSN : 2349 - 3143 (Print) Vol. 3, Issue 3 July - Sept. 2016 and Communication Technology (IJRECT 2016)

shift register
scan_en To counter clk input
scan_clk Q0 Qn-2 Qn-1 Qn

TFT

pll_clk_en
pll_clk1
pll_clk2 4 pll_clk CG
pll_clk3 4 clk_out1
pll_clk4 cg_out 4 clk_out2
clk_out3
clk_out4
2

2
2-bit counter
From shift register Qn output

Fig. 3: Proposed OCC Structure for 4 Clock Domains

scan_en
TFT
pll_clk1
TFT
pll_clk2
TFT
pll_clk3
TFT
pll_clk4
Fig. 2: Regular OCC behaviour - (a) For Transition Test, (b) For TFT
pll_clk_en
Stuck-at Test
cg_out

Table 1 : Area Count for Regular OCC clk_out1

clk_out2
clk_out3
clk_out4 t1 t3 t5 t7

t2 t4 t6 t8

Fig. 4: Proposed OCC behaviour for 4 Clock Domain

The detailed behaviour of the proposed OCC is illustrated in

below steps;
1. When scan_en is high, the clk_out Mux is connecting scan_
clk to clk_out.
2. When scan_en is low, the pll_clk1 is selected by default initial
value of counter (00) and the shift-register starts shifting ‘1’
which is controlled by pll_clk1. For transition test, the launch
pulse for this pll_clk1 comes when the shift-register shifting
III. Logic Design of Proposed OCC Structure for N Clock ‘1’ at Qn-2 bit position and capture pulse comes at Qn-1 bit
Domains position. The delay t1 between scan_en low to the launch
The regular OCC structure is slightly modified in the shift-register pulse is (tQn-2)*pll_clk1 and for capture pulse delay t2 is
by making feedback the output to input. There is additional logic (tQn-1)*pll_clk1; where, tQn-2 is the time delay for shifting
of Counter, multiplexer (Mux) and de-multiplexer (Demux) added ‘1’ from Q0 to Qn-2 bit position at pll_clk1 frequency and
in the design. The proposed OCC structure for 4-clock domain is tQn-1 is (tQn-2)+1.
shown in Fig.3. The behaviour of this OCC is shown in Fig.4 for 3. The Q0 gets inverted value from Qn while scan_en remains
transition test. The output clocks (clk_out1 to clk_out4) are pulsed low, and the shift-register starts shifting its new value ‘0’
in staggered manner between each PLL clock domain (pll_clk1 which is controlled by pll_clk2. The counter increases when
to pll_clk4). the shift-register Qn toggles 0 to 1. For transition test, the
launch pulse for this pll_clk2 comes only again the shift-
register is shifting ‘1’ at Qn-2 bit position and capture pulse
comes when ‘1’ at Qn-1 bit position. The delay between pll_
clk1 capture pulse and pll_clk2 launch pulse is ((tQn+(Qn-
2))*pll_clk2), where, tQn is time delay for shifting ‘0’ to the

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International Journal of Research in Electronics ISSN : 2348 - 9065 (Online)
and Communication Technology (IJRECT 2016) Vol. 3, Issue 3 July - Sept. 2016 ISSN : 2349 - 3143 (Print)

entire shift-register and Qn-2 is time delay for shifting ‘1’ to flops. (For example, In Table.2 excluding last 4 instances)
Qn-2 bit position.  N-1*(2) = Number of 2:1 Mux for pll_clk + 1:2 Demux
4. The behavior of step3 follows for pll_clk3 and pll_clk4. for clk_out
5. Delay timing for all the pll_clk’s in transition test can be  log2N = Number of flops in counter
defined as follows,
 scan_en low to the launch pulse of pll_clk1 (t1) = (tQn- Tabel 3 : Area Comparison between Regular OCC and Proposed
2)*pll_clk1 OCC for 4 to 32 Clock Domains
 scan_en low to the capture pulse of pll_clk1 (t2) = (tQn-
1)*pll_clk1
 pll_clk1 capture pulse to pll_clk2 launch pulse (t3) =
(tQn+(Qn-2))*pll_clk2
 pll_clk1 capture pulse to pll_clk2 capture pulse (t4) =
(tQn+(Qn-1))*pll_clk2
 pll_clk2 capture pulse to pll_clk3 launch pulse (t5) =
(tQn+(Qn-2))*pll_clk3
 pll_clk2 capture pulse to pll_clk3 capture pulse (t6) =
(tQn+(Qn-1))*pll_clk3 450
 pll_clk3 capture pulse to pll_clk4 launch pulse (t7) = 400
(tQn+(Qn-2))*pll_clk4

Area (# Instance)
350
 pll_clk3 capture pulse to pll_clk4 capture pulse (t8) = 300
(tQn+(Qn-1))*pll_clk4 250
6. The capture pulse behavior of the transition test is similar 200
for stuck-at. 150
The area detail of the proposed OCC structure is shown in 100
Table 2. There are 2 Inverters used in the design, where in 50
one at scan_en path and another one at shift-register feedback 0
path. Regular OCC 4 8 16 32
Proposed OCC Number of clock domian
Table 2 : Area Count of Proposed OCC for 4 Clock Domain
Fig. 5: Performance of Proposed OCC than Regular OCC for 4
to 32 Clock Domains

The comparison results are clearly shows that the area of the
proposed OCC structure is reduced 50%, 63%, 69% and 73% than
regular OCC for 4,8,16 and 32 clock domains respectively.

IV. Three Pulse Generation for Transition Test

This paper proposed a design idea of using single OCC for multiple
clock domains. This logic can be modified further as required.
For example, some designs are required more than one launch
pulse in transition test, based on their sequential depth. It can be
done by using a configurable register in the design as shown in
Fig.6. This configurable register is pre-loaded with ‘1’ to select
three pulses for pll_clk3 domain. The behavior of this OCC is
shown in Fig.7.

Area comparison between the regular OCC and proposed OCC

for 4 to 32 clock domain is reported in Table 3. The comparison
graph is shown in Fig.5. An equation derived to determine the
area required for N-clock domain as follows,

Regular OCC = N * 13
Proposed OCC = 14 + ((N-1)*2) + N + log2n

Where,
 N = Number of clock domain
 13= Area of regular OCC for one clock domain
 14= Number of instances in the proposed OCC excluding 2:1
Mux for clk_out, 2:1 Mux for pll_clk, 1:2 Demux and counter

© 2014, IJRECT All Rights Reserved www.ijrect.com

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ISSN : 2348 - 9065 (Online) International Journal of Research in Electronics
ISSN : 2349 - 3143 (Print) Vol. 3, Issue 3 July - Sept. 2016 and Communication Technology (IJRECT 2016)

same capture cycle in staggered manner as shown in Fig.4.

scan_en
shift register Exp3: Stuck-at test - using a regular OCC per clock domain:
To counter clk input
scan_clk Q0 Qn-3 Qn-2 Qn-1 Qn
In regular approach, a common external scan clock used for all
the clock domains for stuck-at test. Since this paper demonstrates
0 OCC for single pulse generation, this exp uses one regular OCC per
0 clock domain capture. This exp is similar to exp1 with TFT=0. 
pll_clk_en
1 Exp4: Stuck-at test - using proposed OCC: 
TFT
1
This exp is similar to exp2 with TFT=0. 
pll_clk1
pll_clk2 4 pll_clk Table 4 : Experimental Results
pll_clk3 0
pll_clk4 4-bit CFG 0
register 1
0
2
CG
4 clk_out1
4 clk_out2
CFG_in cg_out clk_out3
clk_out4
2
scan_en
2-bit counter
From shift register Q4 output scan_clk
The test coverage is same for transition faults using regular and
Fig. 6: Proposed OCC Structure for 4 Clock Domain and 3 capture proposed OCC, but the pattern count is reduced 383 by using
pulse for pll_clk3 the proposed OCC.  For stuck-at test also, the test coverage is
same in both cases and pattern count is reduced 305 with the
scan_en
scan_en proposed OCC. These experimental results are clearly shows that
TFT the proposed OCC is not affecting the actual test coverage and
pll_clk1 saves the pattern count. The aim of these experiments is to show
TFT the proposed OCC is not affecting the actual coverage of using
pll_clk2
TFT
the regular OCC, hence the author is not analyzed the reaming
pll_clk3 untested faults in above experiments. Therefore the proposed
TFT OCC increases the test quality by reducing the pattern count
pll_clk4
TFT and preserving the actual test coverage.
pll_clk_en

cg_out VI. Conclusion

Modern structural testing approaches target each clock domain
clk_out1
faults sequentially (staggered) to avoid more switching power
clk_out2 consumption. Since all the clock domain faults are not targeted
clk_out3 at same time, it is really not required to run multiple OCC’s
clk_out4 in parallel. A simple modification applied in the regular OCC
structure proposed in this paper saves significant area overhead
Fig. 7: Proposed OCC behaviour for 4 Clock Domain and 3 capture of using multiple OCC in the SOC, which is proved in the area
pulse for pll_clk3 comparison results in section 3. This modification can be applied
to any kind of existing OCC structure to use for multiple clock
V. ATPG Experiments for Transition and Stuck-at Test domains. The ATPG result shows that there is no affect on actual
The proposed OCC is designed for 6 clock domain and used in test coverage and saves pattern count with the proposed OCC.
one of the 6 different clock domain netlist to perform transition Therefore the proposed OCC structure is simple and efficient to
& stuck-at test by having different clock frequency for pll_clk1 implement in SOC.
to pll_clk6. The netlist contains ~40,000 scan flops which are
connected in 176 balanced internal scan chains with the maximum References
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International Journal of Research in Electronics ISSN : 2348 - 9065 (Online)
and Communication Technology (IJRECT 2016) Vol. 3, Issue 3 July - Sept. 2016 ISSN : 2349 - 3143 (Print)

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Author Profile
Ramkumar Balasubramanian working in DFT (Design For
Testability) domain in Altran India Technologies, Bangalore,
India. He received Ph.D degree from VIT University, Vellore in
2014. He completed Master of Engineering in VLSI design, 2006
and Bachelor of Engineering in Electronics & Communication,
2004.

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