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AHB vs AXI: Key Differences Explained

The document discusses various concepts related to Advanced High-performance Bus (AHB) and Advanced eXtensible Interface (AXI) protocols such as: 1. AHB uses pipelined architecture and can transfer a maximum of 1K data in a single transfer. It follows the 1K boundary concept. 2. AXI differs from AHB and also uses a 4KB boundary condition. It supports features like out-of-order transactions, multiple outstanding address pending, and data interleaving. 3. Both protocols explain concepts like arbitration, response types, burst transfers, and address boundaries.

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Mayur Khairnar
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242 views2 pages

AHB vs AXI: Key Differences Explained

The document discusses various concepts related to Advanced High-performance Bus (AHB) and Advanced eXtensible Interface (AXI) protocols such as: 1. AHB uses pipelined architecture and can transfer a maximum of 1K data in a single transfer. It follows the 1K boundary concept. 2. AXI differs from AHB and also uses a 4KB boundary condition. It supports features like out-of-order transactions, multiple outstanding address pending, and data interleaving. 3. Both protocols explain concepts like arbitration, response types, burst transfers, and address boundaries.

Uploaded by

Mayur Khairnar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

1. How AHB is pipelined architecture?

2. What is the size of the max data that can be transferred in a single transfer?
3. Explain the 1k boundary concept in AHB?
4. Okay, response is a single cycle? but error/split/retry is two cycles, why?
5. Explain the concept of a two-cycle response?
6. What if the slave gets the address out of range?
7. How to connect multiple slaves to a single master?
8. Explain the round robin arbitration concept?
9. Explain the split-retry concept?
10. What is the difference between HREADY and HREADY_OUT signals?
11. What is the slave response for a BUSY transfer?
12. What is the difference between WRAP4 and INCR4?
13. How to terminate the INCR type transfer?
14. What is the difference between BURST and Beat?
15. How to calculate the size of the burst?
16. Is HREADY is Input or output to/from the slave?
17. What is the aligned and un-align concept?
18. Explain wrapping calculation?
19. Is early burst termination is done by Slave/Arbiter?
20. Explain the LOCKED transfer?
21. What is the default Master?
22. What is a little-endian and big-endian?
23. How the slave will detect the end of INCR type burst transfer?

1. How AXI is different from AHB?


2. Explain the concept of the AXI 4KB boundary condition?
3. Explain the valid ready handshake in AXI?
4. Explain the channel concept?
5. Explain the out-of-order concept?
6. What is the fixed burst type?
7. Explain the AXI response types?

Difference between AHB and AXI?

What is AXI Lite?

Name five special features of AXI?


Why streaming support,it's advantages?

Write an assertion on handshake signals - ready and valid, ready comes after 5 cycles from
the start of valid high?

Explain AXI read transaction

What is the AXI capability of data interleaving?

Explain out-of-order transaction support on AXI?

Explain multiple outstanding address pending?

Any flow control mechanism in AXI?

How to ensure data integrity on AXI?

What is 'last' signal?

What are bursts and transfers?

Maximum size of a transfer?

Write response codes?

What is strobing in AXI?

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