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VLSI M3 Ktunotes - in PDF

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Sangeetha Sumam
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0% found this document useful (0 votes)
221 views76 pages

VLSI M3 Ktunotes - in PDF

Uploaded by

Sangeetha Sumam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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E S .

I N
KTU NOT

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S . I N
T U N OTE
K

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E S . I N
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E S . I N
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E S . I N
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Reference Text Book:

“Basic VLSI Design” S . I N


TE
U N
by O
‘Douglas Pucknell’
KT

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MOS Circuit Design Processes

 The aim of MOS design is to turn a design


specification into masks for N processing the
silicon wafer to meet E S . I
T design specifications
KTU NOthe

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MOS Layers

 MOS circuits are formed on four basic layer


- n-Diffusion
- p-Diffusion
E S . I N
- Polysilicon (Polycrystalline Si)
U N O T
KT
- Metal

 In some processes, there may be a 2nd metal


layer & a 2nd polysilicon layer also

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MOS Layers

 All the layers are isolated from one another by


thick or thin silicon dioxide (thinox) that
insulates these layers

 S
“Polysilicon & thinox interact
E . I N
so that a MOS
U N OT
KT where they cross one another”
transistor is formed

Contact
 Layers may be joined together where contacts
are formed

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STICK Diagrams

 The MOS design processes are aided &


simplified by the stick diagrams

 Stick diagrams are used to convey layer info.


through color codes .IN
OT E S
K T U N
 Examples of color codes are
- Green for n-Diffusion
- Red for Polysilicon
- Blue for metal
- Black for contact areas
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Color Plates for
E S . I N
OT
single metal nMOS
K TUN

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Stick Diagram of nMOS Transistor

S . I N
T U N OTE
K

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Color Plates for double metal
CMOS p-well process

S . I N
T U N OTE
K

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Stick Diagram of pMOS Transistor

S . I N
T U N OTE
K

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Color Plates for double
metal, double poly
S . I N
BiCMOS n-well process
T U N OTE
K

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Stick Diagrams & Layouts

 The stick diagrams directly reflects the


topology of actual mask layout in silicon

 ie. Mask layouts can be easily drawn


N from the
E S . I
stick diagrams
KTU NOT

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Conclusion of Stick Diagrams

 Stick diagrams are used to convey layer


information & topology

 These diagrams can be easily


E S . I N turned into
mask layouts TUN OT
K

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E S . I N
Drawing Stick
T U N Diagrams………
OT
K

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nMOS Design Style

 Only n-MOS transistors will be present in


nMOS design style

 The layout of nMOS involves:


- n-Diffusion (Green) E S . I N
U N O T
T
K -1 or Poly-1 (Red)
- Polysilicon
- Metal-1 (Blue)
- Implant areas (Yellow)
- Contacts (Black or Brown for buried
contacts)

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nMOS Design Style

 In nMOS design style, all diffusion areas are of


n-type only (green)

 A MOS transistor is formed wherever a Poly-


Si crosses n-diffussion E S . I N
U N OT
T
ie. red over green
K

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Drawing nMOS design

 First step is to draw the metal (blue) VDD


& GND rails in parallel allowing enough
space b/w them for other circuit elements

S . I N
 Next, green pathsT U N
are OTE
drawn b/w the metal
K
rails for inverters

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Stick Diagram of „nMOS Inverter‟
 In nMOS inverter circuit, a depletion mode
transistor connected from the output point to
VDD & an enhancement mode transistor
interconnected b/w output point & GND

S . I N
T U N OTE
K
Circuit Diagram

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Stick Diagram of nMOS INVERTER

S . I N
T U N OTE
K
 The implant (yellow) is
for depletion mode
transistors
 L : W is length to width
ratio is also shown

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Circuit Diagram

S . I N
T U N OTE
K

Stick Diagram of nMOS


INVERTER (Monochromatic)
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Circuit Diagram

S . I N
T U N OTE
K

Stick Diagram of
nMOS NAND Gate
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Circuit Diagram

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T U N OTE
K

Stick Diagram of
nMOS NOR Gate
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CMOS Design Style

 CMOS is an extension of nMOS design style

 Here, the implant (yellow square) is not used


.
because no depletion transistor
E S I Nexists
N OT
KTU
 Yellow lines in CMOS design is used to identify
p-transistors

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CMOS Design Style

 In CMOS, two types of MOS transistors are


present

 They are ‘n-MOSFET’ and ‘p-MOSFETs’


.IN
OT E S
K T U N
 n-MOS’ and ‘p-MOS’ are separated in the stick
layout by the demarcation line

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CMOS Design Style

Demarcation Line
 A line used to separate ‘n-MOS’ and ‘p-MOS’
transistors in the stick layout

 S .
Demarcation Line represents
E I N the p-well
U N OT
KT which all p-type devices are
boundary above
placed

 The n-devices (green) are placed below


demarcation line
(n-devices are fabricated in the p-well)
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CMOS Design Style

Demarcation Line Rules


 n-Diffusion line or p-Diffusion must not cross
the demarcation line
 Only Metal & Poly-Si can cross the
demarcation line S.IN
OT E
K TUN
 So when a connection is needed, the n-
diffusion & p-diffusion lines are joined by metal

 Apart from demarcation line, there is no


indication of p-well at this stick diagram
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Drawing Stick Diagrams in CMOS design

 Begins with drawing of VDD and Vss metal


rails in parallel and demarcation line in b/w

 The n-MOS transistors are the N placed below


E S . I
this line & they are N OTto Vss
close
KTU
 p-MOS transistors are placed above the line
and they are below VDD

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Drawing Stick Diagrams in CMOS design

 Both the transistors are placed horizontal in


the diagram

ie. Transistors with their diffusion paths


parallel to VDD & GND S . I
E railsN
T U N OTmetal
K
 Only metal & polysilicon can cross the
demarcation line

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Drawing CMOS layout

 Interconnection of the n-MOS & p-MOS


transistors are done using metal

 Metal rails can run over diffusion


N also
E S . I
K TU NOT
 Finally appropriate interconnections, control
signals & data inputs are added

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Circuit Diagram

S . I N
T U N OTE
K

Stick Diagram of
CMOS INVERTER
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Stick Diagram of CMOS INVERTER

S . I N
T U N OTE
K

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Circuit Diagram

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Stick Diagram of
CMOS Nor Gate
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Stick Diagram of
CMOS NOR gate

S . I N
T U N OTE
K

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Circuit Diagram

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K

Stick Diagram of
CMOS Nand Gate
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