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Sipo VHDL Code

This document contains VHDL code for a serial-in parallel-out (SIPO) shift register and a testbench to test it. The SIPO code defines a 4-bit output port that shifts input bits from sin to each output bit on each clock cycle. The testbench instantiates the SIPO component and applies a stimulus of changing sin input values over multiple clock cycles to shift bits through the output port.

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Manohar thota
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35 views5 pages

Sipo VHDL Code

This document contains VHDL code for a serial-in parallel-out (SIPO) shift register and a testbench to test it. The SIPO code defines a 4-bit output port that shifts input bits from sin to each output bit on each clock cycle. The testbench instantiates the SIPO component and applies a stimulus of changing sin input values over multiple clock cycles to shift bits through the output port.

Uploaded by

Manohar thota
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Sipo vhdl code

library ieee;

use ieee.std_logic_1164.all;

entity sipo is

port( res: in std_logic;

sin: in std_logic;

clk: in std_logic;

pout: out std_logic_vector(3 downto 0));

end sipo;

architecture beh of sipo is

signal temp: std_logic_vector( 3 downto 0);

begin

process( clk, res)

begin

if(res='1') then

temp<="0000";

elsif (clk'event and clk ='1') then

temp(3)<=sin;

temp(2)<=temp(3);

temp(1)<=temp(2);

temp(0)<=temp(1);

end if;

end process;
pout<=temp;

end beh;

sipo testbench coding

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY sr IS

END sr;

ARCHITECTURE behavior OF sr IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT sipo

PORT(

res : IN std_logic;

sin : IN std_logic;

clk : IN std_logic;

pout : OUT std_logic_vector(3 downto 0)

);

END COMPONENT;

--Inputs

signal res : std_logic := '0';


signal sin : std_logic := '0';

signal clk : std_logic := '0';

--Outputs

signal pout : std_logic_vector(3 downto 0);

-- Clock period definitions

constant clk_period : time := 50 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: sipo PORT MAP (

res => res,

sin => sin,

clk => clk,

pout => pout

);

-- Clock process definitions

clk_process :process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;


end process;

-- Stimulus process

stim_proc: process

begin

sin<='0';

wait for 50 ns;

sin<='0';

wait for 50 ns;

sin<='1';

wait for 50 ns;

sin<='1';

wait for 50 ns;

sin<='0';

wait for 50 ns;

sin<='1';

wait for 50 ns;

sin<='0';

wait for 50 ns;

sin<='1';

wait for 50 ns;

sin<='0';

wait for 50 ns;

sin<='1';

wait for 50 ns;


sin<='1';

wait for 50 ns;

sin<='0';

wait for 50 ns;

sin<='0';

wait for 50 ns;

wait;

wait;

end process;

END;

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