Magnetoresistive Random Access Memory

Freescale Semiconductor, Inc.

Introduction bit at the cross point of those two lines. During the read
Magnetoresistive Random Access Memory (MRAM) operation the isolation transistor of the target bit is turned
combines a magnetic device with standard silicon-based on to bias the MTJ and the resulting current is compared to
microelectronics to obtain the combined attributes of non- a reference to determine if the resistance state is low are
volatility, high-speed operation and unlimited read and high.
write endurance not found in any other existing memory
technology. In this paper we provide an overview of Write Line 1
Freescale’s MRAM technology and describe the
MR2A16A, a 4 Mbit MRAM device. As shown in Figure i
1, the memory is based on a 1-transistor, 1-magnetic tunnel isense
junction (1T1MTJ) memory cell that employs a novel bit
structure and approach for operation. The MR2A16A is MTJ
fabricated with a 0.18µm CMOS process using five levels
of metal, including program current lines clad with highly
permeable material for magnetic flux concentration. We i
describe how the cell architecture, bit structure, and the Write Line 2
ON for sense
toggle switching mode are combined to provide
OFF for
significantly improved operational performance and
program
manufacturability as compared to MRAM based on
conventional switching. iref
MRAM Description
MRAM is based on magnetic memory elements Figure 1. Schematic of a 1-transistor, 1-MTJ memory cell
integrated with CMOS. Each memory element uses a showing the write lines above and below the bit and the
magnetic tunnel junction (MTJ) device for data storage. read current path.
The MTJ is composed of a fixed magnetic layer, a thin
dielectric tunnel barrier, and a free magnetic layer. When
a bias is applied to the MTJ, electrons that are spin
polarized by the magnetic layers traverse the dielectric
D1 D2 D3
barrier through a process known as tunneling. The MTJ B1
device has a low resistance when the magnetic moment of
the free layer is parallel to the fixed layer and a high B2
resistance when the free layer moment is oriented anti-
parallel to the fixed layer moment. This change in
resistance with the magnetic state of the device is an effect
known as magnetoresistance, hence the name
“Magnetoresistive” RAM.
Unlike most other semiconductor memory
technologies, the data is stored as a magnetic state, rather
W1 W2 W3
than charge, and sensed by measuring the resistance
without disturbing the magnetic state. Using a magnetic Figure 2. A memory array consisting of many MRAM
state for storage has two main benefits: 1) the magnetic cells with digit and bit lines for cross-point writing and
polarization does not leak away with time like charge does, isolation transistors controlled by word lines.
so the information is stored even when the power is turned
off; and 2) switching the magnetic polarization between Toggle MRAM
the two states does not involve actual movement of Freescale’s Toggle approach to bit programming
electrons or atoms and thus has no known wear-out effectively eliminates the single-line disturb phenomenon
mechanism. The magnetoresistive device used in MRAM present in previous approaches to MRAM switching.
is very similar to the device used for the reader in hard Through the use of a new free layer structure, bit
disk drives. orientation and current pulse sequence, the MRAM bit
To make a high-density memory, the MRAM cells state can be programmed via a "Toggle" mode we have
shown in Figure 1 are arranged in a matrix with each write named "Savtchenko switching" after its late inventor.
line spanning hundreds or thousands of bits as shown in “Toggle” means that the exact same pulse sequence is used
Figure 2. During the write operation, current pulses are to write from the “0” state to the “1” state and for “1” to
passed through a digit line and a bit line, writing only the
Freescale Semiconductor, Inc. Revised June 23, 2006
“0;” each time the sequence is executed the device changes
from its current magnetic state to the opposite state. This
type of switching is significantly different from the simple
H2
H1 + H2
type of switching where the magnetic moment of the free
layer simply follows the applied field. Because the
switching mode is fundamentally different, the selectivity
using this mode is greatly enhanced as described below. H1
Savtchenko switching relies on the unique behavior of
a synthetic antiferromagnet (SAF) free layer that is formed
from two ferromagnetic layers separated by a non-
magnetic coupling spacer layer. This is shown
schematically in Figure 3. The moment-balanced SAF i1,
free-layer responds to an applied magnetic field differently Write
than the single ferromagnetic layer of conventional Line 1
MRAM. Rather than following an applied magnetic field,
the two antiparallel layer magnetizations will rotate to be
approximately orthogonal to the applied field. A current
pulse sequence is used to generate a rotating magnetic field
that moves the free-layer moments through the 180-degree i2,
switch from one state to the other, as shown in Figure 4. Write
Line 2
Top electrode
Figure 4. Schematic of a toggle MRAM bit with the field
Free sequence used to switch the free layer from one state to the
SAF Ru other. The fields, H1, H1+H2, and H2, are produced by
Sense layer passing currents, i1 and i2, through the write lines.

AlOx Tunnel barrier

Reference
Fixed layer
Ru H1
SAF Write
Pulses
Pinning H2

Base electrode Figure 5. The current pulse sequence used to produce the
sequence of magnetic fields used for toggle switching.

Figure 3. The magnetic tunnel junction (MTJ) material

stack used for Toggle MRAM. The Free SAF magnetic Figure 6 is a switching characteristic map versus
moments switch between two states when the proper current for an entire 4-Mbit memory. In the region below
magnetic field sequence is applied. Electrons tunnel the switching threshold, no bits changed state and hence
across the alumina (AlOx) tunnel barrier, resulting in a there were no disturbs from half selects. A large operating
magnetoresistance that is sensitive to the magnetic moment region is observed above the threshold consistent with the
direction of the sense layer. single bit characteristic presented above. The contours in
the transition region just at the threshold are a measure of
the bit-to-bit switching distribution. Note that there are no
To exploit the unique field response of this free layer, disturbs all the way up to the highest currents, displaying
a two-phase programming pulse sequence, shown in the remarkable resistance to single-line disturbs with this
Figure 5, is applied to effectively rotate the magnetic approach.
moments of the SAF by 180 degrees. Because of the
inherent symmetry, this sequence toggles the bit to the
opposite state regardless of existing state. A pre-read is
therefore used to determine if a write is required. Because
of the way a SAF responds to applied fields, a single line
alone cannot switch the bit, providing greatly enhanced
selectivity over the previous approaches to MRAM
switching.

Freescale Semiconductor, Inc. Revised June 23, 2006

 memory circuit such as a processor or controller. For
example, a processor may need to have some fast memory
and some non-volatile memory on board; MRAM could
provide both capabilities. Because the MRAM module is
Operating independent of the front-end CMOS, the MRAM
region capability can be added without perturbing the CMOS
logic process. This approach may provide cost and
performance advantages in many system-on-chip
i2 (H2)

applications.

Comparison to Other Memory Technologies

Comparison of MRAM with other memory
0% switching region technologies suggests that it can be competitive in overall
(no disturbs) performance. Since MRAM is nonvolatile, it retains the
data when completely turned off. System power can be
i1 (H1) significantly reduced compared to DRAM by shutting
down the MRAM when inactive since there is no
background refreshing required. The straightforward
Figure 6. Measured toggling characteristic map of an entire integration scheme used for MRAM makes it easier to
4-Mbit die showing the large operating region. embed.
Comparison with SRAM shows that MRAM will
Integration of Magnetic Devices with CMOS compete favorably in cost because of its smaller cell size.
A schematic cross-sectional view of our integrated It also is non-volatile, which is only available in more
MRAM cell for a 1T1MTJ cell architecture is shown in complex and expensive battery backup solutions for
Figure 7. In this case, the MRAM process module is SRAM.
integrated between the last two layers of metal in an When compared with Flash, MRAM achieves much
otherwise standard semiconductor process flow. The better performance in write characteristics since no high-
MRAM module is termed a "back-end" module because it voltage tunneling mode is required and MRAM write cycle
is inserted after all of the associated CMOS circuitry is is much faster. MRAM consumes much less energy in a
fabricated. This integration scheme requires no alteration write cycle because the energy/bit is several orders of
to the front-end CMOS process flow. This back-end magnitude lower than Flash. In addition, MRAM
approach separates the specialized magnetic materials endurance is unlimited, with no known or expected
processing from the standard CMOS process. deterioration mechanism, while typical Flash endurance is
only 105 write cycles.

Single MRAM Bit Cell

MTJ

M5: “Bit”Line with cladding M5

Back-end Contact
MRAM Via M4 Line M4 Line Via
to MTJ
M4 M4
module Stud Stud
Via Via Metal 4
M3 “Digit” Line with M3
Front-end contact stud
cladding
CMOS Via Via in via stack
M2 M2
module
Via Word Via Transistor
Line Common
M1 M1 M1

CNT CNT CNT

N+ N+ N+
Drain Shared Source Drain P-
Silicon Substrate

Figure 7. A schematic cross-sectional view of our

integrated MRAM cell for a 1T1MTJ cell architecture.
The MRAM module is inserted after the front-end CMOS Figure 8. Micrograph of the MR2A16A MRAM device.
(above the horizontal red line).

This integration scheme lends itself to embedded

applications, where the memory core is part of a non-

Freescale Semiconductor, Inc. Revised June 23, 2006