Features

• Compatible with MCS-51® Products

• 8K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 1000 Write/Erase Cycles
• 2.7V to 4.0V Operating Range
• Fully Static Operation: 0 Hz to 16 MHz
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
•
•
Eight Interrupt Sources
Full Duplex UART Serial Channel
8-bit
•
•
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Low-Voltage
• Watchdog Timer
• Dual Data Pointer Microcontroller
• Power-off Flag
• Flexible ISP Programming (Byte and Page Modes) with 8K Bytes
Description
In-System
The AT89LS52 is a low-voltage, high-performance CMOS 8-bit microcontroller with 8K Programmable
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus- Flash
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a
monolithic chip, the Atmel AT89LS52 is a powerful microcontroller which provides a
AT89LS52
highly-flexible and cost-effective solution to many embedded control applications.
The AT89LS52 provides the following standard features: 8K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a Preliminary
six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89LS52 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.

Rev. 2601A–12/01

1
Pin Configurations

PDIP
PLCC
(T2) P1.0 1 40 VCC

P1.1 (T2 EX)

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
(T2 EX) P1.1 2 39 P0.0 (AD0)

P1.0 (T2)
P1.2 3 38 P0.1 (AD1)

VCC
P1.4
P1.3
P1.2

NC
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)

6
5
4
3
2
1
44
43
42
41
40
(MOSI) P1.5 6 35 P0.4 (AD4) (MOSI) P1.5 7 39 P0.4 (AD4)
(MISO) P1.6 7 34 P0.5 (AD5) (MISO) P1.6 8 38 P0.5 (AD5)
(SCK) P1.7 8 33 P0.6 (AD6) (SCK) P1.7 9 37 P0.6 (AD6)
RST 9 32 P0.7 (AD7) RST 10 36 P0.7 (AD7)
(RXD) P3.0 10 31 EA/VPP (RXD) P3.0 11 35 EA/VPP
(TXD) P3.1 11 30 ALE/PROG NC 12 34 NC
(INT0) P3.2 12 29 PSEN (TXD) P3.1 13 33 ALE/PROG
(INT1) P3.3 13 28 P2.7 (A15) (INT0) P3.2 14 32 PSEN
(T0) P3.4 14 27 P2.6 (A14) (INT1) P3.3 15 31 P2.7 (A15)
(T1) P3.5 15 26 P2.5 (A13) (T0) P3.4 16 30 P2.6 (A14)

(WR) P3.6 16 25 P2.4 (A12) (T1) P3.5 17 29 P2.5 (A13)

18
19
20
21
22
23
24
25
26
27
28
(RD) P3.7 17 24 P2.3 (A11)

(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)

TQFP
P1.1 (T2 EX)

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P1.0 (T2)

VCC
P1.4
P1.3
P1.2

NC
44
43
42
41
40
39
38
37
36
35
34

(MOSI) P1.5 1 33 P0.4 (AD4)

(MISO) P1.6 2 32 P0.5 (AD5)
(SCK) P1.7 3 31 P0.6 (AD6)
RST 4 30 P0.7 (AD7)
(RXD) P3.0 5 29 EA/VPP
NC 6 28 NC
(TXD) P3.1 7 27 ALE/PROG
(INT0) P3.2 8 26 PSEN
(INT1) P3.3 9 25 P2.7 (A15)
(T0) P3.4 10 24 P2.6 (A14)
(T1) P3.5 11 23 P2.5 (A13)
12
13
14
15
16
17
18
19
20
21
22
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4

2 AT89LS52
2601A–12/01
 AT89LS52

Block Diagram
P0.0 - P0.7 P2.0 - P2.7

VCC
PORT 0 DRIVERS PORT 2 DRIVERS

GND

RAM ADDR. PORT 0 PORT 2

REGISTER RAM LATCH LATCH FLASH

PROGRAM
B STACK ADDRESS
REGISTER ACC POINTER REGISTER

BUFFER
TMP2 TMP1

PC
ALU INCREMENTER

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PROGRAM
PSW COUNTER

PSEN
ALE/PROG TIMING INSTRUCTION
AND REGISTER DUAL DPTR
EA / VPP CONTROL
RST

WATCH PORT 3 PORT 1 ISP PROGRAM

DOG LATCH LATCH PORT LOGIC

OSC
PORT 3 DRIVERS PORT 1 DRIVERS

P3.0 - P3.7 P1.0 - P1.7

3
2601A–12/01
Pin Description
VCC Supply voltage.

GND Ground.

Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight
TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance
inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes
during program verification. External pull-ups are required during program verification.

Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (IIL) because of the internal pull-ups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the fol-
lowing table.
Port 1 also receives the low-order address bytes during Flash programming and verification.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2), clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control)
P1.5 MOSI (used for In-System Programming)
P1.6 MISO (used for In-System Programming)
P1.7 SCK (used for In-System Programming)

Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being
pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and
during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Spe-
cial Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash pro-
gramming and verification.

Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.

4 AT89LS52
2601A–12/01
 AT89LS52

Port 3 also serves the functions of various special features of the AT89LS52, as shown in the
following table.

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)

RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DIS-
RTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state
of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may
be used for external timing or clocking purposes. Note, however, that one ALE pulse is
skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled
high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution
mode.

PSEN Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89LS52 is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during each access
to external data memory.

EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (V PP ) during Flash
programming.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

5
2601A–12/01
Table 1. AT89LS52 SFR Map and Reset Values

0F8H 0FFH

B
0F0H 0F7H
00000000

0E8H 0EFH

ACC
0E0H 0E7H
00000000

0D8H 0DFH

PSW
0D0H 0D7H
00000000

T2CON T2MOD RCAP2L RCAP2H TL2 TH2

0C8H 0CFH
00000000 XXXXXX00 00000000 00000000 00000000 00000000

0C0H 0C7H

IP
0B8H 0BFH
XX000000

P3
0B0H 0B7H
11111111

IE
0A8H 0AFH
0X000000

P2 AUXR1 WDTRST
0A0H 0A7H
11111111 XXXXXXX0 XXXXXXXX

SCON SBUF
98H 9FH
00000000 XXXXXXXX

P1
90H 97H
11111111

TCON TMOD TL0 TL1 TH0 TH1 AUXR

88H 8FH
00000000 00000000 00000000 00000000 00000000 00000000 XXX00XX0

P0 SP DP0L DP0H DP1L DP1H PCON

80H 87H
11111111 00000111 00000000 00000000 00000000 00000000 0XXX0000

6 AT89LS52
2601A–12/01
 AT89LS52

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read
accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea-
tures. In that case, the reset or inactive values of the new bits will always be 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in
Table ) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture
mode or 16-bit auto-reload mode.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six
interrupt sources in the IP register.
Table 2. T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
7 6 5 4 3 2 1 0

Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1
or TCLK = 1.
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer
2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

7
2601A–12/01
Table 3. AUXR: Auxiliary Register
AUXR Address = 8EH Reset Value = XXX00XX0B
Not Bit Addressable
– – – WDIDLE DISRTO – – DISALE
Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

DISALE Disable/Enable ALE
DISALE Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
DISRTO Disable/Enable Reset out
DISRTO
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode
WDIDLE
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data
Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1
selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before
accessing the respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power
up. It can be set and rest under software control and is not affected by reset.
Table 4. AUXR1: Auxiliary Register 1
AUXR1 Address = A2H Reset Value = XXXXXXX0B
Not Bit Addressable
– – – – – – – DPS
Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

DPS Data Pointer Register Select
DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H

8 AT89LS52
2601A–12/01
 AT89LS52

Memory MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
Organization bytes each of external Program and Data Memory can be addressed.

Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89LS52, if EA is connected to VCC, program fetches to addresses 0000H through
1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are
directed to external memory.

Data Memory The AT89LS52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel
address space to the Special Function Registers. This means that the upper 128 bytes have
the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode
used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the
SFR space. Instructions which use direct addressing access of the SFR space.
For example, the following direct addressing instruction accesses the SFR at location 0A0H
(which is P2).
MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the
following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at
address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data
RAM are available as stack space.

9
2601A–12/01
Watchdog The WDT is intended as a recovery method in situations where the CPU may be subjected to
Timer software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a
(One-time user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).
Enabled with When the WDT is enabled, it will increment every machine cycle while the oscillator is running.
The WDT timeout period is dependent on the external clock frequency. There is no way to dis-
Reset-out) able the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment
every machine cycle while the oscillator is running. This means the user must reset the WDT
at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H
to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written.
When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET
pulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it
should be serviced in those sections of code that will periodically be executed within the time
required to prevent a WDT reset.

WDT During In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
Power-down down mode, the user does not need to service the WDT. There are two methods of exiting
Power-down mode: by a hardware reset or via a level-activated external interrupt which is
and Idle enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89LS52 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To pre-
vent the WDT from resetting the device while the interrupt pin is held low, the WDT is not
started until the interrupt is pulled high. It is suggested that the WDT be reset during the inter-
rupt service for the interrupt used to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best
to reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit =
0) as the default state. To prevent the WDT from resetting the AT89LS52 while in IDLE mode,
the user should always set up a timer that will periodically exit IDLE, service the WDT, and
reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.

UART The UART in the AT89LS52 operates the same way as the UART in the AT89C51 and
AT89C52. For further information on the UART operation, refer to the ATMEL Web site
(http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architecture Flash
Microcontroller’, then ‘Product Overview’.

10 AT89LS52
2601A–12/01
 AT89LS52

Timer 0 and 1 Timer 0 and Timer 1 in the AT89LS52 operate the same way as Timer 0 and Timer 1 in the
AT89C51 and AT89C52. For further information on the timers’ operation, refer to the ATMEL
Web site (http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architec-
ture Flash Microcontroller’, then ‘Product Overview’.

Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The
type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has
three operating modes: capture, auto-reload (up or down counting), and baud rate generator.
The modes are selected by bits in T2CON, as shown in Table . Timer 2 consists of two 8-bit
registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine
cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the
oscillator frequency.

Table 5. Timer 2 Operating Modes

RCLK +TCLK CP/RL2 TR2 MODE
0 0 1 16-bit Auto-reload
0 1 1 16-bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)

In the Counter function, the register is incremented in response to a 1-to-0 transition at its cor-
responding external input pin, T2. In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one cycle and a low in the next cycle,
the count is incremented. The new count value appears in the register during S3P1 of the
cycle following the one in which the transition was detected. Since two machine cycles (24
oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24
of the oscillator frequency. To ensure that a given level is sampled at least once before it
changes, the level should be held for at least one full machine cycle.

Capture Mode In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2
is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be
used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-
0 transition at external input T2EX also causes the current value in TH2 and TL2 to be cap-
tured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit
EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture
mode is illustrated in Figure 1.

11
2601A–12/01
Figure 1. Timer in Capture Mode

OSC ÷12
C/T2 = 0

TH2 TL2 TF2

OVERFLOW
CONTROL
TR2
C/T2 = 1

T2 PIN CAPTURE

RCAP2H RCAP2L
TRANSITION
DETECTOR TIMER 2
INTERRUPT
T2EX PIN EXF2

CONTROL
EXEN2

Auto-reload Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload
(Up or Down mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR
Counter) T2MOD (see Table ). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count
up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX
pin.
Figure 2 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options
are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then
sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded
with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H
and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by
an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2
bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 2. In this mode,
the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up.
The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit
value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2,
respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal
the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes
0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit
of resolution. In this operating mode, EXF2 does not flag an interrupt.

12 AT89LS52
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 AT89LS52

Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)

OSC ÷12
C/T2 = 0

TH2 TL2

CONTR OL OVERFLOW
TR2
C/T2 = 1
RELO AD
T2 PIN TIMER 2
RCAP2H RCAP2L INTERRUPT

TF2
TRANSITION
DETECTOR

T2EX PIN EXF2

CONTROL
EXEN2

Table 6. T2MOD – Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable
– – – – – – T2OE DCEN
Bit 7 6 5 4 3 2 1 0

Symbol Function
– Not implemented, reserved for future
T2OE Timer 2 Output Enable bit
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter

13
2601A–12/01
Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)
(DOWN COUNTING RELOAD VALUE) TOGGLE

0FFH 0FFH EXF2

OSC ÷ 12 OVERFLOW
C/T2 = 0

TH2 TL2 TF2

CONTROL
TR2
C/T2 = 1 TIMER 2
INTERRUPT
T2 PIN
RCAP2H RCAP2L
COUNT
(UP COUNTING RELOAD VALUE) DIRECTION
1=UP
0=DOWN

T2EX PIN

Figure 4. Timer 2 in Baud Rate Generator Mode

TIMER 1 OVERFLOW

÷2
"0" "1"
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
SMOD1

OSC ÷2
C/T2 = 0
"1" "0"
TH2 TL2
RCLK
Rx
CONTROL CLOCK
TR2
÷ 16
C/T2 = 1
"1" "0"
T2 PIN
TCLK
RCAP2H RCAP2L Tx
CLOCK
TRANSITION ÷ 16
DETECTOR

TIMER 2
T2EX PIN EXF2 INTERRUPT

CONTROL
EXEN2

14 AT89LS52
2601A–12/01
 AT89LS52

Baud Rate Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table
Generator 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the
receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK
puts Timer 2 into its baud rate generator mode, as shown in Figure 4.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2
causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and
RCAP2L, which are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the
following equation.

Modes 1 and 3 Baud Rates = Timer 2 Overflow Rate-

-----------------------------------------------------------
16

The Timer can be configured for either timer or counter operation. In most applications, it is
configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it
is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at
1/12 the oscillator frequency). As a baud rate generator, however, it increments every state
time (at 1/2 the oscillator frequency). The baud rate formula is given below.

Modes 1 and 3 Oscillator Frequency

--------------------------------------- = --------------------------------------------------------------------------------------
Baud Rate 32 x [65536-RCAP2H,RCAP2L)]

where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit
unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or
TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an
interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not
cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a
baud rate generator, T2EX can be used as an extra external interrupt.
Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2
or TL2 should not be read from or written to. Under these conditions, the Timer is incremented
every state time, and the results of a read or write may not be accurate. The RCAP2 registers
may be read but should not be written to, because a write might overlap a reload and cause
write and/or reload errors. The timer should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.

15
2601A–12/01
Figure 5. Timer 2 in Clock-Out Mode

TL2 TH2
OSC ÷2
(8-BITS) (8-BITS)

TR2

RCAP2L RCAP2H
C/T2 BIT

P1.0
÷2
(T2)

T2OE (T2MOD.1)

TRANSITION
DETECTOR

P1.1 TIMER 2
(T2EX) EXF2
INTERRUPT

EXEN2

16 AT89LS52
2601A–12/01
 AT89LS52

Programmable A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This
Clock Out pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input
the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz
to 4 MHz (for a 16 MHz operating frequency).
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared
and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2
capture registers (RCAP2H, RCAP2L), as shown in the following equation.

Oscillator Frequency
Clock-Out Frequency = ------------------------------------------------------------------------------------
-
4 x [65536-(RCAP2H,RCAP2L)]

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar
to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate
generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-
out frequencies cannot be determined independently from one another since they both use
RCAP2H and RCAP2L.

Interrupts The AT89LS52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all
shown in Figure 6.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimplemented. User software should not
write 1 to this bit position, since it may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-
ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine may have to determine whether it was TF2 or EXF2 that generated the inter-
rupt, and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2
flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

17
2601A–12/01
 Table 7. Interrupt Enable (IE) Register
(MSB) (LSB)

EA – ET2 ES ET1 EX1 ET0 EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables the interrupt.

Symbol Position Function

EA IE.7 Disables all interrupts. If EA = 0, no interrupt is
acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or clearing
its enable bit.
– IE.6 Reserved.
ET2 IE.5 Timer 2 interrupt enable bit.
ES IE.4 Serial Port interrupt enable bit.
ET1 IE.3 Timer 1 interrupt enable bit.
EX1 IE.2 External interrupt 1 enable bit.
ET0 IE.1 Timer 0 interrupt enable bit.
EX0 IE.0 External interrupt 0 enable bit.
User software should never write 1s to reserved bits, because they may be used in future AT89
products.

Figure 6. Interrupt Sources

0
INT0 IE0
1

TF0

0
INT1 IE1
1

TF1

TI
RI

TF2
EXF2

18 AT89LS52
2601A–12/01
 AT89LS52

Oscillator XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be
Characteristics configured for use as an on-chip oscillator, as shown in Figure 7. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven, as shown in Figure 8. There are no require-
ments on the duty cycle of the external clock signal, since the input to the internal clocking
circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low
time specifications must be observed.

Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special functions
registers remain unchanged during this mode. The idle mode can be terminated by any
enabled interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-
gram execution from where it left off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when idle mode is terminated by a reset, the instruction following the one that invokes
idle mode should not write to a port pin or to external memory.

Power-down In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-
Mode down is the last instruction executed. The on-chip RAM and Special Function Registers retain
their values until the Power-down mode is terminated. Exit from Power-down mode can be ini-
tiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or
INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not
be activated before VCC is restored to its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.

Figure 7. Oscillator Connections

C2
XTAL2

C1
XTAL1

GND

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

19
2601A–12/01
 Figure 8. External Clock Drive Configuration

NC XTAL2

EXTERNAL
OSCILLATOR XTAL1
SIGNAL

GND

Table 8. Status of External Pins During Idle and Power-down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data

20 AT89LS52
2601A–12/01
 AT89LS52

Program The AT89LS52 has three lock bits that can be left unprogrammed (U) or can be programmed
Memory (P) to obtain the additional features listed in the following table.
Table 9. Lock Bit Protection Modes
Lock Bits
Program Lock Bits
LB1 LB2 LB3 Protection Type
1 U U U No program lock features
2 P U U MOVC instructions executed from external program memory are
disabled from fetching code bytes from internal memory, EA is
sampled and latched on reset, and further programming of the
Flash memory is disabled
3 P P U Same as mode 2, but verify is also disabled
4 P P P Same as mode 3, but external execution is also disabled

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during
reset. If the device is powered up without a reset, the latch initializes to a random value and
holds that value until reset is activated. The latched value of EA must agree with the current
logic level at that pin in order for the device to function properly.

Programming The AT89LS52 is shipped with the on-chip Flash memory array ready to be programmed. The
the Flash – programming interface needs a high-voltage (12-volt) program enable signal and is compati-
ble with conventional third-party Flash or EPROM programmers.
Parallel Mode
The AT89LS52 code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89LS52, the address, data, and control
signals should be set up according to the Flash programming mode table and Figures 13 and
14. To program the AT89LS52, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-
write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1
through 5, changing the address and data for the entire array or until the end of the
object file is reached.
Data Polling: The AT89LS52 features Data Polling to indicate the end of a byte write cycle.
During a write cycle, an attempted read of the last byte written will result in the complement of
the written data on P0.7. Once the write cycle has been completed, true data is valid on all out-
puts, and the next cycle may begin. Data Polling may begin any time after a write cycle has
been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY out-
put signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0
is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code
data can be read back via the address and data lines for verification. The status of the individ-
ual lock bits can be verified directly by reading them back.

21
2601A–12/01
 Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-
mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled
to a logic low. The values returned are as follows.
(000H) = 1EH indicates manufactured by Atmel
(100H) = 62H indicates 89LS52
(200H) = 06H
Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the
proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns -
500 ns.
In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase
instruction. In this mode, chip erase is self-timed and takes about 500 ms.
During chip erase, a serial read from any address location will return 00H at the data output.

Programming The Code memory array can be programmed using the serial ISP interface while RST is
pulled to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After
the Flash –
RST is set high, the Programming Enable instruction needs to be executed first before other
Serial Mode operations can be executed. Before a reprogramming sequence can occur, a Chip Erase
operation is required.
The Chip Erase operation turns the content of every memory location in the Code array into
FFH.
Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be con-
nected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be
less than 1/16 of the crystal frequency. With a 16 MHz oscillator clock, the maximum SCK fre-
quency is 1 MHz.

Serial To program and verify the AT89LS52 in the serial programming mode, the following sequence
Programming is recommended:
Algorithm 1. Power-up sequence:
Apply power between VCC and GND pins.
Set RST pin to “H”.
If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 16 MHz
clock to XTAL1 pin and wait for at least 10 milliseconds.
2. Enable serial programming by sending the Programming Enable serial instruction to
pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be
less than the CPU clock at XTAL1 divided by 16.
3. The Code array is programmed one byte at a time in either the Byte or Page mode. The
write cycle is self-timed and typically takes less than 1 ms at 2.7V.
4. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO/P1.6.
5. At the end of a programming session, RST can be set low to commence normal device
operation.

Power-off sequence (if needed):

Set XTAL1 to “L” (if a crystal is not used).
Set RST to “L”.

22 AT89LS52
2601A–12/01
 AT89LS52

Turn VCC power off.

Data Polling: The Data Polling feature is also available in the serial mode. In this mode, dur-
ing a byte write cycle an attempted read of the last byte written will result in the complement of
the MSB of the serial output byte on MISO.

Serial Programming Instruction Set

The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in Table 11.

23
2601A–12/01
Programming Interface – Parallel Mode
Every code byte in the Flash array can be programmed by using the appropriate combination of control signals. The write
operation cycle is self-timed and once initiated, will automatically time itself to completion.
All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local pro-
gramming vendor for the appropriate software revision.
Table 10. Flash Programming Modes
P2.4-0 P1.7-0
ALE/ EA/ P0.7-0
Mode VCC RST PSEN PROG VPP P2.6 P2.7 P3.3 P3.6 P3.7 Data Address
(2)
Write Code Data 5V H L 12V L H H H H DIN A12-8 A7-0

Read Code Data 5V H L H H L L L H H DOUT A12-8 A7-0

(3)
Write Lock Bit 1 5V H L 12V H H H H H X X X

(3)
Write Lock Bit 2 5V H L 12V H H H L L X X X

(3)
Write Lock Bit 3 5V H L 12V H L H H L X X X

P0.2,
Read Lock Bits
5V H L H H H H L H L P0.3, X X
1, 2, 3
P0.4
(1)
Chip Erase 5V H L 12V H L H L L X X X

Read Atmel ID 5V H L H H L L L L L 1EH X 0000 00H

Read Device ID 5V H L H H L L L L L 62H X 0001 00H

Read Device ID 5V H L H H L L L L L 06H X 0010 00H

Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase.

2. Each PROG pulse is 200 ns - 500 ns for Write Code Data.
3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits.
4. RDY/BSY signal is output on P3.0 during programming.
5. X = don’t care.

24 AT89LS52
2601A–12/01
 AT89LS52

Figure 9. Programming the Flash Memory (Parallel Mode)

4.5V - 5.5V
AT89LS52
A0 - A7 VCC
ADDR. P1.0-P1.7
0000H/1FFFH PGM
P2.0 - P2.4 P0 DATA
A8 - A12
P2.6
SEE FLASH P2.7 ALE PROG
PROGRAMMING P3.3
MODES TABLE P3.6
P3.7
XTAL2 EA VIH/VPP

3-16 MHz
RDY/
P3.0
BSY

XTAL1 RST VIH

GND PSEN

Figure 10. Verifying the Flash Memory (Parallel Mode)

4.5V - 5.5V
AT89LS52
A0 - A7 VCC
ADDR. P1.0-P1.7
0000H/1FFFH PGM DATA
P2.0 - P2.4 P0 (USE 10K
A8 - A12
PULLUPS)
P2.6
SEE FLASH P2.7 ALE
PROGRAMMING P3.3
MODES TABLE P3.6
VIH
P3.7

XTAL 2 EA

3-16 MHz

XTAL1 RST VIH

GND PSEN

25
2601A–12/01
Flash Programming and Verification Characteristics (Parallel Mode)
TA = 20°C to 30°C, VCC = 4.5V to 5.5V
Symbol Parameter Min Max Units
VPP Programming Supply Voltage 11.5 12.5 V
IPP Programming Supply Current 10 mA
ICC VCC Supply Current 30 mA
1/tCLCL Oscillator Frequency 3 16 MHz
tAVGL Address Setup to PROG Low 48tCLCL
tGHAX Address Hold After PROG 48tCLCL
tDVGL Data Setup to PROG Low 48tCLCL
tGHDX Data Hold After PROG 48tCLCL
tEHSH P2.7 (ENABLE) High to VPP 48tCLCL
tSHGL VPP Setup to PROG Low 10 µs
tGHSL VPP Hold After PROG 10 µs
tGLGH PROG Width 0.2 1 µs
tAVQV Address to Data Valid 48tCLCL
tELQV ENABLE Low to Data Valid 48tCLCL
tEHQZ Data Float After ENABLE 0 48tCLCL
tGHBL PROG High to BUSY Low 1.0 µs
tWC Byte Write Cycle Time 50 µs

Figure 11. Flash Programming and Verification Waveforms – Parallel Mode

PROGRAMMING VERIFICATION
P1.0 - P1.7
ADDRESS ADDRESS
P2.0 - P2.4
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tGHDX
tAVGL tGHAX
ALE/PROG
tSHGL tGHSL
tGLGH
VPP LOGIC 1
EA/VPP LOGIC 0

tEHSH tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.0
(RDY/BSY) BUSY READY
tWC

26 AT89LS52
2601A–12/01
 AT89LS52

Figure 12. Flash Memory Serial Downloading

VCC
AT89LS52
VCC

INSTRUCTION
INPUT P1.5/MOSI
DATA OUTPUT P1.6/MISO

CLOCK IN P1.7/SCK

XTAL2

3-16 MHz

XTAL1 RST VIH

GND

Flash Programming and Verification Waveforms – Serial Mode

Figure 13. Serial Programming Waveforms

7 6 5 4 3 2 1 0

27
2601A–12/01
Table 11. Serial Programming Instruction Set
Instruction
Format
Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation
Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming
0110 1001 while RST is high
(Output on MISO)
Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase Flash memory
array

A12
A11
A10
A9
A8

A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read Program Memory 0010 0000 xxx Read data from Program
(Byte Mode) memory in the byte mode

A12
A11
A10
A9
A8

D7
D6
D5
D4
D3
D2
D1
D0
Write Program Memory 0100 0000 xxx Write data to Program

A7
A6
A5
A4
A3
A2
A1
A0
(Byte Mode) memory in the byte mode
Write Lock Bits(2) B1
B2
1010 1100 1110 00 xxxx xxxx xxxx xxxx Write Lock bits. See Note
(2).

LB3

LB2
LB1
Read Lock Bits 0010 0100 xxxx xxxx xxxx xxxx xxx xx Read back current status of
the lock bits (a programmed
lock bit reads back as a ‘1’)
Read Signature Bytes(1)
A7
A12
A11
A10
A9
A8

0010 1000 xxx xxx xxx0 Signature Byte Read Signature Byte
A12
A11
A10
A9
A8

Read Program Memory 0011 0000 xxx Byte 0 Byte 1... Byte 255 Read data from Program
(Page Mode) memory in the Page Mode
(256 bytes)
A12
A11
A10
A9
A8

Write Program Memory 0101 0000 xxx Byte 0 Byte 1... Byte 255 Write data to Program
(Page Mode) memory in the Page Mode
(256 bytes)

}
Notes: 1. The signature bytes are not readable in Lock Bit Modes 3 and 4.
2. B1 = 0, B2 = 0 ---> Mode 1, no lock protection Each of the lock bits needs to be activated sequentially before
B1 = 0, B2 = 1 ---> Mode 2, lock bit 1 activated Mode 4 can be executed.
B1 = 1, B2 = 0 ---> Mode 3, lock bit 2 activated
B1 = 1, B1 = 1 ---> Mode 4, lock bit 3 activated
After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data
bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1.
For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are
latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready
to be decoded.

28 AT89LS52
2601A–12/01
 AT89LS52

Serial Figure 14. Serial Programming Timing

Programming
Characteristics
MOSI
tOVSH tSHOX tSLSH

SCK
tSHSL

MISO
tSLIV

Table 12. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7V - 4.0V (Unless otherwise noted)
Symbol Parameter Min Typ Max Units
1/tCLCL Oscillator Frequency 0 16 MHz
tCLCL Oscillator Period 62.5 ns
tSHSL SCK Pulse Width High 8 tCLCL ns
tSLSH SCK Pulse Width Low 8 tCLCL ns
tOVSH MOSI Setup to SCK High tCLCL ns
tSHOX MOSI Hold after SCK High 2 tCLCL ns
tSLIV SCK Low to MISO Valid 10 16 32 ns
tERASE Chip Erase Instruction Cycle Time 500 ms
tSWC Serial Byte Write Cycle Time 64 tCLCL + 400 µs

29
2601A–12/01
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage ............................................ 6.6V conditions for extended periods may affect
device reliability.
DC Output Current...................................................... 15.0 mA

DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 2.7V to 4.0V, unless otherwise noted.
Symbol Parameter Condition Min Max Units

VIL Input Low Voltage (Except EA) -0.5 0.7 V

VIL1 Input Low Voltage (EA) -0.5 0.2 VCC-0.3 V

VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V

VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V

(1)
VOL Output Low Voltage (Ports 1,2,3) IOL = 0.8 mA 0.45 V
(1)
Output Low Voltage
VOL1 IOL = 1.6 mA 0.45 V
(Port 0, ALE, PSEN)

IOH = -60 µA, VCC = 5V ± 10% 2.4 V

Output High Voltage
VOH IOH = -25 µA 0.75 VCC V
(Ports 1,2,3, ALE, PSEN)
IOH = -10 µA 0.9 VCC V

IOH = -800 µA, VCC = 5V ± 10% 2.4 V

Output High Voltage
VOH1 IOH = -300 µA 0.75 VCC V
(Port 0 in External Bus Mode)
IOH = -80 µA 0.9 VCC V

IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA

Logical 1 to 0 Transition Current

ITL VIN = 2V, VCC = 5V ± 10% -650 µA
(Ports 1,2,3)

ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA

RRST Reset Pulldown Resistor 50 300 KΩ

CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF

Active Mode, 12 MHz 25 mA

Power Supply Current
ICC Idle Mode, 12 MHz 6.5 mA
(1)
Power-down Mode VCC = 4.0V 30 µA
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.

30 AT89LS52
2601A–12/01
 AT89LS52

AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
External Program and Data Memory Characteristics
16 MHz Oscillator Variable Oscillator
Symbol Parameter Min Max Min Max Units
1/tCLCL Oscillator Frequency 0 16 MHz
tLHLL ALE Pulse Width 85 2tCLCL-40 ns
tAVLL Address Valid to ALE Low 22 tCLCL-40 ns
tLLAX Address Hold After ALE Low 32 tCLCL-30 ns
tLLIV ALE Low to Valid Instruction In 150 4tCLCL-100 ns
tLLPL ALE Low to PSEN Low 32 tCLCL-30 ns
tPLPH PSEN Pulse Width 142 3tCLCL-45 ns
tPLIV PSEN Low to Valid Instruction In 82 3tCLCL-105 ns
tPXIX Input Instruction Hold After PSEN 0 0 ns
tPXIZ Input Instruction Float After PSEN 37 tCLCL-25 ns
tPXAV PSEN to Address Valid 75 tCLCL-8 ns
tAVIV Address to Valid Instruction In 207 5tCLCL-105 ns
tPLAZ PSEN Low to Address Float 10 10 ns
tRLRH RD Pulse Width 275 6tCLCL-100 ns
tWLWH WR Pulse Width 275 6tCLCL-100 ns
tRLDV RD Low to Valid Data In 147 5tCLCL-165 ns
tRHDX Data Hold After RD 0 0 ns
tRHDZ Data Float After RD 65 2tCLCL-60 ns
tLLDV ALE Low to Valid Data In 350 8tCLCL-150 ns
tAVDV Address to Valid Data In 397 9tCLCL-165 ns
tLLWL ALE Low to RD or WR Low 137 239 3tCLCL-50 3tCLCL+50 ns
tAVWL Address to RD or WR Low 122 4tCLCL-130 ns
tQVWX Data Valid to WR Transition 13 tCLCL-50 ns
tQVWH Data Valid to WR High 287 7tCLCL-150 ns
tWHQX Data Hold After WR 13 tCLCL-50 ns
tRLAZ RD Low to Address Float 0 0 ns
tWHLH RD or WR High to ALE High 23 103 tCLCL-40 tCLCL+40 ns

31
2601A–12/01
External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL tLLIV
tLLPL
PSEN tPLIV
tPXAV
tPLAZ
tPXIZ
tLLAX
tPXIX
PORT 0 A0 - A7 INSTR IN A0 - A7

tAVIV

PORT 2 A8 - A15 A8 - A15

External Data Memory Read Cycle

tLHLL
ALE
tWHLH

PSEN
tLLDV
tRLRH
tLLWL

RD tLLAX
tRLDV tRHDZ
tAVLL
tRLAZ
tRHDX

PORT 0 A0 - A7 FROM RI OR DPL DATA IN A0 - A7 FROM PCL INSTR IN

tAVWL
tAVDV
PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH

32 AT89LS52
2601A–12/01
 AT89LS52

External Data Memory Write Cycle

tLHLL
ALE
tWHLH

PSEN
tLLWL tWLWH

WR tLLAX
tAVLL tQVWX tWHQX
tQVWH

PORT 0 A0 - A7 FROM RI OR DPL DATA OUT A0 - A7 FROM PCL INSTR IN

tAVWL

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH

External Clock Drive Waveforms

tCHCX
tCHCX tCLCH tCHCL
VCC - 0.5V
0.7 VCC

0.2 VCC - 0.1V

0.45V
tCLCX
tCLCL

External Clock Drive

Symbol Parameter Min Max Units
1/tCLCL Oscillator Frequency 0 16 MHz
tCLCL Clock Period 62.5 ns
tCHCX High Time 20 ns
tCLCX Low Time 20 ns
tCLCH Rise Time 20 ns
tCHCL Fall Time 20 ns

33
2601A–12/01
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 2.7V to 4.0V and Load Capacitance = 80 pF.
12 MHz Osc Variable Oscillator
Symbol Parameter Min Max Min Max Units
tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs
tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns
tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-80 ns
tXHDX Input Data Hold After Clock Rising Edge 0 0 ns
tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

Shift Register Mode Timing Waveforms

INSTRUCTION 0 1 2 3 4 5 6 7 8
ALE
tXLXL
CLOCK
tQVXH
tXHQX
WRITE TO SBUF 0 1 2 3 4 5 6 7
tXHDX
OUTPUT DATA tXHDV SET TI
CLEAR RI VALID VALID VALID VALID VALID VALID VALID VALID

INPUT DATA SET RI

AC Testing Input/Output Waveforms(1)

VCC - 0.5V
0.2 VCC + 0.9V
TEST POINTS
0.2 VCC - 0.1V
0.45V

Note: 1. AC Inputs during testing are driven at VCC - 0.5V

for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.

Float Waveforms(1)
V LOAD+ 0.1V V OL - 0.1V

V LOAD Timing Reference

Points
V LOAD - 0.1V V OL + 0.1V

Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded VOH/VOL level occurs.

34 AT89LS52
2601A–12/01
 AT89LS52

Ordering Information
Speed Power
(MHz) Supply Ordering Code Package Operation Range
16 2.7V to 4.0V AT89LS52-16AC 44A Commercial
AT89LS52-16JC 44J (0°C to 70°C)
AT89LS52-16PC 40P6
AT89LS52-16AI 44A Industrial
AT89LS52-16JI 44J (-40°C to 85°C)
AT89LS52-16PI 40P6

Package Type
44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)

35
2601A–12/01
Packaging Information

44A

PIN 1
B
PIN 1 IDENTIFIER

e E1 E

D1
D

C 0˚~7˚

A1 A2 A
L
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable E1 9.90 10.00 10.10 Note 2
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum B 0.30 – 0.45
plastic body size dimensions including mold mismatch.
C 0.09 – 0.20
3. Lead coplanarity is 0.10 mm maximum.
L 0.45 – 0.75
e 0.80 TYP

10/5/2001
TITLE DRAWING NO. REV.
2325 Orchard Parkway
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
R San Jose, CA 95131 44A B
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

36 AT89LS52
2601A–12/01
 AT89LS52

44J

1.14(0.045) X 45˚
1.14(0.045) X 45˚ PIN NO. 1
0.318(0.0125)
IDENTIFIER 0.191(0.0075)

E1 E B1 D2/E2
B

e
A2
D1
A1
D
A

0.51(0.020)MAX COMMON DIMENSIONS

45˚ MAX (3X) (Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion. E1 16.510 – 16.662 Note 2
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 D2/E2 14.986 – 16.002
and E1 include mold mismatch and are measured at the extreme
B 0.660 – 0.813
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum. B1 0.330 – 0.533
e 1.270 TYP

10/04/01

TITLE DRAWING NO. REV.

2325 Orchard Parkway
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) 44J B
R San Jose, CA 95131

37
2601A–12/01
40P6

D
PIN
1

E1

SEATING PLANE

A1
L
B
B1
e

COMMON DIMENSIONS
0º ~ 15º REF (Unit of Measure = mm)
C
SYMBOL MIN NOM MAX NOTE

eB A – – 4.826
A1 0.381 – –
D 52.070 – 52.578 Note 2
E 15.240 – 15.875
E1 13.462 – 13.970 Note 2
B 0.356 – 0.559

Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. B1 1.041 – 1.651
2. Dimensions D and E1 do not include mold Flash or Protrusion. L 3.048 – 3.556
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP

09/28/01
TITLE DRAWING NO. REV.
2325 Orchard Parkway
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual 40P6 B
R San Jose, CA 95131 Inline Package (PDIP)

38 AT89LS52
2601A–12/01
 Atmel Headquarters Atmel Product Operations
Corporate Headquarters Atmel Colorado Springs
2325 Orchard Parkway 1150 E. Cheyenne Mtn. Blvd.
San Jose, CA 95131 Colorado Springs, CO 80906
TEL (408) 441-0311 TEL (719) 576-3300
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Atmel Smart Card ICs
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TEL (44) 1355-357-000
FAX (44) 1355-242-743

e-mail
[email protected]
Web Site
http://www.atmel.com

© Atmel Corporation 2001.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.

ATMEL ® is the registered trademark of Atmel.

MCS-51 ® is the registered trademark of Intel Corporation.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.

2601A–12/01/0M