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4x1 Using 2x1

This document describes the design and implementation of a 4-to-1 multiplexer (mux) using two 2-to-1 mux modules. It defines a 4x1 mux module that instantiates two 2x1 mux modules and combines their outputs. It also defines a 2x1 mux module. A testbench simulates the 4x1 mux design and verifies the output matches expectations based on the input and select signals.

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940 views

4x1 Using 2x1

This document describes the design and implementation of a 4-to-1 multiplexer (mux) using two 2-to-1 mux modules. It defines a 4x1 mux module that instantiates two 2x1 mux modules and combines their outputs. It also defines a 2x1 mux module. A testbench simulates the 4x1 mux design and verifies the output matches expectations based on the input and select signals.

Uploaded by

jakk234
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
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https://www.edaplayground.

com/x/4qJM
// Design of 4x1 mux using 2x1 mux
module mux_4x1_using_2x1 (I,S,f);
//input declaration
input [3:0] I;
input [1:0] S;

//output declaration
output f;

//implicit declaration
wire [3:0] I;
wire [1:0] S;
wire f;
wire g1,g2;

mux_2X1 M3 (.I({I[3],I[2]}),
.s(S[0]),
.y(g2));
mux_2X1 M2 (.I({I[1],I[0]}),
.s(S[0]),
.y(g1));
mux_2X1 M1 (.I({g2,g1}),
.s(S[1]),
.y(f));

endmodule

// Design of 2x1 mux


module mux_2X1 (I,s,y);

//input declaration
input [1:0] I;
input s;

//output declaration
output y;

//implicit declaration
wire [1:0] I;
wire s;
wire y;

assign y = s ? I[1] :I[0];

endmodule

/******* TB *******/
// Testbench for design of 4x1 mux using 2x1

module Top;

//implicit declaration
reg [3:0] I;
reg [1:0] S;
wire f;
reg exp_f;
event sim_done;

//instantiation of 4x1 mux using 2x1 mux


mux_4x1_using_2x1 uut (.I(I),
.S(S),
.f(f));
initial
begin
$monitor("monitor: time=%t,I=%b,S=%b,f=%b,exp_f=%b",$time,I,S,f,exp_f);
end

//stimulus
initial
begin
#10;I=4'b0000;S=2'b00;
#10;I=4'b0001;S=2'b00;
#10;I=4'b0010;S=2'b01;
#10;I=4'b0100;S=2'b10;
#10;I=4'b1000;S=2'b11;
#10;I=4'b1110;S=2'b00;
#10;I=4'b1101;S=2'b01;
#10;I=4'b1011;S=2'b10;
#10;I=4'b0111;S=2'b11;
->sim_done;
end
initial
begin
@(sim_done);
#100;
$finish;
end

//checker

always@(I or S) begin
case(S)
2'b00:begin exp_f=I[0]; end
2'b01:begin exp_f=I[1]; end
2'b10:begin exp_f=I[2]; end
2'b11:begin exp_f=I[3]; end
default: exp_f='x;
endcase
end
always@(f) begin
if(exp_f===f) begin
$display("Matched: time=%t,I=%b,S=%b,f=%b,exp_f=%b",$time,I,S,f,exp_f);
end
else begin
$error("Not Matched: time=%t,I=%b,S=%b,f=%b,exp_f=%b",
$time,I,S,f,exp_f);
end
end

endmodule

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