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01 Tutorial

This document provides instructions for a Quartus II tutorial that involves implementing a toggle flip-flop (TFF) component using both a schematic design and VHDL description. It describes creating a new Quartus project, adding a schematic source file with the TFF component, simulating the design, assigning pins to the DE2-115 board, compiling and programming the FPGA. It also provides steps for creating a VHDL source file with a TFF description and completing the same implementation tasks.

Uploaded by

BINOD KUMAR
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
69 views

01 Tutorial

This document provides instructions for a Quartus II tutorial that involves implementing a toggle flip-flop (TFF) component using both a schematic design and VHDL description. It describes creating a new Quartus project, adding a schematic source file with the TFF component, simulating the design, assigning pins to the DE2-115 board, compiling and programming the FPGA. It also provides steps for creating a VHDL source file with a TFF description and completing the same implementation tasks.

Uploaded by

BINOD KUMAR
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Quartus II Tutorial

Task:
This tutorial exercise introduces FPGA design flow for Altera's Quartus II software. In
schematic editor instantiate a TFF storage element. Simulate the design to learn how this
component is working. Assign pushbutton to the clock input, switches to all other inputs
and LED to the trigger output. Using DE2-115 board implement the storage element. Write
a VHDL description of the same trigger, simulate it to verify correctness and implement it
in the same way as before. Refer to DE2-115 board manual for pin numbers.

Quartus II overview
Quartus II development software provides a complete design environment for System on a
Programmable Chip (SOPC) design. Quartus II offers easy design entry (using schematics,
block diagrams, AHDL, VHDL, Verilog and SystemVerilog), powerful logic synthesis,
functional and timing simulation, device programming and verification.

The default Quartus II software graphical user interface (Figure 1) can be divided into six
main components:
Drop-down Menus – provide access to all features of Quartus II software.
Adjustable Toolbar – provides shortcuts to the most frequently used tools.
Project Navigator window – provides control over project options and source files.
Status window – provides status information on any process in progress.
Editor window – provides source file review and editing capabilities.
Console window – provides design flow related messages.

The default toolbar (Figure 2) provides a quick launch capability for the most frequently
used tools. The leftmost icon opens and closes Project Navigator window. Right next to it is
the project Settings icon. The following three icons provide access to Assignment Editor,
Pin Planner and Chip Planner. These tools are used to place area and timing constraints on
the design. Any running process can be stopped by clicking on the Stop Processing icon.
The icon with a purple triangle-shaped symbol starts full design compilation, which
generates a configuration file in the end. Next to it is a Start Analysis & Synthesis icon,
which is the first step of the full compilation process. Icons with watches launch Timing
Analyzer tool. The icon with a blue triangle-shaped symbol starts the simulation. The
following icon opens compilation report. Next to it, is the Programmer icon. This tool is
used to configure Altera FPGA devices. The icon with three rectangles starts Qsys System
Integration Tool (this tool will be discussed later). And finally, the question mark icon
opens Quartus II help file.

Figure 1: Quartus II software graphical user interface

Figure 2: The default toolbar


Creating a new project
On the File drop-down menu select New Project Wizard... option. Choose the directory
for this particular project, then name the project. Exactly the same name will be given to
the top-level design entity automatically. Click Next. As there is no files to add click Next
once again. Set Family to Cyclone IVE and select EP4CE115F29C7 device (the same
device is highlighted in Figure 3). Settings of the Show in 'Available device' list menu
would just reduce the list, but are not required. Click Next until the Summary page, then
click Finish to create new project.

Figure 3: Family & Device Settings

Creating a schematic source file


On the File drop-down menu select New. Choose the Block Diagram/Schematic File type
and click OK. An empty workspace opens up in editor window. To the left is the schematic
editor toolbar, Figure 4 shows the most important icons. The leftmost icon is used to detach
source file editor and attach it back. Next to it is a Selection Tool icon. All objects can be
selected with this option turned on. The following icon opens Symbol Tool, all design
primitives can be selected there. To connect the instances use the next two icons. Icon with
a thin line represents a single wire, icon with a thick line – the bus. The last icon selects the
Zoom Tool, left-click zooms editor window in and right-click zooms it out.

Figure 4: Schematic editor toolbar

Open the Symbol Tool. Expand the libraries folder first, then primitives. Most of the
standard components can be found here. Expand storage folder and select tff component.
Click OK. The trigger is now attached to the mouse cursor, left-click to place it anywhere
on the workspace. Enable Selection Tool to detach the element. Open the Symbol Tool
again and expand pin folder. Trigger has four inputs and one output, thus four input and
one output pins are needed. Make connections using wires, not buses. Double-click each
pin to open Pin Properties dialog box and rename them. Save the result schematic
(Figure 5), giving it the project entity name to make it top-level source file. Note that
Quartus II does not have an in-built simulator, thus en external simulator (e.g. ModelSim
Altera Starter Edition) should be used to verify the functionality of the design. However, it
is not possible to simulate schematic source files unless they are converted to HDL first.

Figure 5: TFF component

Pin assignment
Run Analysis & Synthesis by pressing the corresponding icon on the default toolbar, then
open Pin Planner tool. In Location column provide the appropriate pin numbers. Figure 6
provides an example pin assignment. Clock input is assigned to pushbutton KEY3, input
CLRN is assigned to switch SW2, input PRN is assigned to switch SW1, input T is
assigned to switch SW0, output Q is assigned to LEDR0. When pin assignment is made,
simply close the Pin Planner.
Figure 6: Pin assignment

To eliminate the possibility of any damage to the board all unused pins must be set as
inputs. Click on the Settings icon and select Device category. Click Device & Pin
Options... and switch to Unused Pins tab. Set Reserve all unused pins to As input
tri-stated. Click OK, then click OK again. Repeat this step for any new project.

Programming FPGA device


Click on the Start Compilation icon in the main toolbar to perform a full compilation and
generate the configuration file (project_name.sof). Launch the Programmer tool from the
same toolbar. The configuration file is added automatically. If No Hardware message is
displayed, then click Hardware Setup... button. Click Add Hardware... button and set
Hardware type to ByteBlasterMV or ByteBlaster II and Port to USB1. Click OK, then
Close. No Hardware message should be replaced with ByteBlaster [USB1]. Set Mode to
JTAG, select the Program/Configure box and click Start. The FPGA device is now
configured. Test the design using switches to generate inputs and pushbutton to generate
clock signal. Observe the trigger output on LED.

Creating a VHDL source file


Create a new project, On the File drop-down menu select New. Choose the VHDL File
type and click OK. The VHDL file is totally empty. To insert entity and architecture
templates right-click the VHDL editor window and select Insert Template... option.
Depending on the code inclusion of some standard IEEE VHDL libraries may also be
required (e.g. STD_LOGIC_1164, NUMERIC_STD, etc.). Write a VHDL description of
the TFF component, make sure it works exactly the same as in schematic implementation.
Run a simulation (optional), assign pins and implement the design just like before.

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