Lab Report#05: Basharat Khattak
Lab Report#05: Basharat Khattak
LAB REPORT#05
BASHARAT KHATTAK
CLASS # 37
17/4/2014
TRUTH TABLE:
Bin X Y D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
̅̅̅̅̅̅̅) + 𝑋̅. 𝑌
𝐵 = 𝑍. (𝑋@𝑌
PROCEDURE:
First of all open the DSCH software and start from the basics i-e make the simple full subtractor
circuit and check it for various inputs and see it’s timing diagram. After that make the full subtractor
schematic diagram by making four different IC’s of full subtractor schematic whose output is fed into 7-
segments display. Two keyboard ports are used for 4-bit(i-e hexa dicimal) inputs. At last simulate the
circuit and verify the output with truth table.
SCHEMATIC DAIGRAM OF SINGLE BIT SUBTRACTOR:
TIMING DAIGRAM:
IC FORM:
The IC converted form of the full subtractor circuit is given below.
SCHEMATIC DAIGRAM OF 4-BIT SUBTRACTOR :
TIMING DAIGRAM:
Reference:
1. http://www.ee.surrey.ac.uk/Projects/Labview/gatesfunc/
2. http://doyle.wcdcb.ca/ICE4MI/digital_electronics/karnaugh_maps.htm
3. Book: Digital Logic Design by Moris Mano
4. Book: Fundamentals of Microelectronics by Behzad Rezvi