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MAX9218 27-Bit, 7MHz-to-35MHz

DC-Balanced LVDS Deserializer
General Description Features
The MAX9218 digital video serial-to-parallel converter ● Proprietary Data Decoding for DC Balance and
deserializes a total of 27 bits during data and control phas- Reduced EMI
es. In the data phase, the LVDS serial input is converted ● Control Data Deserialized During Video Blanking
to 18 bits of parallel video data and in the control phase,
the input is converted to 9 bits of parallel control data. ● Five Control Data Inputs Are Single Bit-Error Tolerant
The separate video and control phases take advantage of ● Output Transition Time Is Scaled to Operating
video timing to reduce the serial data rate. The MAX9218 Frequency for Reduced EMI
pairs with the MAX9217 serializer to form a complete digi- ● Staggered Output Switching Reduces EMI
tal video transmission system.
● Output Enable Allows Busing of Outputs
Proprietary data decoding reduces EMI and provides DC
● Clock Pulse Stretch on Lock
balance. The DC balance allows AC coupling, providing
isolation between the transmitting and receiving ends of ● Wide ±2% Reference Clock Tolerance
the interface. The MAX9218 features a selectable rising ● Synchronizes to MAX9217 Serializer Without
or falling output latch edge. External Control
ESD tolerance is specified for ISO 10605 with ±10kV ● ISO 10605 ESD Protection
contact discharge and ±30kV air discharge.
● Separate Output Supply Allows Interface to 1.8V to
The MAX9218 operates from a +3.3V core supply and 3.3V Logic
features a separate output supply for interfacing to 1.8V
● +3.3V Core Power Supply
to 3.3V logic-level inputs. This device is available in 48-
lead Thin QFN and LQFP packages and is specified from ● Space-Saving Thin QFN and LQFP Packages
-40°C to +85°C. ● -40°C to +85°C Operating Temperature

Applications
Ordering Information appears at end of data sheet.
● Navigation System Display
● In-Vehicle Entertainment System
● Video Camera
● LCD Displays

Pin Configurations
RGB_OUT7
RGB_OUT6
RGB_OUT5
RGB_OUT4
RGB_OUT3
RGB_OUT2
RGB_OUT1
RGB_OUT0
PCLK_OUT

TOP VIEW
VCCOGND

RGB_OUT7
RGB_OUT6
RGB_OUT5
RGB_OUT4
RGB_OUT3
RGB_OUT2
RGB_OUT1
RGB_OUT0
PCLK_OUT

VCCO GND
LOCK
VCCO

LOCK
VCCO
36
35
34
33
32
31
30
29
28
27
26
25

36
35
34
33
32
31
30
29
28
27
26
25

VCCOGND 37 24 DE_OUT
VCCO 38 23 CNTL_OUT8 VCCO GND 37 24 DE_OUT
RGB_OUT8 39 22 CNTL_OUT7 VCCO 38 23 CNTL_OUT8
RGB_OUT9 40 21 CNTL_OUT6 RGB_OUT8 39 22 CNTL_OUT7
RGB_OUT10 41 20 CNTL_OUT5 RGB_OUT9 40 21 CNTL_OUT6
RGB_OUT11 42 19 CNTL_OUT4 RGB_OUT10 41 20 CNTL_OUT5
MAX9218
RGB_OUT12 43 18 CNTL_OUT3 RGB_OUT11 42 19 CNTL_OUT4
MAX9218
RGB_OUT13 44 17 CNTL_OUT2 RGB_OUT12 43 18 CNTL_OUT3
RGB_OUT14 45 16 CNTL_OUT1T RGB_OUT13 44 17 CNTL_OUT2
RGB_OUT15 46 15 CNTL_OUT0 RGB_OUT14 45 16 CNTL_OUT1
RGB_OUT16 47 14 OUTEN RGB_OUT15 46 15 CNTL_OUT0
RGB_OUT17 48 13 PWRDWN RGB_OUT16 47 14 OUTEN
+
RGB_OUT17 48 + 13 PWRDWN
1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12
R/F
RNG1
VCCLVDS
IN+
IN-
LVDS GND
PLL GND
VCCPLL
RNG0
GND
VCC
REFCLK

R/F
RNG1
VCCLVDS
IN+
IN-
LVDS GND
PLL GND
VCCPLL
RNG0
GND
VCC
REFCLK

LQFP
THIN QFN-EP

19-3557; Rev 6; 1/19

MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

Absolute Maximum Ratings

VCC_ to _GND.......................................................-0.5V to +4.0V ESD Protection
Any Ground to Any Ground...................................-0.5V to +0.5V Machine Model (RD = 0Ω, CS = 200pF)
IN+, IN- to LVDS GND..........................................-0.5V to +4.0V All Pins to GND..............................................................±200V
IN+, IN- Short Circuit to LVDS GND or VCCLVDS......Continuous Human Body Model (RD = 1.5kΩ, CS = 100pF)
IN+, IN- Short Through 0.125μF (or smaller), All Pins to GND.............................................................±3.0kV
25V Series Capacitor.........................................-0.5V to +16V ISO 10605 (RD = 2kΩ, CS = 330pF)
(R/F, OUTEN, RNG_, REFCLK, Contact Discharge (IN+, IN-) to GND.............................±10kV
PWRDWN) to GND............................... -0.5V to (VCC + 0.5V) Air Discharge (IN+, IN-) to GND.....................................±30kV
(RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, Storage Temperature Range............................. -65°C to +150°C
LOCK) to VCCO GND..........................-0.5V to (VCCO + 0.5V) Junction Temperature.......................................................+150°C
Continuous Power Dissipation (TA = +70°C) Lead Temperature (soldering, 10s).................................. +300°C
48-Lead LQFP (derate 21.7mW/°C above +70°C).....1739mW
48-Lead Thin QFN (derate 37mW/°C above +70°C).2963mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

DC Electrical Characteristics
(VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage │VID│ = 0.05V to 1.2V, input common-mode voltage VCM = │VID/2
│ to VCC - │VID/2│, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, │VID│ = 0.2V, VCM = 1.2V,
TA = +25°C.) (Notes 1, 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SINGLE-ENDED INPUTS (R/F, OUTEN, RNG0, RNG1, REFCLK, PWRDWN)
High-Level Input Voltage VIH 2.0 VCC + 0.3 V
Low-Level Input Voltage VIL -0.3 +0.8 V
VIN = -0.3V to (VCC + 0.3V),
Input Current IIN -70 +70 µA
PWRDWN = high or low
Input Clamp Voltage VCL ICL = -18mA -1.5 V
SINGLE-ENDED OUTPUTS (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK)
IOH = -100µA VCCO - 0.1
IOH = -2mA,
VCCO - 0.35
High-Level Output Voltage VOH RNG1, RNG0 = high V
IOH = -2mA, RNG1, RNG0 both not high
VCCO - 0.4
simultaneously
IOL = 100µA 0.1
IOL = 2mA,
0.3
Low-Level Output Voltage VOL RNG1, RNG0 = high V
IOL = 2mA, RNG1, RNG0 both not high
0.35
simultaneously
PWRDWN = low or OUTEN = low,
High-Impedance Output Current IOZ -10 +10 µA
VO = -0.3V to VCCO + 0.3V

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

DC Electrical Characteristics (continued)

(VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage │VID│ = 0.05V to 1.2V, input common-mode voltage VCM = │VID/2
│ to VCC - │VID/2│, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, │VID│ = 0.2V, VCM = 1.2V,
TA = +25°C.) (Notes 1, 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

RNG1, RNG0 = high, VO = 0 -10 -50
Output Short-Circuit Current IOS RNG1, RNG0 both not high mA
-7 -40
simultaneously, VO = 0
LVDS INPUT (IN+, IN-)
Differential Input High Threshold VTH 50 mV
Differential Input Low Threshold VTL -50 mV
Input Current IIN+, IIN- PWRDWN = high or low -20 +20 µA
PWRDWN = high or low 35 50 65 kΩ
Input Bias Resistor RIB VCC_ = 0 or open,
35 50 65 kΩ
PWRDWN = 0 or open, Figure 1
VCC_ = 0 or open,
Power-Off Input Current IINO+, IINO- -40 +40 µA
PWRDWN = 0 or open
POWER SUPPLY
RNG1 = high, 7MHz 25
CL = 8pF,
Worst-Case Supply Current worst-case RNG0 = low 15MHz 47
ICCW mA
pattern, RNG1 = high, 15MHz 37
Figure 2 RNG0 = high 35MHz 70
Power-Down Supply Current ICCZ (Note 3) 50 µA

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

AC Electrical Characteristics
(VCC_ = +3.0V to 3.6V, CL = 8pF, PWRDWN = high, differential input voltage │VID│ = 0.1V to 1.2V, input common-mode voltage
VCM = │VID/2│ to VCC - │VID/2│, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, │VID│ = 0.2V,
VCM = 1.2V, TA = +25°C.) (Notes 4, 5)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

REFCLK TIMING REQUIREMENTS
Period tT 28.57 333.00 ns
Frequency fCLK 7 35 MHz
Frequency Variation DfCLK REFCLK to serializer PCLK_IN -2.0 +2.0 %
Duty Cycle DC 40 50 60 %
Transition Time tTRAN 20% to 80% 6 ns
SWITCHING CHARACTERISTICS
RNG1, RNG0 = high 3.2 4.4
Output Rise Time tR Figure 3 RNG1, RNG0 both not high ns
3.8 5.5
simultaneously
RNG1, RNG0 = high 2.7 4.5
Output Fall Time tF Figure 3 RNG1, RNG0 both not high ns
3.6 5.3
simultaneously
0.4 x 0.45 x 0.6 x
PCLK_OUT High Time tHIGH Figure 4 ns
tT tT tT
0.4 x 0.45 x 0.6 x
PCLK_OUT Low Time tLOW Figure 4 ns
tT tT tT
Data Valid Before PCLK_OUT tDVB Figure 5 0.35 x tT 0.4 x tT ns
Data Valid After PCLK_OUT tDVA Figure 5 0.35 x tT 0.4 x tT ns
2.575 x 2.725 x
Input-to-Output Delay tDELAY Figure 6 tT + tT + ns
8.5 12.8
16385 x
PLL Lock to REFCLK tPLLREF Figure 7 ns
tT
Power-Down Delay tPDD Figure 7 100 ns
Output Enable Time tOE Figure 8 30 ns
Output Disable Time tOZ Figure 9 30 ns
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH and VTL.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA = +25°C.
Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ VCC - 0.3V. PWRDWN is ≤ 0.3V.
Note 4: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 5: CL includes probe and test jig capacitance.

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

Typical Operating Characteristics

(VCC_ = +3.3V, CL = 8pF, TA = +25°C, unless otherwise noted.)

WORST-CASE PATTERN OUTPUT TRANSITION TIME

SUPPLY CURRENT vs. FREQUENCY vs. OUTPUT SUPPLY VOLTAGE (VCCO)
80 7

MAX9218 toc01

MAX9218 toc02
70 6

OUTPUT TRANSITION TIME (ns)

60 tR
SUPPLY CURRENT (mA)

5
50
4
40
3 tF
30
2
20

10 1
RNG1 = RNG0 = HIGH
0 0
3 7 11 15 19 23 27 31 35 1.8 2.1 2.4 2.7 3.0 3.3
FREQUENCY (MHz) OUTPUT SUPPLY VOLTAGE (V)

OUTPUT TRANSITION TIME BIT-ERROR RATE

vs. OUTPUT SUPPLY VOLTAGE (VCCO) vs. CABLE LENGTH
7 10 -14
MAX9218 toc03

MAX9218 toc04
CAT5e
6 tR
OUTPUT TRANSITION TIME (ns)

10 -13
5
BIT-ERROR RATE

4 tF
10 -12
3

2
10 -11
35MHz CLOCK
1
700Mbps DATA RATE
RNG1 = RNG0 = BOTH NOT HIGH
FOR <12m, BER < 10-12
0 10 -10
1.8 2.1 2.4 2.7 3.0 3.3 0 4 8 12 16 20
OUTPUT SUPPLY VOLTAGE (V) CAT5e CABLE LENGTH (m)

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

Pin Description
PIN NAME FUNCTION
Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for
1 R/F latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch
edge. Internally pulled down to GND.
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input
2 RNG1
frequency. Internally pulled down to GND.
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as close to
3 VCCLVDS
the device as possible, with the smallest value capacitor closest to the supply pin.
4 IN+ Noninverting LVDS Serial Data Input
5 IN- Inverting LVDS Serial Data Input
6 LVDS GND LVDS Supply Ground
7 PLL GND PLL Supply Ground
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close to
8 VCCPLL
the device as possible, with the smallest value capacitor closest to the supply pin.
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input
9 RNG0
frequency. Internal pulldown to GND.
10 GND Digital Supply Ground
Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to GND with
11 VCC 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value
capacitor closest to the supply pin.
LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within ±2% of the serializer
12 REFCLK
PCLK_IN frequency. Internally pulled down to GND.
13 PWRDWN LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving low places the
14 OUTEN
single-ended outputs in high impedance. Internally pulled down to GND.
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the rising
15–23 CNTL_OUT [8:0] or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held at the last state
when DE_OUT is high.
LVTTL/LVCMOS Data Enable Output. High indicates RGB_OUT[17:0] are active. Low indicates
24 DE_OUT
CNTL_OUT[8:0] are active.
25, 37 VCCO GND Output Supply Ground
Output Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the
26, 38 VCCO
device as possible, with the smallest value capacitor closest to the supply pin.
27 LOCK LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.
28 PCLK_OUT LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F.
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are latched into
29–36,
RGB_OUT [17:0] the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high, and are held at the
39–48
last state when DE_OUT is low.
— EP Exposed Pad for Thin QFN Package Only. Connect to GND.

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

Functional Diagram

MAX9218 R/F
OUTEN
IN+ 1 RGB_OUT[17:0]
DC BALANCE/
IN- DECODE SER-TO-PAR 0 CNTL_OUT[8:0]
DE_OUT

PCLK_OUT
RNG0
PLL
RNG1 REFCLK

TIMING AND PWRDWN

CONTROL LOCK

IN+

0.9VCCO
RIB DE_OUT
1.2V LVDS LOCK
RECEIVER
PCLK_OUT
0.1VCCO
RGB_OUT[17:0]
RIB
CNTL_OUT[8:0] tR tF

IN-

Figure 1. LVDS Input Bias Figure 3. Output Rise and Fall Times

PCLK_OUT

PCLK_OUT
2.0V
ODD tHIGH
RGB_OUT
0.8V
CNTL_OUT
EVEN
RGB_OUT
CNTL_OUT tLOW

RISING LATCH EDGE SHOWN (R/F = HIGH).

Figure 2. Worst-Case Output Pattern Figure 4. High and Low Times

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

2.0V
PCLK_OUT
0.8V

PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE)

tDVB tDVA

DE_OUT
2.0V 2.0V
LOCK
RGB_OUT[17:0] 0.8V 0.8V

CNTL_OUT[8:0]

Figure 5. Synchronous Output Timing

20 SERIAL BITS PCLK_OUT SHOWN FOR R/F = HIGH

IN+, IN- SERIAL-WORD N SERIAL-WORD N + 1

tDELAY

PCLK_OUT

CNTL_OUT
PARALLEL-WORD N - 1 PARALLEL-WORD N
RGB_OUT

Figure 6. Deserializer Delay

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

2.0V
0.8V
PWRDWN TRANSITION
tPLLREF
WORD tPDD
FOUND

REFCLK

RECOVERED CLOCK

PCLK_OUT HIGH IMPEDANCE HIGH IMPEDANCE

CLOCK STRETCH
VALID DATA
RGB_OUT
CNTL_OUT HIGH IMPEDANCE HIGH IMPEDANCE
DE_OUT

LOCK HIGH IMPEDANCE HIGH IMPEDANCE

NOTE: R/F = HIGH

Figure 7. PLL Lock to REFCLK and Power-Down Delay

2.0V
OUTEN OUTEN
0.8V

tOE tOZ
DE_OUT DE_OUT

LOCK LOCK
RGB_OUT[17:0] HIGH-Z ACTIVE RGB_OUT[17:0] ACTIVE HIGH-Z
CNTL_OUT[8:0] CNTL_OUT[8:0]

Figure 8. Output Enable Time Figure 9. Output Disable Time

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

Detailed Description is the AC-coupled serializer and deserializer with four

The MAX9218 DC-balanced deserializer operates at a capacitors per link.
parallel-clock frequency of 7MHz to 35MHz, deserial-
izing video data to the RGB_OUT[17:0] outputs when
Applications Information
the data enable output DE_OUT is high, or control Selection of AC-Coupling Capacitors
data to the CNTL_OUT[8:0] outputs when DE_OUT See Figure 12 for calculating the capacitor values for
is low. The video phase words are decoded using two AC coupling, depending on the parallel clock frequency.
overhead bits, EN0 and EN1. Control phase words The plot shows capacitor values for two- and four-
are decoded with one overhead bit, EN0. Encoding, capacitor-per-link systems. For applications using less
performed by the MAX9217 serializer, reduces EMI than 18MHz clock frequency, use 0.1μF capacitors.
and maintains DC balance across the serial cable.
The serial input word formats are shown in Table 1 Termination and Input Bias
and Table 2. The IN+ and IN- LVDS inputs are internally connected to
Control-data inputs C0 to C4, each repeated over three +1.2V through 35kΩ (min) to provide biasing for AC cou-
serial bit times by the serializer, are decoded using major- pling (Figure 1). Assuming 100Ω interconnect, the LVDS
ity voting. Two or three bits at the same state determine input can be terminated with a 100Ω resistor. Match the
the state of the recovered bit, providing single bit-error tol- termination to the differential impedance of the intercon-
erance for C0 to C4. The state of C5 to C8 is determined nect.
by the level of the bit itself (no voting is used). Use a Thevenin termination, providing 1.2V bias, on an
AC-coupled link in noisy environments. For interconnect
AC-Coupling Benefits with 100Ω differential impedance, pull each LVDS line up
AC-coupling increases the input voltage of the LVDS to VCC with 130Ω and down to ground with 82Ω at the
receiver to the voltage rating of the capacitor. Two capaci- deserializer input (Figure 10 and Figure 11). This termina-
tors are sufficient for isolation, but four capacitors—two at tion provides both differential and common-mode termina-
the serializer output and two at the deserializer input— tion. The impedance of the Thevenin termination should
provide protection if either end of the cable is shorted be half the differential impedance of the interconnect and
to a high voltage. AC-coupling blocks low-frequency provide a bias voltage of 1.2V.
ground shifts and common-mode noise. The MAX9217
serializer can also be DC-coupled to the MAX9218
deserializer. Figure 10 is the AC-coupled serializer and
deserializer with two capacitors per link, and Figure 11

Table 1. Serial Video Phase Word Format

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17
Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.

Table 2. Serial Control Phase Word Format

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
EN0 C0 C0 C0 C1 C1 C1 C2 C2 C2 C3 C3 C3 C4 C4 C4 C5 C6 C7 C8
Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs.

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

VCC

130Ω 130Ω
R/F
* OUTEN

DC BALANCE/
DC BALANCE/
INPUT LATCH

SER-TO-PAR
RGB_IN 1 PAR-TO-SER 1 RGB_OUT

DECODE
ENCODE

OUT IN
* 0 CNTL_OUT
CNTL_IN 0
DE_OUT
82Ω 82Ω
CMF
DE_IN

PCLK_OUT
RNG0
PCLK_IN PLL
TIMING AND RNG1 REFCLK
RNG0 PLL
CONTROL
RNG1
TIMING AND PWRDWN
PWRDWN CONTROL LOCK

MAX9217 MAX9218

CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE

*CAPS CAN BE AT EITHER END.

Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link

VCC

130Ω 130Ω
R/F
OUTEN
DC BALANCE/
DC BALANCE/
INPUT LATCH

SER-TO-PAR
PAR-TO-SER

RGB_IN 1 1 RGB_OUT
DECODE
ENCODE

OUT IN
0 0 CNTL_OUT
CNTL_IN
DE_OUT
82Ω 82Ω
CMF
DE_IN

PCLK_OUT
RNG0
PCLK_IN PLL
TIMING AND RNG1 REFCLK
RNG0 PLL
CONTROL
RNG1
TIMING AND PWRDWN
PWRDWN CONTROL LOCK

MAX9217 MAX9218

CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE

Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

Input Frequency Detection

AC-COUPLING CAPACITOR VALUE
A frequency-detection circuit detects when the LVDS input vs. PARALLEL CLOCK FREQUENCY
is not switching. When not switching, all outputs except 140
LOCK are low, LOCK is high, and PCLK_OUT follows
125
REFCLK. This condition occurs, for example, if the serial-
izer is not driving the interconnect or if the interconnect 110 FOUR CAPACITORS PER LINK

CAPACITOR VALUE (nF)

is open. 95

Frequency Range Setting (RNG[1:0]) 80

The RNG[1:0] inputs select the operating frequency range 65 TWO CAPACITORS PER LINK
of the MAX9218 and the transition time of the outputs.
50
Select the frequency range that includes the MAX9217
serializer PCLK_IN frequency. Table 3 shows the select- 35

able frequency ranges and the corresponding data rates 20

and output transition times. 18 21 24 27 30 33 36
PARALLEL CLOCK FREQUENCY (MHz)
Power Down
Driving PWRDWN low puts the outputs in high impedance Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency
and stops the PLL. With PWRDWN ≤ 0.3V and all LVTTL/ of 18MHz to 35MHz
LVCMOS inputs ≤ 0.3V or ≥ VCC - 0.3V, the supply cur-
rent is reduced to less than 50μA. Driving PWRDWN high If a transition word is not detected within 220 cycles of
initiates lock to the local reference clock (REFCLK) and PCLK_OUT, LOCK is driven high and the other outputs
afterwards to the serial input. except PCLK_OUT are driven low. REFCLK is output on
PCLK_OUT and the deserializer continues monitoring
Lock and Loss of Lock (LOCK) the serial input for a transition word. See Figure 7 for the
When PWRDWN is driven high, the PLL begins lock- synchronization timing diagram.
ing to REFCLK, drives LOCK from high impedance to
high and the other outputs from high impedance to low Output Enable (OUTEN) and
except PCLK_OUT. PCLK_OUT outputs REFCLK while Busing Outputs
the PLL is locking to REFCLK. Locking to REFCLK takes The outputs of two MAX9218s can be bused to form a 2:1
a maximum of 16,385 REFCLK cycles. When locking to mux with the outputs controlled by the output enable. Wait
REFCLK is complete, the serial input is monitored for a 30ns between disabling one deserializer (driving OUTEN
transition word. When a transition word is found, LOCK low) and enabling the second one (driving OUTEN high)
is driven low indicating valid output data, and the paral- to avoid contention of the bused outputs. OUTEN controls
lel rate clock recovered from the serial input is output on all outputs.
PCLK_OUT. PCLK_OUT is stretched on the change from
Rising or Falling Output Latch Edge (R/F)
REFCLK to recovered clock (or vice versa).
The MAX9218 has a selectable rising or falling output
Table 3. Frequency Range Programming latch edge through a logic setting on R/F. Driving R/F
high selects the rising output latch edge, which latches
PARALLEL SERIAL OUTPUT the parallel output data into the next chip on the rising
RNG1 RNG0 CLOCK DATA RATE TRANSITION edge of PCLK_OUT. Driving R/F low selects the falling
(MHz) (Mbps) TIME
output latch edge, which latches the parallel output data
0 0 into the next chip on the falling edge of PCLK_OUT. The
Do not use MAX9218 output-latch-edge polarity does not need to
0 1
match the MAX9217 serializer input-latch-edge polarity.
1 0 7 to 15 140 to 300 Slow
Select the latch-edge polarity required by the chip being
1 1 15 to 35 300 to 700 Fast driven by the MAX9218.

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

Staggered and Transition Time supply and VCCLVDS GND). The grounds are isolated by
Adjusted Outputs diode connections. Bypass each VCC, VCCO, VCCPLL,
RGB_OUT[17:0] are grouped into three groups of six, and VCCLVDS pin with high-frequency, surface-mount
with each group switching about 1ns apart in the video ceramic 0.1μF and 0.001μF capacitors in parallel as close
phase to reduce EMI and ground bounce. to the device as possible, with the smallest value capaci-
tor closest to the supply pin. The outputs are powered
CNTL_OUT[8:0] switch during the control phase. Output
from VCCO, which accepts a 1.71V to 3.6V supply, allow-
transition times are slower in the 7MHz-to-15MHz range
ing direct interface to inputs with 1.8V to 3.3V logic levels.
and faster in the 15MHz-to-35MHz range.
Cables and Connectors
Data Enable Output (DE_OUT)
Interconnect for LVDS typically has a differential imped-
The MAX9218 deserializes video and control data at dif-
ance of 100Ω. Use cables and connectors that have
ferent times. Control data is deserialized during the video
matched differential impedance to minimize impedance
blanking time. DE_OUT high indicates that video data
discontinuities.
is being deserialized and output on RGB_OUT[17:0].
DE_OUT low indicates that control data is being deserial- Twisted-pair and shielded twisted-pair cables offer supe-
ized and output on CNTL_OUT[8:0]. When outputs are rior signal quality compared to ribbon cable and tend to
not being updated, the last data received is latched on the generate less EMI due to magnetic field canceling effects.
outputs. Figure 13 shows the DE_OUT timing. Balanced cables pick up noise as common mode, which
is rejected by the LVDS receiver.
Power-Supply Circuits and Bypassing
There are separate on-chip power domains for digital cir-
Board Layout
cuits and LVTTL/LVCMOS inputs (VCC supply and GND), Separate the LVTTL/LVCMOS outputs and LVDS inputs
outputs (VCCO supply and VCCO GND), PLL (VCCPLL to prevent crosstalk. A four-layer PCB with separate lay-
supply and VCCPLL GND), and the LVDS input (VCCLVDS ers for power, ground, and signals is recommended.

CONTROL DATA VIDEO DATA CONTROL DATA

PCLK_OUT

CNTL_OUT

DE_OUT

RGB_OUT

PCLK_OUT TIMING SHOWN FOR R/F = HIGH (RISING OUTPUT LATCH EDGE)
= OUTPUT DATA HELD

Figure 13. Output Timing

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

ESD Protection
The MAX9218 ESD tolerance is rated for the Human
RD
Body Model, Machine Model, and ISO 10605. ISO 10605 0Ω
specifies ESD tolerance for electronic systems.
CHARGE-CURRENT- DISCHARGE
The Human Body Model discharge components are CS LIMIT RESISTOR RESISTANCE
= 100pF and RD = 1.5kΩ (Figure 14). The ISO 10605 HIGH-
CS DEVICE
VOLTAGE STORAGE
discharge components are CS = 330pF and RD = 2kΩ DC 200pF CAPACITOR UNDER
TEST
(Figure 15). The Machine Model discharge components SOURCE
are CS = 200pF and RD = 0Ω (Figure 16).

Figure 16. Machine Model ESD Test Circuit.

RD
1MΩ 1.5kΩ

CHARGE-CURRENT- DISCHARGE Chip Information

LIMIT RESISTOR RESISTANCE
HIGH- PROCESS: CMOS
CS STORAGE DEVICE
VOLTAGE
100pF CAPACITOR UNDER
DC
TEST
SOURCE
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX9218ECM+ -40°C to +85°C 48 LQFP
Figure 14. Human Body ESD Test Circuit MAX9218ECM/V+ -40°C to +85°C 48 LQFP
MAX9218ETM+ -40°C to +85°C 48 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
RD *EP = Exposed pad.
50Ω TO 100Ω 2kΩ

CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR RESISTANCE Package Information
HIGH-
VOLTAGE CS STORAGE DEVICE For the latest package outline information and land patterns
330pF UNDER
DC CAPACITOR (footprints), go to www.maximintegrated.com/packages. Note
TEST
SOURCE that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

Figure 15. ISO 10605 Contact Discharge ESD Test Circuit 48 LQPF C48+5 21-0054
48 TQFN T4866+1 21-0141

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MAX9218 27-Bit, 7MHz-to-35MHz
DC-Balanced LVDS Deserializer

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
3 2/08 Corrected typo (REF_IN should be REFCLK) in Figure 11 11
Corrected LQFP package, added Machine Model ESD, and corrected 1, 2, 6, 7, 10, 11,
4 5/08
diagrams 14-18
5 8/09 Added automotive qualified part to Ordering Information 1
Removed all reference to 3MHz-7MHz operation in DC Electrical Charac-
6 1/19 teristics, AC Electrical Characteristics, Detailed Description, Applications 3, 4, 10, 12, 13
Information, and Table 3

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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. ©  2019 Maxim Integrated Products, Inc. │  15