U62H64SA

Automotive Fast 8K x 8 SRAM

Features Description

F Fast 8192 x 8 bit static CMOS The U62H64SA is a static RAM go High-Z until the new read infor-
RAM manufactured using a CMOS pro- mation is available. The data out-
F 35 ns Access Time cess technology with the following puts have no preferred state. If the
F Bidirectional data inputs and data operating modes: memory is driven by CMOS levels
outputs - Read - Standby in the active state, and if there is no
F Three-state outputs - Write - Data Retention change of the address, data input
F Data retention current at 3 V: The memory array is based on a and control signals W or G, the
< 50 µA 6-transistor cell. operating current (at IO = 0 mA)
F Standby current < 100 µA The circuit is activated by the rising drops to the value of the operating
F TTL/CMOS-compatible edge of E2 (at E1 = L), or the falling current in the Standby mode. The
F Automatic reduction of power edge of E1 (at E2 = H). The Read cycle is finished by the falling
dissipation in long Read or Write address and control inputs open edge of E2 or W, or by the rising
cycles simultaneously. edge of E1, respectively.
F Power supply voltage 5 V According to the information of W Data retention is guaranteed down
F Operating temperature range and G, the data inputs, or outputs, to 2 V.
-40 to 125 °C are active. During the active state With the exception of E1 and E2,
F Quality assessment according to (E1 = L and E2 = H), each address all inputs consist of NOR gates, so
CECC 90000, CECC 90100 and change leads to a new Read or that no pull-up/pull-down resistors
CECC 90111 Write cycle. In a Read cycle, the are required. This gate circuit
F ESD protection > 2000 V data outputs are activated by the allows to achieve low power
(MIL STD 883C M3015.7) falling edge of G, afterwards the standby requirements by activation
F Latch-up immunity > 200 mA data word read will be available at with TTL-levels too.
F Package: SOP28 (300 mil) the outputs DQ0 - DQ7. After the
address change, the data outputs

Pin Configuration Pin Description

n.c. 1 28 VCC
A12 2 27 W (WE)
A7 3 26 E2 (CE2) Signal Name Signal Description
A6 4 25 A8 A0 - A12 Address Inputs
A5 5 24 A9 DQ0 - DQ7 Data In/Out
A4 6 23 A11 E1 Chip Enable 1
A3 7 22 G (OE) Chip Enable 2
E2
8
SOP 21 A10
A2 Output Enable
G
A1 9 20 E1 (CE1)
W Write Enable
A0 10 19 DQ7
VCC Power Supply Voltage
DQ0 11 18 DQ6
VSS Ground
DQ1 12 17 DQ5
n.c. not connected
DQ2 13 16 DQ4
VSS 14 15 DQ3

Top View

November 01, 2001 1

U62H64SA
Block Diagram

A6

Row Decoder
Row Address
Memory Cell
A7 Array

Inputs
A8
A9
A10 128 Rows
A11 64 x 8 Columns
A12

A0

Column Decoder
Column Address

A1
Inputs

A2 DQ0
Sense Amplifier/

Bidirectional Data I/O

A3 DQ1
Write Control Logic
A4 DQ2
A5 DQ3
DQ4
DQ5
Address
Change Clock
Generator DQ6
Detector
DQ7

E2 VCC VSS W G
E1

Truth Table

Operating Mode E1 E2 W G DQ0 - DQ7

Standby/not * L * * High-Z
selected H * * * High-Z
Internal Read L H H H High-Z
Read L H H L Data Outputs Low-Z
Write L H L * Data Inputs High-Z
* H or L

Characteristics

All voltages are referenced to VSS = 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.

Maximum Ratings Symbol Min. Max. Unit

Power Supply Voltage VCC -0.3 7 V

Input Voltage VI -0.3 VCC + 0.5 V
Output Voltage VO -0.3 VCC + 0.5 V
Operating Temperature Ta -40 125 °C
Storage Temperature Tstg -65 150 °C
Output Short-Circuit Current |IOS| 200 mA
at VCC = 5 V and V O = 0 V *
* Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 s.

2 November 01, 2001

 U62H64SA

Recommended
Symbol Conditions Min. Max. Unit
Operating Conditions

Power Supply Voltage VCC 4.5 5.5 V

Data Retention Voltage VCC(DR) 2.0 - V

Input Low Voltage * VIL -0.3 0.8 V

Input High Voltage VIH 2.2 VCC+0.3 V

* -2 V at Pulse Width 10 ns or -1 V at Pulse Width 50 ns

Electrical Characteristics Symbol Conditions Min. Max. Unit

Supply Current - Operating Mode ICC(OP) VCC = 5.5 V

VIL = 0.8 V
VIH = 2.2 V
tcW = 35 ns 50 mA

Supply Current - Standby Mode ICC(SB) VCC = 5.5 V 100 µA

(CMOS level) VE1 = VE2 = VCC - 0.2 V

Supply Current - Standby Mode ICC(SB)1 VCC = 5.5 V 5 mA

(TTL level) VE1 = VE2 = 2.2 V (typ. 2)

Supply Current - Data Retention Mode ICC(DR) VCC(DR) = 3.0 V 50 µA

VE1 = VE2 = VCC(DR) - 0.2 V

Output High Voltage VOH VCC = 4.5 V 2.4 - V

IOH = -4.0 mA
Output Low Voltage VOL VCC = 4.5 V - 0.4 V
IOL = 8.0 mA

Output High Current IOH VCC = 4.5 V - -4.0 mA

VOH = 2.4 V
Output Low Current IOL VCC = 4.5 V 8.0 - mA
VOL = 0.4 V

Input High Leakage Current IIH VCC = 5.5 V - 2 µA

VIH = 5.5 V
Input Low Leakage Current IIL VCC = 5.5 V -2 - µA
VIL = 0V

Output Leakage Current

High at Three-State Outputs IOHZ VCC = 5.5 V - 2 µA
VOH = 5.5 V
Low at Three-State Outputs IOLZ VCC = 5.5 V -2 - µA
VOL = 0V

November 01, 2001 3

U62H64SA

Symbol Min. Max. Unit

Switching Characteristics
Alt. IEC 35 35

Time to Output in Low-Z from

E1 LOW or E2 HIGH tLZCE ten(E) 5 ns
G LOW tLZOE ten(G) 0 ns
W HIGH tLZWE ten(W) 0 ns

Cycle Time
Write Cycle Time tWC tcW 35 ns
Read Cycle Time tRC tcR 35 ns

Access Time
E1 LOW or E2 HIGH to Data Valid tACE ta(E) 35 ns
G LOW to Data Valid tOE ta(G) 15 ns
Address to Data Valid tAA ta(A) 35 ns

Pulse Widths
Write Pulse Width tWP tw(W) 20 ns
Chip Enable to End of Write tCW tw(E) 25 ns

Setup Times
Address Setup Time tAS tsu(A) 0 ns
Chip Enable to End of Write tCW tsu(E) 25 ns
Write Pulse Width tWP tsu(W) 20 ns
Data Setup Time tDS tsu(D) 15 ns

Data Hold Time tDH th(D) 0 ns

Address Hold from End of Write tAH th(A) 0 ns

Output Hold Time from Address Change tOH tv(A) 5 ns

E1 HIGH or E2 LOW to Output in High-Z tHZCE tdis(E) 15 ns

W LOW to Output in High-Z tHZWE tdis(W) 15 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 ns

E1 LOW or E2 HIGH to Power-Up tPU 0 ns

E1 HIGH or E2 LOW to Power-Down tPD 35 ns

Data Retention Mode E1-Controlled Data Retention Mode E2-Controlled

VCC VCC
4.5 V 4.5 V

VCC(DR) ≥ 2 V VCC(DR) ≥ 2 V E2
tDR Data Retention trec
2.2 V 2.2 V 0.8 V 0.8 V
tDR Data Retention trec E1
0V 0V

VE2(DR) ≥ VCC(DR) - 0.2 V or V E2(DR) ≤ 0.2 V VE1(DR) ≥ VCC(DR) - 0.2 V or V E1(DR) ≤ 0.2 V
VCC(DR) - 0.2 V ≤ VE1(DR) ≤ V CC(DR) + 0.3 V VE2(DR) ≤ 0.2 V

Chip Deselect to Data Retention Time tDR: min 0 ns

Operating Recovery Time at VCC(DR) trec: min t cR

4 November 01, 2001

 U62H64SA
Test Configuration for Functional Check

5V
A0 VCC
A1
A2
A3 DQ0
A4

relevant test measurement

481

Input level according to the

DQ1

ment of all 8 output pins

Simultaneous measure-
A5 DQ2
VIH A6 DQ3
A7 DQ4
A8 DQ5
A9 DQ6
VIL A10 DQ7
A11 VO
A12

E1 30 pF1)
E2
W 255
G VSS

1)
In measurement of tdis(E), tdis(W), tdis(G), ten(E), ten(W) , ten(G) the capacitance is 5 pF.

Capacitance Conditions Symbol Min. Max. Unit

VCC = 5.0 V
Input Capacitance CI 8 pF
VI = VSS

f = 1 MHz
Output Capacitance CO 10 pF
Ta = 25 °C

All pins not under test must be connected with ground by capacitors.

IC Code Number

Example
U62H64 S A 35

Type

Access Time
35 = 35 ns

Package
S = SOP

Operating Temperature Range

A = -40 to 125 °C

The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.

November 01, 2001 5

U62H64SA
Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH, Ai-controlled)

tcR
Ai Addresses Valid
ta(A)
DQi Previous Data Valid Output Data Valid
Output
tv(A)

Read Cycle 2 (during Read cycle: W = VIH, G-, E1- or E2-controlled)

tcR
Ai Addresses Valid
tsu(A) ta(E)
E1 ten(E)
tdis(E)
tsu(A) ta(E) tdis(E)

E2 ten(E)
ta(G)
G
tdis(G)
ten(G)
DQi High-Z
Output Output Data Valid
tPU* tPD*
ICC(OP)
50 % 50 %
ICC(SB)

* The same applies to E1

Write Cycle 1 (W-controlled)

tcW
Ai Addresses Valid
tsu(E) th(A)
E1

E2 tsu(E)
tsu(A) tw(W)
W
tsu(D) th(D)
DQi
Input Input Data Valid
tdis(W)
ten(W)
DQi High-Z
Output

6 November 01, 2001

 U62H64SA
Write Cycle 2 (E1-controlled)

tcW
Ai Addresses Valid
tsu(A) tw(E) th(A)
E1

E2 tsu(E)
E2 tsu(W)
W
tsu(D) th(D)
DQi
Input Input Data Valid
tdis(W)
ten(E)
DQi High-Z
Output

Write Cycle 3 (E2-controlled)

tcW
Ai Addresses Valid
tsu(E) th(A)

E1
tsu(A)

tw(E)
E2
tsu(W)
W
tsu(D) th(D)
DQi
Input Data Valid
Input tdis(W)
ten(E)
DQi High-Z
Output

undefined L- or H-level

The information describes the type of component and shall not be considered as assured characteristic. Terms of
delivery and rights to change design reserved.

November 01, 2001 7

 U62H64SA

LIFE SUPPORT POLICY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.

LIMITED WARRANTY

The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.

November 01, 2001 Zentrum Mikroelektronik Dresden AG

Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: [email protected] • http://www.zmd.de