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Lecture-52 Strobed Output Mode

The document describes how to use an 8255A programmable peripheral interface (PPI) chip to transfer data between two systems in strobed output mode. System 1 programs its PPI port A to output mode to send data, while system 2 programs its port A to input mode to receive data. The output and acknowledge lines of the two ports are connected to synchronize the transfer, generating interrupts on both systems when data is ready or received. Timing diagrams and flow charts show the data transfer process.

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Shrey Misra
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
37 views

Lecture-52 Strobed Output Mode

The document describes how to use an 8255A programmable peripheral interface (PPI) chip to transfer data between two systems in strobed output mode. System 1 programs its PPI port A to output mode to send data, while system 2 programs its port A to input mode to receive data. The output and acknowledge lines of the two ports are connected to synchronize the transfer, generating interrupts on both systems when data is ready or received. Timing diagrams and flow charts show the data transfer process.

Uploaded by

Shrey Misra
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Lecture-52

Strobed Output Mode


Fig.9.17a and 9.17b illustrate on 8255A set up with both port A & B
as mode-1 output.
Group A
Mode 1 Output
8
PORT A PA7-PA0
INTE
A F/F PC6 ACKA
PC7 OBFA

WR
PC3 INTRA
2
PC4, PC5 I/O

Fig.9.17a 8255A Group A Programmed in Mode-1 Strobed Output Mode

The control word to program PORT A in strobed output mode is


D7 D6 D5 D4 D3 D2 D1 D0
Mode Group A PA PCU Gp B PB PCL
1 0 1 0 1/0 X X X

PORT B may be programmed in mode-0 or in mode-1. In case PC6


bit is reset, the interrupt INTRA will be disabled. If the group A is
programmed in strobed output mode, the unused PORT C (Upper)
lines PC5 & PC4 are not used as control or status lines and, therefore,
they can be used as either input or output. Bit-3 of the control word
determines whether these lines are input or output.
Output control definitions:
The functions of the PORT C lines used for group A control as
determined by the mode are described below.
PC7 ( OBF A): Output buffer full for PORT A. When data is written into
port A by the CPU, this signal goes low to indicate that data is
available at port A. The data is latched in PORT A buffer and also
available at the output lines.
PC6 (ACK A): Acknowledge input signal for PORT A. When this
signal goes low it indicates that an external device has accepted the
data that has been written to output PORT A. This signal going low,
will reset the OBF A signal back HIGH indicating that the data has
been accepted by the output device.
PC3 (INTR A): Interrupt request for PORT A. This bit is set HIGH
when ACK A goes HIGH after a data transfer provided its interrupt
enable flip-flop was set earlier. This flip-flop can be set/reset using
PC6 bit of PORT C in bit set/reset mode. This signal can be used as
an interrupt to indicate that data sent earlier has been accepted by an
external device. This means that the CPU can now load the next data
into port A.

Similarly, the functions of the PORT C lines used for group B control
are described below:
PC1 ( OBF B): Output buffer full for PORT B.
PC2 (ACK B): Acknowledge input signal for PORT B.
PC0 (INTR B): Interrupt request for PORT B.
The internal interrupt enable flip-flop INTE F/F can be set/reset using
bit set/reset of PC2.
Group B
Mode 1 Output
8
PORT B PB7-PB0
INTE
B F/F PC2 STBB
PC1 OBFB

WR
PC0 INTRB
1
PC3 I/O

Fig.9.17b 8255A Group B Programmed in Mode-1 Strobed Output Mode

The control word to program PORT B in strobed input mode is


D7 D6 D5 D4 D3 D2 D1 D0
Mode Group A PA PCU Gp B PB PCL
1 X X X X 1 0 1/0

PORT A may be programmed in other mode. In case PC2 bit is reset,


the interrupt INTRB will be disabled. The unused PCL line PC3 can be
programmed in input or output. Bit-0 of the control word determines
whether these lines are input or output.

Let us consider an output device is to be interfaced with the system


through group A programmed in output mode. The basic output
timing diagram is a shown in fig. Whenever 8255A is programmed in
mode 1 (output), the INTR signal goes HIGH if internal INTE flip-flop
is set be the corresponding bit PC6. If CPU interrupt is enabled, it
interrupts the processor. The CPU, which has been interrupted by
this signal, transfers the control to interrupt service subroutine. In ISS,
the processor writes the data to port A buffer and the data is latched
in port buffer. The WR going low reset the INTR. Once the data is
written to PORT A, the OBF A line goes low indicating that data has
been latched in buffer and is available at the output lines. The
external device takes its own time to read the data from the port latch.

INTRA

WR

OBFA

ACKA

PA7-PA0 Valid Data

Fig.9.18 Timing Waveform of Group A Programmed in Mode-1 Output Mode

When the external device has read the data, it acknowledges it by


sending ACK A low. The trailing edge of ACK A causes OBF A to go
HIGH. The empty output buffer (OBF A high) together with WR high
and ACK A high reinitiates the INTR A (high) and the complete
process is recycled when CPU accepts this interrupt. The OBF A can
also be reset by the CPU. If it is high the buffer is empty and the next
data can be written to 8255A.

Example-5
Let the data is to be transferred from microprocessor based
system ‘1’ to another system ‘2. Let this data transfer is to done
through 8255A ports programmed in strobed mode. The two systems,
each having 8255A can be connected as shown in figure below:
8255 A GroupA 8255 A GroupA
Output Mode Input Mode
PORT 8 PORT
A A
OBFA STBA
PC7 PC4

1 2
ACKA IBFA
PC6 PC5

INTRA INTRA
PC3 PC3

RST 6.5 RST 6.5

Fig.9.19 Data Transfer from one System to another System Through 8255A

One of the 8022The output and input ports of the two systems, acting
as data lines, are connected. The OBF of system ‘1’ is connected to
STB of system ‘2’. The IBF of system ‘2’ is connected to ACK of
system ‘1’ through inverter. The interrupt outputs are connected to
any interrupt of the system. Here, they are connected to RST6.5.
INTRA1

WR1

OBFA1

STBA2

IBFA2

ACKA1

INTRA2

RD2

PA7-PA0 Valid Data

Fig.9.18 Timing Waveform of Group A Programmed in Mode-1 for Data


Transfer from System 1 to System 2
As and when system ‘1’ is programmed in output mode and the INTE
F/F is enabled, it generates an interrupt for the processor. Since the
processor interrupt is already enabled, the processor is interrupted.
The control is transferred to ISS in which processor outputs the data
to PORT A. The WR signal going low resets the interrupt INTR. Once
the data is latched, the OBF becomes active low. It acts as a STB for
system ‘2’ PORT A. The data available on PORT A lines will be
latched in PORT A buffer of system ‘2’. The IBF signal output of
system ‘2’ becomes active high. It does two things. First, it makes the
ACK input of system ‘1’ active through inverter which, in turn, clears
the buffer and OBF signal becomes high. Second, it generates the
interrupt for system ‘2’ as its INTE F/F has already been enabled. The
processor of system ‘2’ is interrupted and the control is transferred to
ISS where it reads the data from PORT A buffer. Once the data is
read from PORT A buffer, buffer becomes empty and IBF signal of
PORT A becomes low. This, in turn, makes ACK inactive high. This is
the end of the process. Again the system ‘1’ interrupt is generated
and the process is repeated till all the data from system ‘1’ is
transmitted to system ‘2’ through PORT A of the systems. The
waveforms for during data transfer are shown in fig.
The flow charts for data transfer in this manner are given in
Fig.9.21(a) and (b) for system’1’ to system ‘2’.
Main 1 Main 2

Initialize 8255A Initialize 8255A


Group A in Mode1 Group A in Mode1
PORT A Output PORT A Input

Unmask RST6.5 Unmask RST6.5

Set INTE F/F Set INTE F/F

Enable Interrupt Enable Interrupt

Halt Halt

ISS1 ISS2

Output Data Input Data

Return Return

Fig.9.21 Flow Charts for Data Transfer from System 1 to System 2

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