LOGIC CIRCUITS & SWITCHING THEORY

CHAPTER 4 Standard Combinational Logic

Circuits

COMBINATIONAL LOGIC
- implemented using LOGIC GATES only
- depends only in existing conditions to produce the outputs.

SEQUENTIAL LOGIC
- Consists of logic gates and memory devices or elements such as FLIP-FLOPS
- outputs depend not only on current existing input conditions but to previous
inputs as well.

1. HALF ADDER
- One of the most basic building blocks of a calculator or computer circuits.
- Used to add two bits in binary fashion
- Two input bits are augend and addend and two output bits for sum and carry.

Sum shows 3-input EX-OR

Carry shows logic 1 when either the first carry OR the second carry is a logic 1.

2. FULL ADDER
- Performs binary addition of three bits.
- Three input bits are augend and addends and two output bits for sum and carry.

3. BINARY ADDER
A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascade, with
the output carry from each full adder connected to the input carry of the next full
adder in the chain.

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The signal from the possible input carry from C to the output carry
propagates through an AND gate and an OR gate, which constitute two gate
levels.

If there are four full adders in the adder, the output carry C4 would have 2 *
4 = 8 gate levels from C0 to C4.
For an n-bit adder, there are 2 n gate levels for the carry to propagate from
input to output.
• employ faster gates with reduced delays
• Increase the complexity of the equipment in such a way that the carry delay
time is reduced

5. CARRY LOOK-AHEAD LOGIC

Gi is called a carry generate , and it produces a carry of 1 when both Ai and
Bi are 1, regardless of the input carry Ci.

Gi = Ai Bi

Pi is called a carry propagate , because it determines whether a carry into

stage i will propagate into next stage i+1 (i.e., whether an assertion of Ci will
propagate to an assertion of Ci+1 )

Pi = Ai ⊕ Bi

4. CARRY PROPAGATION
The addition of two binary numbers in parallel implies that all the bits of the
augend and addend are available for computation at the same time.
As in any combinational circuit, the signal must propagate through the gates
before the correct output sum is available in the output terminals.
The total propagation time is equal to the propagation delay of a typical gate,
times the number of gate levels in the circuit.

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Carry Outputs: 6. HALF SUBTRACTOR

Since the Boolean function for each output carry is expressed in sum-of- - Used to Subtract two bits in binary fashion. Difference = A - B
products form, each carry function can be implemented with one level of AND - Two input bits are minuend and subtrahend and two output bits for difference
gates followed by an OR gate. and borrow.

7. FULL SUBTRACTOR
- Performs binary subtraction of 3 bits. Difference = A – B - C
- Three input bits are minuend and subtrahends and 2 output bits for difference
and borrow.
- Difference shows 3-input EX-OR
- Borrow shows logic 1 when either the first borrow OR the second borrow is a
logic 1.

This circuit can add in less time because C4 does not have to wait for C3,
C2 and C1 to propagate; in fact, C4 is propagated at the same time as C1, C2
and C3. This gain in speed of operation is achieved (2-gate level) at the expense
of additional complexity (hardware).

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The 2’s complement can be obtained by taking the 1’s complement and
adding 1 to the least significant pair of bits. The 1’s complement can be
implemented with inverters, and a logic 1 (+5v) can be added to the sum through
the input carry.

 When the difference is a negative number, take the 2’s complement and affix the
negative sign.

8. BINARY SUBTRACTOR
The subtraction of unsigned binary numbers A - B can be done by taking the XNOR is used as a Controlled Inverter and
2’s complement of B and adding it to A. C4 controls the 1’s complement and plus 1 OR passage of SN

It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of the next full adder in
the chain.

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 When the difference is a negative number, take the 2’s complement and affix the
negative sign.

• Invalid codes are corrected by the adding 6 to the invalid BCD code.
• Valid codes but giving the wrong answer is indicated by the carry out of the
end-carry bit C4=1 of the 4-bit full adder and is corrected by the adding 6 to
the wrong BCD code.
XOR is used as a Controlled Inverter and
C4 controls the 1’s complement and plus 1 OR passage of SN

9. BCD ADDER
Computers or calculators that perform arithmetic operations directly in the
decimal number system represent them in binary-coded decimal BCD form.
BCD uses 4-bit code to represent decimal digits 0 to 9, but 10 to 15 are
considered invalid BCD codes.
A decimal adder requires a minimum of nine inputs and five outputs, since
four bits are required to code each decimal digit and the circuit must have an
input and output carry.

Sums of BCD digits equal to 9 or less than 9 already gives valid answers.

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10. BCD SUBTRACTOR When the initial difference is a negative number as indicated by the top
The subtraction of unsigned BCD numbers A - B can primarily be done by C4=0, take the 2’s complement of the initial difference.
taking the 2’s complement of B and adding it to A. Then check the result for invalid codes, and subtract 6 from the invalid code.
When the difference is a negative number, take the 2’s complement and affix
the negative sign.
Invalid digits shall be corrected by subtracting 6 from the invalid digits as a
whole.

The 2’s complement of the subtrahend takes all bits of the decimal digits.
Check first if difference is negative to apply 2’s complement, then check for
Invalid codes which are corrected by the Subtracting 6.

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The output of the partial products of each AND gate is added to the partial
product of the previous level shifted left each time to form new partial products.
The last level produces the product.
For A-multiplier bits and B-multiplicand bits, we need:
(A x B) AND gates and (A-1) B-bit adders to produce the required
product of (A + B) bits

Components needed:
We need 12 AND gates and 2 Four-bit adders to produce a product of 7 bits.
11. BINARY MULTIPLICATION
The multiplicand is multiplied by each bit of the multiplier, starting from the
least significant bit. Each such multiplication forms a partial product.
Successive partial products are shifted one position to the left. The final
product is obtained from the sum of the partial products.

The partial product operation are identical to AND operation.

The sum of the partial products shall use HALF ADDERS.
The least significant bit of the product does not have to go through the
adder. It is formed by the output of the first AND gate.

N-bit BINARY MULTIPLIER 12. THREE-STATE LOGIC

Each bit of the multiplier (A) is ANDed with each bit of the multiplicand (B) in Digital circuits that exhibit three states. Two of the state are logic 0 and logic
as many levels as there are bits in the multiplier. 1 signals while the third state is a HIGH IMPEDANCE STATE that is not
available in other gates.

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HIGH IMPEDANCE STATE: 13. DECODER

• The logic circuit behaves like an open circuit which means that the output Discrete quantities of information are represented in digital systems using
appears disconnected. binary codes of N-bits that is capable of representing 2N distinct coded elements.
• The circuit has no logic significance. A decoder converts coded binary information from N-input lines and ACTIVATES
• The circuit connected to its output is not affected by the inputs to the gate. ONLY THE OUTPUT THAT CORRESPONDS TO THE INPUT CODE, out of the
possible maximum of 2N unique M-output lines or less.

A number of tri-state outputs can be connected with wires to form a common

line without resulting to contention.

Example:
Design a logic circuit using active high tri-state logic that could perform the
following:
Solution:
Each of the output QN (where N is a decimal number) represents one of the
Since there are four different
Control minterms of the input variables.
C1 C2 Operation output required that are triggered by
Output Each of the 2N AND gates generates one of the minterms together with the
different control signals from C1 and
0 0 1 1 inverters that complement the inputs.
C2, connect the output of each logic
0 1 1 A or B The output whose value is logic 1 represents the minterms of the binary
operation to the input of each tri-state
1 0 1 A and B number currently available in the input lines.
logic.
1 1 1 0 Take the SOP of C1 and C2
for the control output signal.

Answer:

The tri-state outputs can be

connected to form a common line
without resulting to contention as
long as each tri-state is enabled
only if all other tri-states are
disabled at the same time.

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 DECODER with Enable inputs 3-Line-to-8-Line Decoder with enable

Some decoders use NAND gates that provide a complemented output form, The ENABLE-AND gate’s output (Enable
(Active-Low Outputs) and INVERTERS to provide one or more complemented Signal) is connected to each of the input
enable inputs (Active-Low ENABLE Inputs) that control the circuit operation. of the 8 NAND gates.
Outputs are Active Low
If either E0=1 OR E1=1 OR E2=0, then the
circuit is disabled, and all outputs are
equal to 1.

 Generating a 4x16 Decoder

Design a 1-of-16 decoder using two 1-of-8 decoder ICs 74LS138 with
enable.
Hence, use one of the enable inputs to provide the Most Significant Bit
position and another as Master Enable.

The decoder is enable when E=0, and only one output can be equal to logic
0 at any given time, while all other outputs are equal to logic 1.
The circuit is disabled when E=1 regardless of the values of the inputs, and
none of the outputs are equal to logic 0.

4-Line-to-16-Line Decoder

 Binary-to-Octal Decoder
1-of-8 decoder IC 74LS138 with enable. Note that E2 is active high while E1
and E0 are both active low enable inputs.

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Example:
Design a Full-Adder circuit using a 3-Line-to-8-Line Decoder and OR gates.

Solution:
Any Boolean function in SOP format of N-inputs and M-outputs can be
implemented by a N-to-2N-DECODER and M-input OR gates.
The inputs to each OR gate are selected from the decoder outputs according
to the list of minterms of each function.
Sum (x, y, z) = ∑ (1, 2, 4, 7)
Carry (x, y, z) = ∑ (3, 5, 6, 7)

Note that only one QN shall be enabled at a time while all others are disabled.

 BCD-to-7-Segment Decoder Truth Table of 74LS46 (Common Cathode)

 BCD-to-7-Segment Decoder
Used to convert a 4-bit BCD input into its decimal digit equivalent by allowing = Blanking Input/
current to pass through the appropriate segments display. Ripple Blanking
The logic is more complicated than normal decoders because each output is Output
activated for more than one combination of inputs. = Ripple Blanking
input
= Lamp Test input

Note:
A = A3
B = A2
C = A1
D = A0

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14. ENCODER  Priority Encoder

Performs the inverse operation of a decoder. Includes the necessary logic to ensure that when two or more inputs are
An encoder has 2N Input Lines or less, ONLY ONE OF WHICH IS activated, the output code will correspond to the highest decimal-numbered
ACTIVATED AT A GIVEN TIME and has N-output lines that generates binary input.
codes corresponding to the input that was activated.
4-Line-to-2-Line Priority Encoder

A0 does not affect the higher input.

When A3 is activated, its code (11) is already dominant of A1 (01) and A2 (10).
But when A2 and A1 are activated at the same time, it will result to a code of
binary 11, which is a wrong code. So A2 should control the passage of A1 through
the upper OR gate.

Analysis suggests that:

When A2 = 0,
A1 is allowed to pass through, X = A1
When A2 = 1,
A1 should be disabled to zero, X = 0

4-Line-to-2-Line Priority Encoder

The higher the subscript number, the higher the priority of the input.
Truth Table:

Each of the input represents one of the minterms of the output variables.
The M-outputs OR gates make up one of the output minterms.
The input AN (where N is a decimal number) whose value is logic 1
represents the minterms of the binary number currently available on the output
lines.

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The x’s in the input columns are useful for representing a truth table in
condensed form.
Instead of listing all 16 minterms of four variables, the truth table uses an x
to represent either 1 or 0 (don’t care).

 Octal-to-Binary Priority Encoder

The higher input would control the lower input bits.
Use of AND gate with INVERTER for the controlling input. The other input to
the AND gate is the controlled input.
Multiple control signals will share as inputs of an OR gate.

15. MULTIPLEXER
A digital multiplexer or DATA SELECTOR is a logic circuit that accepts
several digital data inputs and selects one of them at any given time to pass on
to the output.
The routing of the desired data from input to the output is controlled by
SELECT inputs (often referred to as ADDRESS inputs).

It acts like a digitally-controlled multi-position switch where the SELECT

input code determines which input is transmitted to the output Z.

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The AND gates and the inverters resemble a decoder, and indeed, they
decode the selection input lines.

In general, a 2n-to-1-line
multiplexer is constructed from
an n-to-2n decoder by adding
2n data input lines to it, one to
each AND gate. The outputs of
the AND gates are applied to a
single OR gate.

Think of this multiplexer as being a simple two-input multiplexer, but each

input is four lines and the output is four lines.
The four output lines switch back and forth between the two sets of four
input lines under the control of one select input.

Applications include data selection, data routing, operation sequencing,

parallel-to-serial conversion, waveform generation, & logic-function generation.

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 Quad 2-input Multiplexer used as DATA ROUTER

The 74ALS157 can be used to route data from one of several sources to one
destination.
The application selects and display the contents of either of two BCD
counters using a single set of decoder/drivers and LED displays.
The purpose of the multiplexing technique is to timeshare the
decoder/drivers and display circuits between the two counters rather than have a
separate set of decoder / drivers and displays for each counter. The waveforms are for the case where:
System for displaying two multi-digit BCD counters one at a time, let say an X7X6X5X4X3X2X1X0 = 10110101
up-counter & down-counter.

 Multiplexer used as a LOGIC FUNCTION GENERATOR

 Multiplexer used as PARALLEL-TO-SERIAL CONVERTER

Many digital systems process binary data in parallel form (all bits Z = AB’C’ + A’BC’ + ABC
simultaneously) because it is faster.
But when data are to be transmitted over relatively long distances, however,
the parallel arrangement is undesirable because it requires a large number of
This cannot be simplified The input variables C, B, A are connected
transmission lines.
either algebraically or by K to respectively as SELECT Inputs, so that
For this reason, binary data or information in parallel form is often converted
mapping, and so its gate the levels on these inputs determine
to serial form before being transmitted to a remote destination.
implementation would require three which data input appears at output Z.
X0 (the LSB) is transmitted first and the X07 (MSB) is transmitted last.
INVERTERs and three AND gates This method of implementation is often
and one OR gate, for a total of 3 more efficient than using separate logic
ICs. gates

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16. DEMULTIPLEXER
A demultiplexer also known as DATA DISTRIBUTOR performs the opposite
of a multiplexer, such that it takes a single input and distributes it over one of N
several outputs.
The routing of the desired DATA INPUT to the whichever output is controlled
by SELECT inputs.

 1-Line-to-2-Line Demultiplexer
It acts like a digitally-controlled multi-position switch where the SELECT
input code determines where the input is transmitted to which output.

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 Multiplexer & Demultiplexer in a Security System Alternative form:

Basic 1-Bit Comparator: It is a combinational logic circuit that
A security monitoring system in an industrial plant, the open/closed status of
Compares one bit to another bit compares two numbers A and B and
many access doors is to be monitored.
Each door controls the state of a switch, and it is necessary to display the determines their relative magnitudes.
state of each switch on LEDs that are mounted on a remote monitoring panel at
the security guard’s station.
The counter is clocked through its eight states 000 through 111, the LEDs
will sequentially indicate the status of the eight doors.

The MUX/DEMUX combination is used to transmit the status of each door to

its LED one at a time (serially) instead of all at once (parallel).

17. COMPARATOR
Compares two unsigned input binary quantities and generates an output to  Four-Bit Comparator
that determine whether one number is greater than, less than, or equal to the A = A3 A2 A1 A0
other number. B = B3 B2 B1 B0
The two numbers are EQUAL if all pairs of significant digits are equal:
A3 = B3, A2 = B2, A1 = B1, and A0 = B0.
1-Bit Comparator Truth Table:
When the numbers are binary, the digits are either 1 or 0, and the equality of
Outp
COMP each pair of bits can be expressed logically with an EXNOR function as:
A
uts
A ARAT >A B
B for i = 0, 1, 2, 3
OR A
<B
DAT =B For equality to exist, all Xi variables must be equal to 1, a condition that
A dictates an AND gate operation of all Xi variables:
Inp
uts

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(A = B) = x3 x2 x1 x0

To know if A is GREATER THAN or LESS THAN B, we inspect the relative

magnitudes of pairs of significant digits, starting from the most significant
position.
If the two digits of a pair are equal, we compare the next lower significant
pair of digits. The comparison continues until a pair of unequal digits is reached
dictates OR function.
If the corresponding digit of A is 1 and that of B is 0, we conclude that A > B.
If the corresponding digit of A is 0 and that
of B is 1, we have A < B. The sequential comparison can be expressed logically
by the two Boolean functions:
(A = B) = x3 x2 x1 x0

 74HC85 4-Bit Comparator

Data Inputs
AAA A BBB B
3 MAGNITU
21 0 321 0
DE

Q Q Q
Outputs
A > A < A =
 Cascading Inputs
B B B Cascading inputs provide a means for expanding the comparison operation
to
more than four bits by cascading two or more four-bit comparators

 74HC85 4-Bit Comparator with Cascading inputs:

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Data Inputs
AAA A B BB B
4-BIT
321 0 321 0
Cas I
A MAGNITU
cadi IIA
>AB DE
ng < B
+
Inp = B Q Outputs
Q Q
5
uts
v A> A< A= Magnitude comparators are also useful in control applications where a
B B B binary number representing the physical variable being controlled (e.g., position,
speed, or temperature) is compared with a reference value.
The comparator outputs are used to actuate circuitry to drive the physical
variable toward the reference value.

18. CODE CONVERTER

A code converter is a logic circuit that changes data presented in one type of
binary code to another type of binary code to make the two systems compatible
even though each uses a different binary code.

 Two-Digit BCD-to-Binary Converter

With Cascading Inputs: The largest two-digit decimal value of 9910 = 1001 1001 in (BCD) is =
11000112 requires only 7 bits in Binary.
(A = B) = x3x2x1x0 ( IA

=B
)

 8-Bit Comparator using 74HC85

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 GRAY TO BINARY CONVERTER

Since each code uses 4 bits to represent a decimal digit, there are 4 inputs
and 4 outputs. Recall that gray code is a non-weighted code.

 BINARY TO GRAY CONVERTER

Since each code uses 4 bits to represent a decimal digit, there are 4 inputs and 4
outputs. Recall that gray code is a non-weighted code.

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