Design of Combinational Logic: Full Adder, Adder, and ALU

1 Today’s goal List 1: Full adder using assigment statementsfa.v

• Learn how to use ISE WebPack. 1 module fa(a, b, cin, s, cout);
2
• Learn the design of combinational logic using Ver- 3 input a, b, cin;
4 output s, cout;
ilog HDL. 5 wire a, b, cin, s, cout;
6
• Learn how to write test benches and perform the simu- 7 assign s = a ˆ b ˆ cin;
lation. 8 assign cout = (a & b) | (b & cin) | (cin & a);
9
10 endmodule
• Learn how to embed a designed circuit into an FPGA.

• Design ALU as a basic component of CPU.

4 Test bench
2 Today’s contents Test bench defines the change of inputs. In List 2, module fa
is instantiated as fa 0.
Step 1 Write full adder(List 1) and its test bench(List 2).

Step 2 Check1 Perform the simulation using the test bench List 2: Test benchfa tb.v for fa.v
to confirm that the full adder works correctly. 1 ‘timescale 1ns / 1ps
2 module fa tb;
Step 3 Check2 Write a UCF(User Constraint File) (List 3), 3
embed it in the FPGA to confirm that the full adder 4 reg a,b,cin;
works in the FPGA correctly. 5 wire s, cout;
6 fa fa0 (.a(a), .b(b), .cin(cin), .s(s), .cout(cout));
7
Step 4 Write full adder using always statement(List 4) and 8 initial begin
confirm that it works correctly by the simulation using 9 a = 0; b = 0; cin = 0;
the test bench(List 2). 10 #100 a = 1; b = 0; cin = 0;
11 #100 a = 0; b = 1; cin = 0;
12 #100 a = 1; b = 1; cin = 0;
Step 5 Check 3 Write 4-bit adder using 4-full adders(List 5) 13 #100 a = 0; b = 0; cin = 1;
and confirm that it works correctly by the simulation 14 #100 a = 1; b = 0; cin = 1;
using its test bench(List 6). 15 #100 a = 0; b = 1; cin = 1;
16 #100 a = 1; b = 1; cin = 1;
17 #100 a = 0; b = 0; cin = 0;
Step 6 Check 4 Write ALU(List 7) and confirm that it works 18 end
correctly by the simulation using its test bench(List 8). 19 endmodule

3 Full adder
Full adder has 3 input bits a,b, cin and 2 output bits s, cout. 5 UCF(User Constraint file)
The sum of 3 input bits are computed and 2 out bits represent
the sum such that s is a lower bit, and count is an upper bit. The UCF defines the mapping between ports of the module
Assignment statements defines continuous assignments. and the pins of an FPGA. NET and LOC correspond to a

1
name of module port, and a name of FPGA pin.

List 3: UCF for fa.ucf (Spartan-3A/AN)

1 # SWITCH
2 NET ”a” LOC = ”V8” | IOSTANDARD = LVTTL | PULLUP; List 5: 4-bit adder using adder4.v
3 NET ”b” LOC = ”U10” | IOSTANDARD = LVTTL | PULLUP 1 module adder4(a, b, s);
; 2
4 NET ”cin” LOC = ”U8” | IOSTANDARD = LVTTL | 3 input [3:0] a,b;
PULLUP; 4 output [3:0] s;
5 5 wire [2:0] c;
6 # LED 6
7 NET ”s” LOC = ”R20” | IOSTANDARD = LVTTL | SLEW = 7 fa fa0(.a(a[0]),.b(b[0]),.cin(0),.s(s[0]),.cout(c[0]));
SLOW | DRIVE = 8; 8 fa fa1(.a(a[1]),.b(b[1]),.cin(c[0]),.s(s[1]),.cout(c[1]));
8 NET ”cout” LOC = ”T19” | IOSTANDARD = LVTTL | 9 fa fa2(.a(a[2]),.b(b[2]),.cin(c[1]),.s(s[2]),.cout(c[2]));
SLEW = SLOW | DRIVE = 8; 10 fa fa3(.a(a[3]),.b(b[3]),.cin(c[2]),.s(s[3]));
11
12 endmodule

6 Always statement
Always statements in List 4 is used to design combinational
logic. “always @ (...)” defines a event list. If the values of
signal (net) in the event list change, the following statement
is executed.

List 6: Test bench for 4-bit adderadder4 tb.v

1 ‘timescale 1ns / 1ps
7 Instantiate modules 2 module adder4 tb;
3
In List 5, module fa is instantiated four times as fa0, fa1, 4 reg [3:0] a,b;
5 wire [3:0] s;
fa2, and fa3. These modules are connected by wires (nets). 6
Instead, we can simply use “ assign s = a+b” instead of using 7 adder4 adder4 0(.a(a),.b(b),.s(s));
four fa’s. 8
9 initial begin
10 a = 4’b0000; b=4’b0000;
11 #100 a = 4’b0001;
12 #100 a = 4’b0010;
List 4: Full adder using always statementfa.v 13 #100 b = 4’b0111;
14 #100 a = 4’b1101;
1 module fa(a, b, cin, s, cout); 15 #100 a = 4’b1011;
2 16 #100 b = 4’b1001;
3 input a, b, cin; 17 #100 b = 4’b1110;
4 output s, cout; 18 #100a = 4’b0000; b=4’b0000;
5 reg s, cout; 19 end
6 20
7 always @(a or b or cin) 21 endmodule
8 begin
9 s = a ˆ b ˆ cin;
10 cout = (a & b) | (b & cin) | (cin & a);
11 end
12
13 endmodule

2
8 ALU
ALU (List 7) is used to compute a selected function. ALU List 7: ALU alu.v
has 3 input ports, f(5 bits), a(16 bits), b(16 bits), and one 1 ‘define ADD 5’b00000
output port s. f is used to select a function (operation), and 2 ‘define SUB 5’b00001
the resulting value is output from s. We assume that a, b, 3 ‘define MUL 5’b00010
s are signed integers (2’s complement). However, array of 4 ‘define SHL 5’b00011
5 ‘define SHR 5’b00100
bits (vector) in Verilog HDL is handled as unsigned integers. 6 ‘define BAND 5’b00101
Thus, for relational operators, we add 16’h8000 to a and b to 7 ‘define BOR 5’b00110
get correct results. 8 ‘define BXOR 5’b00111
9 ‘define AND 5’b01000
10 ‘define OR 5’b01001
11 ‘define EQ 5’b01010
9 Homeworks 12 ‘define NE 5’b01011
13 ‘define GE 5’b01100
14 ‘define LE 5’b01101
In your report, you must show enough explanation and the 15 ‘define GT 5’b01110
simulation results. 16 ‘define LT 5’b01111
17 ‘define NEG 5’b10000
Homework 1 Design an 8-bit adder using 8 full adders, and 18 ‘define NOT 5’b10001
write its test bench. Perform the simulation to confirm 19 ‘define BNOT 5’b10010
20
that the 8-bit adder works correctly. 21 module alu(a, b, f, s);
22
Homework 2 Write test benches for ALU to confirm that 23 input [15:0] a, b;
each of 19 functions works correctly. You should choose 24 input [4:0] f;
25 output [15:0] s;
various input b and a for each functin. For example, 26 reg [15:0] s;
for bianry arithmetic function, you should choose {b > 27 wire [15:0] x,y;
0, b < 0} × {a > 0, a < 0} (4 cases), and the case that 28
the reult is overflow. 29 assign x = a + 16’h8000;
30 assign y = b + 16’h8000;
31
32 always @(a or b or x or y or f)
33 case(f)
34 ‘ADD : s = b + a;
35 ‘SUB : s = b − a;
36 ‘MUL : s = b ∗ a;
37 ‘SHL : s = b << a;
38 ‘SHR : s = b >> a;
39 ‘BAND: s = b & a;
40 ‘BOR : s = b | a;
41 ‘BXOR: s = b ˆ a;
42 ‘AND : s = b && a;
43 ‘OR : s = b || a;
44 ‘EQ : s = b == a;
45 ‘NE : s = b != a;
46 ‘GE : s = y >= x;
47 ‘LE : s = y <= x;
48 ‘GT : s = y > x;
49 ‘LT : s = y < x;
50 ‘NEG : s = −a;
51 ‘BNOT : s = ˜a;
52 ‘NOT : s = !a;
53 default : s = 16’hxxxx;
54 endcase
55
56 endmodule

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 Table 1: Specification of ALU(Arithmetic and Logic Unit)

function f outputs
binary arithmetic ADD 00000 b + a (addition)
SUB 00001 b − a (subtraction)
MUL 00010 b * a (multiplication)
shift SHL 00011 b << a (left shift)
SHR 00100 b >> a (right shift)
bitwise BAND 00101 b & a (bitwise and)
BOR 00110 b | a (bitwise or)
BXOR 00111 b ^ a (bitwise xor)
logic AND 01000 b && a (logical and)
OR 01001 b || a (logical or)
relational EQ 01010 b==a (b is equal toa)
NE 01011 b!=a (b is not equal toa)
GE 01100 b>=a (b is larger than or euqal to a)
LE 01101 b<=a (b is smaller than or equal to a)
GT 01110 b>a (b is larger than a)
LT 01111 b<a (b is smaller than a)
unary arithmetic NEG 10000 −a (negation)
bitwise BNOT 10001 ~a (bitwise not)
logic NOT 10010 !a (logical not)

List 8: Test bench foralu tb.v

1 ‘timescale 1ns / 1ps
2
3 module alu tb;
4
5 reg [15:0] a,b;
6 reg [4:0] f;
7 wire [15:0] s;
8
9 alu alu0(.a(a),.b(b),.f(f),.s(s));
10
11 initial begin
12 a = −3; b= 3; f = 5’b01100;
13 #100 a = −2;
14 #100 a = −1;
15 #100 a = 0;
16 #100 a = 1;
17 #100 a = 2;
18 #100 a = 3;
19 #100 a = 4;
20 #100 a = 5;
21 #100 a = 6;
22 end
23
24 endmodule